1b8b572e1SStephen Rothwell /* 2b8b572e1SStephen Rothwell * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3b8b572e1SStephen Rothwell */ 4b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_PPC_ASM_H 5b8b572e1SStephen Rothwell #define _ASM_POWERPC_PPC_ASM_H 6b8b572e1SStephen Rothwell 7b8b572e1SStephen Rothwell #include <linux/stringify.h> 8b8b572e1SStephen Rothwell #include <asm/asm-compat.h> 9b8b572e1SStephen Rothwell #include <asm/processor.h> 1016c57b36SKumar Gala #include <asm/ppc-opcode.h> 11cf9efce0SPaul Mackerras #include <asm/firmware.h> 122c86cd18SChristophe Leroy #include <asm/feature-fixups.h> 131e688dd2SChristophe Leroy #include <asm/extable.h> 14b8b572e1SStephen Rothwell 15e3f2c6c3SMichael Ellerman #ifdef __ASSEMBLY__ 16b8b572e1SStephen Rothwell 17b8b572e1SStephen Rothwell #define SZL (BITS_PER_LONG/8) 18b8b572e1SStephen Rothwell 19b8b572e1SStephen Rothwell /* 20aebd1fb4SNicholas Piggin * This expands to a sequence of operations with reg incrementing from 21aebd1fb4SNicholas Piggin * start to end inclusive, of this form: 22aebd1fb4SNicholas Piggin * 23aebd1fb4SNicholas Piggin * op reg, (offset + (width * reg))(base) 24aebd1fb4SNicholas Piggin * 25aebd1fb4SNicholas Piggin * Note that offset is not the offset of the first operation unless start 26aebd1fb4SNicholas Piggin * is zero (or width is zero). 27aebd1fb4SNicholas Piggin */ 28aebd1fb4SNicholas Piggin .macro OP_REGS op, width, start, end, base, offset 29aebd1fb4SNicholas Piggin .Lreg=\start 30aebd1fb4SNicholas Piggin .rept (\end - \start + 1) 31aebd1fb4SNicholas Piggin \op .Lreg, \offset + \width * .Lreg(\base) 32aebd1fb4SNicholas Piggin .Lreg=.Lreg+1 33aebd1fb4SNicholas Piggin .endr 34aebd1fb4SNicholas Piggin .endm 35aebd1fb4SNicholas Piggin 36aebd1fb4SNicholas Piggin /* 379d54a5ceSRohan McLure * This expands to a sequence of register clears for regs start to end 389d54a5ceSRohan McLure * inclusive, of the form: 399d54a5ceSRohan McLure * 409d54a5ceSRohan McLure * li rN, 0 419d54a5ceSRohan McLure */ 429d54a5ceSRohan McLure .macro ZEROIZE_REGS start, end 439d54a5ceSRohan McLure .Lreg=\start 449d54a5ceSRohan McLure .rept (\end - \start + 1) 459d54a5ceSRohan McLure li .Lreg, 0 469d54a5ceSRohan McLure .Lreg=.Lreg+1 479d54a5ceSRohan McLure .endr 489d54a5ceSRohan McLure .endm 499d54a5ceSRohan McLure 509d54a5ceSRohan McLure /* 51b8b572e1SStephen Rothwell * Macros for storing registers into and loading registers from 52b8b572e1SStephen Rothwell * exception frames. 53b8b572e1SStephen Rothwell */ 54b8b572e1SStephen Rothwell #ifdef __powerpc64__ 55aebd1fb4SNicholas Piggin #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0 56aebd1fb4SNicholas Piggin #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0 57aebd1fb4SNicholas Piggin #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base) 58aebd1fb4SNicholas Piggin #define REST_NVGPRS(base) REST_GPRS(14, 31, base) 59b8b572e1SStephen Rothwell #else 60aebd1fb4SNicholas Piggin #define SAVE_GPRS(start, end, base) OP_REGS stw, 4, start, end, base, GPR0 61aebd1fb4SNicholas Piggin #define REST_GPRS(start, end, base) OP_REGS lwz, 4, start, end, base, GPR0 62aebd1fb4SNicholas Piggin #define SAVE_NVGPRS(base) SAVE_GPRS(13, 31, base) 63aebd1fb4SNicholas Piggin #define REST_NVGPRS(base) REST_GPRS(13, 31, base) 64b8b572e1SStephen Rothwell #endif 65b8b572e1SStephen Rothwell 669d54a5ceSRohan McLure #define ZEROIZE_GPRS(start, end) ZEROIZE_REGS start, end 679d54a5ceSRohan McLure #ifdef __powerpc64__ 689d54a5ceSRohan McLure #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(14, 31) 699d54a5ceSRohan McLure #else 709d54a5ceSRohan McLure #define ZEROIZE_NVGPRS() ZEROIZE_GPRS(13, 31) 719d54a5ceSRohan McLure #endif 729d54a5ceSRohan McLure #define ZEROIZE_GPR(n) ZEROIZE_GPRS(n, n) 739d54a5ceSRohan McLure 74aebd1fb4SNicholas Piggin #define SAVE_GPR(n, base) SAVE_GPRS(n, n, base) 75aebd1fb4SNicholas Piggin #define REST_GPR(n, base) REST_GPRS(n, n, base) 76b8b572e1SStephen Rothwell 77cbf892baSRohan McLure /* macros for handling user register sanitisation */ 78cbf892baSRohan McLure #ifdef CONFIG_INTERRUPT_SANITIZE_REGISTERS 79cbf892baSRohan McLure #define SANITIZE_SYSCALL_GPRS() ZEROIZE_GPR(0); \ 80cbf892baSRohan McLure ZEROIZE_GPRS(5, 12); \ 81cbf892baSRohan McLure ZEROIZE_NVGPRS() 82cbf892baSRohan McLure #define SANITIZE_GPR(n) ZEROIZE_GPR(n) 83cbf892baSRohan McLure #define SANITIZE_GPRS(start, end) ZEROIZE_GPRS(start, end) 84cbf892baSRohan McLure #define SANITIZE_NVGPRS() ZEROIZE_NVGPRS() 85cbf892baSRohan McLure #define SANITIZE_RESTORE_NVGPRS() REST_NVGPRS(r1) 86cbf892baSRohan McLure #define HANDLER_RESTORE_NVGPRS() 87cbf892baSRohan McLure #else 88cbf892baSRohan McLure #define SANITIZE_SYSCALL_GPRS() 89cbf892baSRohan McLure #define SANITIZE_GPR(n) 90cbf892baSRohan McLure #define SANITIZE_GPRS(start, end) 91cbf892baSRohan McLure #define SANITIZE_NVGPRS() 92cbf892baSRohan McLure #define SANITIZE_RESTORE_NVGPRS() 93cbf892baSRohan McLure #define HANDLER_RESTORE_NVGPRS() REST_NVGPRS(r1) 94cbf892baSRohan McLure #endif /* CONFIG_INTERRUPT_SANITIZE_REGISTERS */ 95cbf892baSRohan McLure 96de79f7b9SPaul Mackerras #define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) 97b8b572e1SStephen Rothwell #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 98b8b572e1SStephen Rothwell #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 99b8b572e1SStephen Rothwell #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 100b8b572e1SStephen Rothwell #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 101b8b572e1SStephen Rothwell #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 102de79f7b9SPaul Mackerras #define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) 103b8b572e1SStephen Rothwell #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 104b8b572e1SStephen Rothwell #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 105b8b572e1SStephen Rothwell #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 106b8b572e1SStephen Rothwell #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 107b8b572e1SStephen Rothwell #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 108b8b572e1SStephen Rothwell 109de79f7b9SPaul Mackerras #define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b 110b8b572e1SStephen Rothwell #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 111b8b572e1SStephen Rothwell #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 112b8b572e1SStephen Rothwell #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 113b8b572e1SStephen Rothwell #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 114b8b572e1SStephen Rothwell #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 115de79f7b9SPaul Mackerras #define REST_VR(n,b,base) li b,16*(n); lvx n,base,b 116b8b572e1SStephen Rothwell #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 117b8b572e1SStephen Rothwell #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 118b8b572e1SStephen Rothwell #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 119b8b572e1SStephen Rothwell #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 120b8b572e1SStephen Rothwell #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 121b8b572e1SStephen Rothwell 122926f160fSAnton Blanchard #ifdef __BIG_ENDIAN__ 123926f160fSAnton Blanchard #define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) 124926f160fSAnton Blanchard #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) 125926f160fSAnton Blanchard #else 126926f160fSAnton Blanchard #define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ 127926f160fSAnton Blanchard STXVD2X(n,b,base); \ 128926f160fSAnton Blanchard XXSWAPD(n,n) 129926f160fSAnton Blanchard 130926f160fSAnton Blanchard #define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ 131926f160fSAnton Blanchard XXSWAPD(n,n) 132926f160fSAnton Blanchard #endif 133b8b572e1SStephen Rothwell /* Save the lower 32 VSRs in the thread VSR region */ 1343ad26e5cSBenjamin Herrenschmidt #define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) 135b8b572e1SStephen Rothwell #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 136b8b572e1SStephen Rothwell #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 137b8b572e1SStephen Rothwell #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 138b8b572e1SStephen Rothwell #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 139b8b572e1SStephen Rothwell #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 1403ad26e5cSBenjamin Herrenschmidt #define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) 141b8b572e1SStephen Rothwell #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 142b8b572e1SStephen Rothwell #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 143b8b572e1SStephen Rothwell #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 144b8b572e1SStephen Rothwell #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 145b8b572e1SStephen Rothwell #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 146b8b572e1SStephen Rothwell 147c51584d5SScott Wood /* 148c51584d5SScott Wood * b = base register for addressing, o = base offset from register of 1st EVR 149c51584d5SScott Wood * n = first EVR, s = scratch 150c51584d5SScott Wood */ 151c51584d5SScott Wood #define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) 152c51584d5SScott Wood #define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) 153c51584d5SScott Wood #define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) 154c51584d5SScott Wood #define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) 155c51584d5SScott Wood #define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) 156c51584d5SScott Wood #define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) 157c51584d5SScott Wood #define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n 158c51584d5SScott Wood #define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) 159c51584d5SScott Wood #define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) 160c51584d5SScott Wood #define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) 161c51584d5SScott Wood #define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) 162c51584d5SScott Wood #define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) 163b8b572e1SStephen Rothwell 164b8b572e1SStephen Rothwell /* Macros to adjust thread priority for hardware multithreading */ 165b8b572e1SStephen Rothwell #define HMT_VERY_LOW or 31,31,31 # very low priority 166b8b572e1SStephen Rothwell #define HMT_LOW or 1,1,1 167b8b572e1SStephen Rothwell #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 168b8b572e1SStephen Rothwell #define HMT_MEDIUM or 2,2,2 169b8b572e1SStephen Rothwell #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 170b8b572e1SStephen Rothwell #define HMT_HIGH or 3,3,3 17150fb8ebeSBenjamin Herrenschmidt #define HMT_EXTRA_HIGH or 7,7,7 # power7 only 172b8b572e1SStephen Rothwell 173d72be892SMichael Neuling #ifdef CONFIG_PPC64 174d72be892SMichael Neuling #define ULONG_SIZE 8 175d72be892SMichael Neuling #else 176d72be892SMichael Neuling #define ULONG_SIZE 4 177d72be892SMichael Neuling #endif 1780b7673c3SMichael Neuling #define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) 1790b7673c3SMichael Neuling #define VCPU_GPR(n) __VCPU_GPR(__REG_##n) 180d72be892SMichael Neuling 181b8b572e1SStephen Rothwell #ifdef __KERNEL__ 1822eda7f11SMichael Ellerman 1832eda7f11SMichael Ellerman /* 1842eda7f11SMichael Ellerman * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit 1852eda7f11SMichael Ellerman * version below in the else case of the ifdef. 1862eda7f11SMichael Ellerman */ 1872eda7f11SMichael Ellerman #ifdef __powerpc64__ 188b8b572e1SStephen Rothwell 18944ce6a5eSMichael Neuling #define STACKFRAMESIZE 256 1900b7673c3SMichael Neuling #define __STK_REG(i) (112 + ((i)-14)*8) 1910b7673c3SMichael Neuling #define STK_REG(i) __STK_REG(__REG_##i) 19244ce6a5eSMichael Neuling 1937d40aff8SChristophe Leroy #ifdef CONFIG_PPC64_ELF_ABI_V2 1946403105bSAnton Blanchard #define STK_GOT 24 195b37c10d1SAnton Blanchard #define __STK_PARAM(i) (32 + ((i)-3)*8) 196b37c10d1SAnton Blanchard #else 1976403105bSAnton Blanchard #define STK_GOT 40 1980b7673c3SMichael Neuling #define __STK_PARAM(i) (48 + ((i)-3)*8) 199b37c10d1SAnton Blanchard #endif 2000b7673c3SMichael Neuling #define STK_PARAM(i) __STK_PARAM(__REG_##i) 20144ce6a5eSMichael Neuling 2027d40aff8SChristophe Leroy #ifdef CONFIG_PPC64_ELF_ABI_V2 2037167af7cSAnton Blanchard 2047167af7cSAnton Blanchard #define _GLOBAL(name) \ 2057167af7cSAnton Blanchard .align 2 ; \ 2067167af7cSAnton Blanchard .type name,@function; \ 2077167af7cSAnton Blanchard .globl name; \ 2087167af7cSAnton Blanchard name: 2097167af7cSAnton Blanchard 210169c7ceeSAnton Blanchard #define _GLOBAL_TOC(name) \ 211169c7ceeSAnton Blanchard .align 2 ; \ 212169c7ceeSAnton Blanchard .type name,@function; \ 213169c7ceeSAnton Blanchard .globl name; \ 214169c7ceeSAnton Blanchard name: \ 215169c7ceeSAnton Blanchard 0: addis r2,r12,(.TOC.-0b)@ha; \ 216169c7ceeSAnton Blanchard addi r2,r2,(.TOC.-0b)@l; \ 217169c7ceeSAnton Blanchard .localentry name,.-name 218169c7ceeSAnton Blanchard 2197167af7cSAnton Blanchard #define DOTSYM(a) a 2207167af7cSAnton Blanchard 2217167af7cSAnton Blanchard #else 2227167af7cSAnton Blanchard 223b8b572e1SStephen Rothwell #define XGLUE(a,b) a##b 224b8b572e1SStephen Rothwell #define GLUE(a,b) XGLUE(a,b) 225b8b572e1SStephen Rothwell 226b8b572e1SStephen Rothwell #define _GLOBAL(name) \ 227b8b572e1SStephen Rothwell .align 2 ; \ 228b8b572e1SStephen Rothwell .globl name; \ 229b8b572e1SStephen Rothwell .globl GLUE(.,name); \ 230bea2dcccSMichael Ellerman .pushsection ".opd","aw"; \ 231b8b572e1SStephen Rothwell name: \ 232b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 233b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 234b8b572e1SStephen Rothwell .quad 0; \ 235bea2dcccSMichael Ellerman .popsection; \ 236b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 237b8b572e1SStephen Rothwell GLUE(.,name): 238b8b572e1SStephen Rothwell 239169c7ceeSAnton Blanchard #define _GLOBAL_TOC(name) _GLOBAL(name) 240169c7ceeSAnton Blanchard 241c1fb0194SAnton Blanchard #define DOTSYM(a) GLUE(.,a) 242c1fb0194SAnton Blanchard 2437167af7cSAnton Blanchard #endif 2447167af7cSAnton Blanchard 245b8b572e1SStephen Rothwell #else /* 32-bit */ 246b8b572e1SStephen Rothwell 247b8b572e1SStephen Rothwell #define _GLOBAL(n) \ 248b8b572e1SStephen Rothwell .globl n; \ 249b8b572e1SStephen Rothwell n: 250b8b572e1SStephen Rothwell 2519715a2e8SAlexander Graf #define _GLOBAL_TOC(name) _GLOBAL(name) 2529715a2e8SAlexander Graf 253ce7d8056SChristophe Leroy #define DOTSYM(a) a 254ce7d8056SChristophe Leroy 255b8b572e1SStephen Rothwell #endif 256b8b572e1SStephen Rothwell 2576f698df1SNicholas Piggin /* 2586f698df1SNicholas Piggin * __kprobes (the C annotation) puts the symbol into the .kprobes.text 2596f698df1SNicholas Piggin * section, which gets emitted at the end of regular text. 2606f698df1SNicholas Piggin * 2616f698df1SNicholas Piggin * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to 2626f698df1SNicholas Piggin * a blacklist. The former is for core kprobe functions/data, the 2636f698df1SNicholas Piggin * latter is for those that incdentially must be excluded from probing 2646f698df1SNicholas Piggin * and allows them to be linked at more optimal location within text. 2656f698df1SNicholas Piggin */ 266c0a51491SNicholas Piggin #ifdef CONFIG_KPROBES 2676f698df1SNicholas Piggin #define _ASM_NOKPROBE_SYMBOL(entry) \ 2686f698df1SNicholas Piggin .pushsection "_kprobe_blacklist","aw"; \ 2696f698df1SNicholas Piggin PPC_LONG (entry) ; \ 2706f698df1SNicholas Piggin .popsection 271c0a51491SNicholas Piggin #else 272c0a51491SNicholas Piggin #define _ASM_NOKPROBE_SYMBOL(entry) 273c0a51491SNicholas Piggin #endif 2746f698df1SNicholas Piggin 275151f2511SAnton Blanchard #define FUNC_START(name) _GLOBAL(name) 276151f2511SAnton Blanchard #define FUNC_END(name) 277151f2511SAnton Blanchard 278b8b572e1SStephen Rothwell /* 279b8b572e1SStephen Rothwell * LOAD_REG_IMMEDIATE(rn, expr) 280b8b572e1SStephen Rothwell * Loads the value of the constant expression 'expr' into register 'rn' 281b8b572e1SStephen Rothwell * using immediate instructions only. Use this when it's important not 282b8b572e1SStephen Rothwell * to reference other data (i.e. on ppc64 when the TOC pointer is not 283e31aa453SPaul Mackerras * valid) and when 'expr' is a constant or absolute address. 284b8b572e1SStephen Rothwell * 285b8b572e1SStephen Rothwell * LOAD_REG_ADDR(rn, name) 286b8b572e1SStephen Rothwell * Loads the address of label 'name' into register 'rn'. Use this when 287b8b572e1SStephen Rothwell * you don't particularly need immediate instructions only, but you need 288b8b572e1SStephen Rothwell * the whole address in one register (e.g. it's a structure address and 289b8b572e1SStephen Rothwell * you want to access various offsets within it). On ppc32 this is 290b8b572e1SStephen Rothwell * identical to LOAD_REG_IMMEDIATE. 291b8b572e1SStephen Rothwell * 2921c49abecSKevin Hao * LOAD_REG_ADDR_PIC(rn, name) 2931c49abecSKevin Hao * Loads the address of label 'name' into register 'run'. Use this when 2941c49abecSKevin Hao * the kernel doesn't run at the linked or relocated address. Please 2951c49abecSKevin Hao * note that this macro will clobber the lr register. 2961c49abecSKevin Hao * 297b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE(rn, name) 298b8b572e1SStephen Rothwell * ADDROFF(name) 299b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 300b8b572e1SStephen Rothwell * register 'rn'. ADDROFF(name) returns the remainder of the address as 301b8b572e1SStephen Rothwell * a constant expression. ADDROFF(name) is a signed expression < 16 bits 302b8b572e1SStephen Rothwell * in size, so is suitable for use directly as an offset in load and store 303b8b572e1SStephen Rothwell * instructions. Use this when loading/storing a single word or less as: 304b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE(rX, name) 305b8b572e1SStephen Rothwell * ld rY,ADDROFF(name)(rX) 306b8b572e1SStephen Rothwell */ 3071c49abecSKevin Hao 3081c49abecSKevin Hao /* Be careful, this will clobber the lr register. */ 3091c49abecSKevin Hao #define LOAD_REG_ADDR_PIC(reg, name) \ 310f5007dbfSChristophe Leroy bcl 20,31,$+4; \ 3111c49abecSKevin Hao 0: mflr reg; \ 3121c49abecSKevin Hao addis reg,reg,(name - 0b)@ha; \ 3131c49abecSKevin Hao addi reg,reg,(name - 0b)@l; 3141c49abecSKevin Hao 315c691b4b8SChristophe Leroy #if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) 3167998eb3dSGuenter Roeck #define __AS_ATHIGH high 3177998eb3dSGuenter Roeck #else 3187998eb3dSGuenter Roeck #define __AS_ATHIGH h 3197998eb3dSGuenter Roeck #endif 320c691b4b8SChristophe Leroy 321c691b4b8SChristophe Leroy .macro __LOAD_REG_IMMEDIATE_32 r, x 322c691b4b8SChristophe Leroy .if (\x) >= 0x8000 || (\x) < -0x8000 323c691b4b8SChristophe Leroy lis \r, (\x)@__AS_ATHIGH 324c691b4b8SChristophe Leroy .if (\x) & 0xffff != 0 325c691b4b8SChristophe Leroy ori \r, \r, (\x)@l 326c691b4b8SChristophe Leroy .endif 327c691b4b8SChristophe Leroy .else 328c691b4b8SChristophe Leroy li \r, (\x)@l 329c691b4b8SChristophe Leroy .endif 330c691b4b8SChristophe Leroy .endm 331c691b4b8SChristophe Leroy 332c691b4b8SChristophe Leroy .macro __LOAD_REG_IMMEDIATE r, x 333c691b4b8SChristophe Leroy .if (\x) >= 0x80000000 || (\x) < -0x80000000 334c691b4b8SChristophe Leroy __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 335c691b4b8SChristophe Leroy sldi \r, \r, 32 336c691b4b8SChristophe Leroy .if (\x) & 0xffff0000 != 0 337c691b4b8SChristophe Leroy oris \r, \r, (\x)@__AS_ATHIGH 338c691b4b8SChristophe Leroy .endif 339c691b4b8SChristophe Leroy .if (\x) & 0xffff != 0 340c691b4b8SChristophe Leroy ori \r, \r, (\x)@l 341c691b4b8SChristophe Leroy .endif 342c691b4b8SChristophe Leroy .else 343c691b4b8SChristophe Leroy __LOAD_REG_IMMEDIATE_32 \r, \x 344c691b4b8SChristophe Leroy .endif 345c691b4b8SChristophe Leroy .endm 346c691b4b8SChristophe Leroy 347c691b4b8SChristophe Leroy #ifdef __powerpc64__ 348c691b4b8SChristophe Leroy 3498e93fb33SNicholas Piggin #define __LOAD_PACA_TOC(reg) \ 3508e93fb33SNicholas Piggin ld reg,PACATOC(r13) 3518e93fb33SNicholas Piggin 3528e93fb33SNicholas Piggin #define LOAD_PACA_TOC() \ 3538e93fb33SNicholas Piggin __LOAD_PACA_TOC(r2) 3548e93fb33SNicholas Piggin 355c691b4b8SChristophe Leroy #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr 356c691b4b8SChristophe Leroy 357d7fb5b18SChristophe Leroy #define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ 358d7fb5b18SChristophe Leroy lis tmp, (expr)@highest; \ 359d7fb5b18SChristophe Leroy lis reg, (expr)@__AS_ATHIGH; \ 360d7fb5b18SChristophe Leroy ori tmp, tmp, (expr)@higher; \ 361d7fb5b18SChristophe Leroy ori reg, reg, (expr)@l; \ 362d7fb5b18SChristophe Leroy rldimi reg, tmp, 32, 0 363b8b572e1SStephen Rothwell 364b8b572e1SStephen Rothwell #define LOAD_REG_ADDR(reg,name) \ 365754f6117SNicholas Piggin addis reg,r2,name@toc@ha; \ 366754f6117SNicholas Piggin addi reg,reg,name@toc@l 367b8b572e1SStephen Rothwell 3683569d84bSNicholas Piggin #ifdef CONFIG_PPC_BOOK3E_64 3693569d84bSNicholas Piggin /* 3703569d84bSNicholas Piggin * This is used in register-constrained interrupt handlers. Not to be used 3713569d84bSNicholas Piggin * by BOOK3S. ld complains with "got/toc optimization is not supported" if r2 3723569d84bSNicholas Piggin * is not used for the TOC offset, so use @got(tocreg). If the interrupt 3733569d84bSNicholas Piggin * handlers saved r2 instead, LOAD_REG_ADDR could be used. 3743569d84bSNicholas Piggin */ 3753569d84bSNicholas Piggin #define LOAD_REG_ADDR_ALTTOC(reg,tocreg,name) \ 3763569d84bSNicholas Piggin ld reg,name@got(tocreg) 3773569d84bSNicholas Piggin #endif 3783569d84bSNicholas Piggin 379b8b572e1SStephen Rothwell #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 380b8b572e1SStephen Rothwell #define ADDROFF(name) 0 381b8b572e1SStephen Rothwell 382b8b572e1SStephen Rothwell /* offsets for stack frame layout */ 383b8b572e1SStephen Rothwell #define LRSAVE 16 384b8b572e1SStephen Rothwell 385b8b572e1SStephen Rothwell #else /* 32-bit */ 386b8b572e1SStephen Rothwell 387c691b4b8SChristophe Leroy #define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr 388c691b4b8SChristophe Leroy 389c691b4b8SChristophe Leroy #define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ 390564aa5cfSMichael Neuling lis reg,(expr)@ha; \ 391564aa5cfSMichael Neuling addi reg,reg,(expr)@l; 392b8b572e1SStephen Rothwell 393c691b4b8SChristophe Leroy #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) 394b8b572e1SStephen Rothwell 395564aa5cfSMichael Neuling #define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha 396b8b572e1SStephen Rothwell #define ADDROFF(name) name@l 397b8b572e1SStephen Rothwell 398b8b572e1SStephen Rothwell /* offsets for stack frame layout */ 399b8b572e1SStephen Rothwell #define LRSAVE 4 400b8b572e1SStephen Rothwell 401b8b572e1SStephen Rothwell #endif 402b8b572e1SStephen Rothwell 403b8b572e1SStephen Rothwell /* various errata or part fixups */ 4043e731858SChristophe Leroy #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_E500) 405b8b572e1SStephen Rothwell #define MFTB(dest) \ 406beb2dc0aSScott Wood 90: mfspr dest, SPRN_TBRL; \ 407b8b572e1SStephen Rothwell BEGIN_FTR_SECTION_NESTED(96); \ 408b8b572e1SStephen Rothwell cmpwi dest,0; \ 409b8b572e1SStephen Rothwell beq- 90b; \ 410b8b572e1SStephen Rothwell END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 411b8b572e1SStephen Rothwell #else 41272e4b2cdSChristophe Leroy #define MFTB(dest) MFTBL(dest) 41372e4b2cdSChristophe Leroy #endif 41472e4b2cdSChristophe Leroy 41572e4b2cdSChristophe Leroy #ifdef CONFIG_PPC_8xx 41672e4b2cdSChristophe Leroy #define MFTBL(dest) mftb dest 41772e4b2cdSChristophe Leroy #define MFTBU(dest) mftbu dest 41872e4b2cdSChristophe Leroy #else 41972e4b2cdSChristophe Leroy #define MFTBL(dest) mfspr dest, SPRN_TBRL 42072e4b2cdSChristophe Leroy #define MFTBU(dest) mfspr dest, SPRN_TBRU 421b8b572e1SStephen Rothwell #endif 422b8b572e1SStephen Rothwell 4238b14e1dfSChristophe Leroy #ifndef CONFIG_SMP 42412c3f1fdSChristophe Leroy #define TLBSYNC 42512c3f1fdSChristophe Leroy #else 42612c3f1fdSChristophe Leroy #define TLBSYNC tlbsync; sync 427b8b572e1SStephen Rothwell #endif 428b8b572e1SStephen Rothwell 429694caf02SAnton Blanchard #ifdef CONFIG_PPC64 430694caf02SAnton Blanchard #define MTOCRF(FXM, RS) \ 431694caf02SAnton Blanchard BEGIN_FTR_SECTION_NESTED(848); \ 43286e32fdcSMichael Neuling mtcrf (FXM), RS; \ 433694caf02SAnton Blanchard FTR_SECTION_ELSE_NESTED(848); \ 43486e32fdcSMichael Neuling mtocrf (FXM), RS; \ 435694caf02SAnton Blanchard ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) 436694caf02SAnton Blanchard #endif 437b8b572e1SStephen Rothwell 438b8b572e1SStephen Rothwell /* 439b8b572e1SStephen Rothwell * This instruction is not implemented on the PPC 603 or 601; however, on 440b8b572e1SStephen Rothwell * the 403GCX and 405GP tlbia IS defined and tlbie is not. 441b8b572e1SStephen Rothwell * All of these instructions exist in the 8xx, they have magical powers, 442b8b572e1SStephen Rothwell * and they must be used. 443b8b572e1SStephen Rothwell */ 444b8b572e1SStephen Rothwell 445968159c0SChristophe Leroy #if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) 446b8b572e1SStephen Rothwell #define tlbia \ 447b8b572e1SStephen Rothwell li r4,1024; \ 448b8b572e1SStephen Rothwell mtctr r4; \ 449b8b572e1SStephen Rothwell lis r4,KERNELBASE@h; \ 450e3824e42SRussell Currey .machine push; \ 451e3824e42SRussell Currey .machine "power4"; \ 452b8b572e1SStephen Rothwell 0: tlbie r4; \ 453e3824e42SRussell Currey .machine pop; \ 454b8b572e1SStephen Rothwell addi r4,r4,0x1000; \ 455b8b572e1SStephen Rothwell bdnz 0b 456b8b572e1SStephen Rothwell #endif 457b8b572e1SStephen Rothwell 458b8b572e1SStephen Rothwell 459b8b572e1SStephen Rothwell #ifdef CONFIG_IBM440EP_ERR42 460b8b572e1SStephen Rothwell #define PPC440EP_ERR42 isync 461b8b572e1SStephen Rothwell #else 462b8b572e1SStephen Rothwell #define PPC440EP_ERR42 463b8b572e1SStephen Rothwell #endif 464b8b572e1SStephen Rothwell 465a515348fSMichael Neuling /* The following stops all load and store data streams associated with stream 466a515348fSMichael Neuling * ID (ie. streams created explicitly). The embedded and server mnemonics for 46715a3204dSNicholas Piggin * dcbt are different so this must only be used for server. 468a515348fSMichael Neuling */ 46915a3204dSNicholas Piggin #define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ 470a515348fSMichael Neuling lis scratch,0x60000000@h; \ 47115a3204dSNicholas Piggin dcbt 0,scratch,0b01010 472a515348fSMichael Neuling 47344c58cccSBenjamin Herrenschmidt /* 47444c58cccSBenjamin Herrenschmidt * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 47544c58cccSBenjamin Herrenschmidt * keep the address intact to be compatible with code shared with 47644c58cccSBenjamin Herrenschmidt * 32-bit classic. 47744c58cccSBenjamin Herrenschmidt * 47844c58cccSBenjamin Herrenschmidt * On the other hand, I find it useful to have them behave as expected 47944c58cccSBenjamin Herrenschmidt * by their name (ie always do the addition) on 64-bit BookE 48044c58cccSBenjamin Herrenschmidt */ 48144c58cccSBenjamin Herrenschmidt #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 482b8b572e1SStephen Rothwell #define toreal(rd) 483b8b572e1SStephen Rothwell #define fromreal(rd) 484b8b572e1SStephen Rothwell 485b8b572e1SStephen Rothwell /* 486b8b572e1SStephen Rothwell * We use addis to ensure compatibility with the "classic" ppc versions of 487b8b572e1SStephen Rothwell * these macros, which use rs = 0 to get the tophys offset in rd, rather than 488b8b572e1SStephen Rothwell * converting the address in r0, and so this version has to do that too 489b8b572e1SStephen Rothwell * (i.e. set register rd to 0 when rs == 0). 490b8b572e1SStephen Rothwell */ 491b8b572e1SStephen Rothwell #define tophys(rd,rs) \ 492b8b572e1SStephen Rothwell addis rd,rs,0 493b8b572e1SStephen Rothwell 494b8b572e1SStephen Rothwell #define tovirt(rd,rs) \ 495b8b572e1SStephen Rothwell addis rd,rs,0 496b8b572e1SStephen Rothwell 497b8b572e1SStephen Rothwell #elif defined(CONFIG_PPC64) 498b8b572e1SStephen Rothwell #define toreal(rd) /* we can access c000... in real mode */ 499b8b572e1SStephen Rothwell #define fromreal(rd) 500b8b572e1SStephen Rothwell 501b8b572e1SStephen Rothwell #define tophys(rd,rs) \ 502b8b572e1SStephen Rothwell clrldi rd,rs,2 503b8b572e1SStephen Rothwell 504b8b572e1SStephen Rothwell #define tovirt(rd,rs) \ 505b8b572e1SStephen Rothwell rotldi rd,rs,16; \ 506b8b572e1SStephen Rothwell ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 507b8b572e1SStephen Rothwell rotldi rd,rd,48 508b8b572e1SStephen Rothwell #else 509b8b572e1SStephen Rothwell #define toreal(rd) tophys(rd,rd) 510b8b572e1SStephen Rothwell #define fromreal(rd) tovirt(rd,rd) 511b8b572e1SStephen Rothwell 512c62ce9efSChristophe Leroy #define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h 513c62ce9efSChristophe Leroy #define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h 514b8b572e1SStephen Rothwell #endif 515b8b572e1SStephen Rothwell 51644c58cccSBenjamin Herrenschmidt #ifdef CONFIG_PPC_BOOK3S_64 517b8b572e1SStephen Rothwell #define MTMSRD(r) mtmsrd r 518b38c77d8SBenjamin Herrenschmidt #define MTMSR_EERI(reg) mtmsrd reg,1 519b8b572e1SStephen Rothwell #else 520b8b572e1SStephen Rothwell #define MTMSRD(r) mtmsr r 521b38c77d8SBenjamin Herrenschmidt #define MTMSR_EERI(reg) mtmsr reg 522b8b572e1SStephen Rothwell #endif 523b8b572e1SStephen Rothwell 524b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 525b8b572e1SStephen Rothwell 526b8b572e1SStephen Rothwell /* The boring bits... */ 527b8b572e1SStephen Rothwell 528b8b572e1SStephen Rothwell /* Condition Register Bit Fields */ 529b8b572e1SStephen Rothwell 530b8b572e1SStephen Rothwell #define cr0 0 531b8b572e1SStephen Rothwell #define cr1 1 532b8b572e1SStephen Rothwell #define cr2 2 533b8b572e1SStephen Rothwell #define cr3 3 534b8b572e1SStephen Rothwell #define cr4 4 535b8b572e1SStephen Rothwell #define cr5 5 536b8b572e1SStephen Rothwell #define cr6 6 537b8b572e1SStephen Rothwell #define cr7 7 538b8b572e1SStephen Rothwell 539b8b572e1SStephen Rothwell 5409a13a524SMichael Neuling /* 5419a13a524SMichael Neuling * General Purpose Registers (GPRs) 5429a13a524SMichael Neuling * 5439a13a524SMichael Neuling * The lower case r0-r31 should be used in preference to the upper 5449a13a524SMichael Neuling * case R0-R31 as they provide more error checking in the assembler. 5459a13a524SMichael Neuling * Use R0-31 only when really nessesary. 5469a13a524SMichael Neuling */ 547b8b572e1SStephen Rothwell 5489a13a524SMichael Neuling #define r0 %r0 5499a13a524SMichael Neuling #define r1 %r1 5509a13a524SMichael Neuling #define r2 %r2 5519a13a524SMichael Neuling #define r3 %r3 5529a13a524SMichael Neuling #define r4 %r4 5539a13a524SMichael Neuling #define r5 %r5 5549a13a524SMichael Neuling #define r6 %r6 5559a13a524SMichael Neuling #define r7 %r7 5569a13a524SMichael Neuling #define r8 %r8 5579a13a524SMichael Neuling #define r9 %r9 5589a13a524SMichael Neuling #define r10 %r10 5599a13a524SMichael Neuling #define r11 %r11 5609a13a524SMichael Neuling #define r12 %r12 5619a13a524SMichael Neuling #define r13 %r13 5629a13a524SMichael Neuling #define r14 %r14 5639a13a524SMichael Neuling #define r15 %r15 5649a13a524SMichael Neuling #define r16 %r16 5659a13a524SMichael Neuling #define r17 %r17 5669a13a524SMichael Neuling #define r18 %r18 5679a13a524SMichael Neuling #define r19 %r19 5689a13a524SMichael Neuling #define r20 %r20 5699a13a524SMichael Neuling #define r21 %r21 5709a13a524SMichael Neuling #define r22 %r22 5719a13a524SMichael Neuling #define r23 %r23 5729a13a524SMichael Neuling #define r24 %r24 5739a13a524SMichael Neuling #define r25 %r25 5749a13a524SMichael Neuling #define r26 %r26 5759a13a524SMichael Neuling #define r27 %r27 5769a13a524SMichael Neuling #define r28 %r28 5779a13a524SMichael Neuling #define r29 %r29 5789a13a524SMichael Neuling #define r30 %r30 5799a13a524SMichael Neuling #define r31 %r31 580b8b572e1SStephen Rothwell 581b8b572e1SStephen Rothwell 582b8b572e1SStephen Rothwell /* Floating Point Registers (FPRs) */ 583b8b572e1SStephen Rothwell 584b8b572e1SStephen Rothwell #define fr0 0 585b8b572e1SStephen Rothwell #define fr1 1 586b8b572e1SStephen Rothwell #define fr2 2 587b8b572e1SStephen Rothwell #define fr3 3 588b8b572e1SStephen Rothwell #define fr4 4 589b8b572e1SStephen Rothwell #define fr5 5 590b8b572e1SStephen Rothwell #define fr6 6 591b8b572e1SStephen Rothwell #define fr7 7 592b8b572e1SStephen Rothwell #define fr8 8 593b8b572e1SStephen Rothwell #define fr9 9 594b8b572e1SStephen Rothwell #define fr10 10 595b8b572e1SStephen Rothwell #define fr11 11 596b8b572e1SStephen Rothwell #define fr12 12 597b8b572e1SStephen Rothwell #define fr13 13 598b8b572e1SStephen Rothwell #define fr14 14 599b8b572e1SStephen Rothwell #define fr15 15 600b8b572e1SStephen Rothwell #define fr16 16 601b8b572e1SStephen Rothwell #define fr17 17 602b8b572e1SStephen Rothwell #define fr18 18 603b8b572e1SStephen Rothwell #define fr19 19 604b8b572e1SStephen Rothwell #define fr20 20 605b8b572e1SStephen Rothwell #define fr21 21 606b8b572e1SStephen Rothwell #define fr22 22 607b8b572e1SStephen Rothwell #define fr23 23 608b8b572e1SStephen Rothwell #define fr24 24 609b8b572e1SStephen Rothwell #define fr25 25 610b8b572e1SStephen Rothwell #define fr26 26 611b8b572e1SStephen Rothwell #define fr27 27 612b8b572e1SStephen Rothwell #define fr28 28 613b8b572e1SStephen Rothwell #define fr29 29 614b8b572e1SStephen Rothwell #define fr30 30 615b8b572e1SStephen Rothwell #define fr31 31 616b8b572e1SStephen Rothwell 617b8b572e1SStephen Rothwell /* AltiVec Registers (VPRs) */ 618b8b572e1SStephen Rothwell 619c2ce6f9fSAnton Blanchard #define v0 0 620c2ce6f9fSAnton Blanchard #define v1 1 621c2ce6f9fSAnton Blanchard #define v2 2 622c2ce6f9fSAnton Blanchard #define v3 3 623c2ce6f9fSAnton Blanchard #define v4 4 624c2ce6f9fSAnton Blanchard #define v5 5 625c2ce6f9fSAnton Blanchard #define v6 6 626c2ce6f9fSAnton Blanchard #define v7 7 627c2ce6f9fSAnton Blanchard #define v8 8 628c2ce6f9fSAnton Blanchard #define v9 9 629c2ce6f9fSAnton Blanchard #define v10 10 630c2ce6f9fSAnton Blanchard #define v11 11 631c2ce6f9fSAnton Blanchard #define v12 12 632c2ce6f9fSAnton Blanchard #define v13 13 633c2ce6f9fSAnton Blanchard #define v14 14 634c2ce6f9fSAnton Blanchard #define v15 15 635c2ce6f9fSAnton Blanchard #define v16 16 636c2ce6f9fSAnton Blanchard #define v17 17 637c2ce6f9fSAnton Blanchard #define v18 18 638c2ce6f9fSAnton Blanchard #define v19 19 639c2ce6f9fSAnton Blanchard #define v20 20 640c2ce6f9fSAnton Blanchard #define v21 21 641c2ce6f9fSAnton Blanchard #define v22 22 642c2ce6f9fSAnton Blanchard #define v23 23 643c2ce6f9fSAnton Blanchard #define v24 24 644c2ce6f9fSAnton Blanchard #define v25 25 645c2ce6f9fSAnton Blanchard #define v26 26 646c2ce6f9fSAnton Blanchard #define v27 27 647c2ce6f9fSAnton Blanchard #define v28 28 648c2ce6f9fSAnton Blanchard #define v29 29 649c2ce6f9fSAnton Blanchard #define v30 30 650c2ce6f9fSAnton Blanchard #define v31 31 651b8b572e1SStephen Rothwell 652b8b572e1SStephen Rothwell /* VSX Registers (VSRs) */ 653b8b572e1SStephen Rothwell 654df99e6ebSAnton Blanchard #define vs0 0 655df99e6ebSAnton Blanchard #define vs1 1 656df99e6ebSAnton Blanchard #define vs2 2 657df99e6ebSAnton Blanchard #define vs3 3 658df99e6ebSAnton Blanchard #define vs4 4 659df99e6ebSAnton Blanchard #define vs5 5 660df99e6ebSAnton Blanchard #define vs6 6 661df99e6ebSAnton Blanchard #define vs7 7 662df99e6ebSAnton Blanchard #define vs8 8 663df99e6ebSAnton Blanchard #define vs9 9 664df99e6ebSAnton Blanchard #define vs10 10 665df99e6ebSAnton Blanchard #define vs11 11 666df99e6ebSAnton Blanchard #define vs12 12 667df99e6ebSAnton Blanchard #define vs13 13 668df99e6ebSAnton Blanchard #define vs14 14 669df99e6ebSAnton Blanchard #define vs15 15 670df99e6ebSAnton Blanchard #define vs16 16 671df99e6ebSAnton Blanchard #define vs17 17 672df99e6ebSAnton Blanchard #define vs18 18 673df99e6ebSAnton Blanchard #define vs19 19 674df99e6ebSAnton Blanchard #define vs20 20 675df99e6ebSAnton Blanchard #define vs21 21 676df99e6ebSAnton Blanchard #define vs22 22 677df99e6ebSAnton Blanchard #define vs23 23 678df99e6ebSAnton Blanchard #define vs24 24 679df99e6ebSAnton Blanchard #define vs25 25 680df99e6ebSAnton Blanchard #define vs26 26 681df99e6ebSAnton Blanchard #define vs27 27 682df99e6ebSAnton Blanchard #define vs28 28 683df99e6ebSAnton Blanchard #define vs29 29 684df99e6ebSAnton Blanchard #define vs30 30 685df99e6ebSAnton Blanchard #define vs31 31 686df99e6ebSAnton Blanchard #define vs32 32 687df99e6ebSAnton Blanchard #define vs33 33 688df99e6ebSAnton Blanchard #define vs34 34 689df99e6ebSAnton Blanchard #define vs35 35 690df99e6ebSAnton Blanchard #define vs36 36 691df99e6ebSAnton Blanchard #define vs37 37 692df99e6ebSAnton Blanchard #define vs38 38 693df99e6ebSAnton Blanchard #define vs39 39 694df99e6ebSAnton Blanchard #define vs40 40 695df99e6ebSAnton Blanchard #define vs41 41 696df99e6ebSAnton Blanchard #define vs42 42 697df99e6ebSAnton Blanchard #define vs43 43 698df99e6ebSAnton Blanchard #define vs44 44 699df99e6ebSAnton Blanchard #define vs45 45 700df99e6ebSAnton Blanchard #define vs46 46 701df99e6ebSAnton Blanchard #define vs47 47 702df99e6ebSAnton Blanchard #define vs48 48 703df99e6ebSAnton Blanchard #define vs49 49 704df99e6ebSAnton Blanchard #define vs50 50 705df99e6ebSAnton Blanchard #define vs51 51 706df99e6ebSAnton Blanchard #define vs52 52 707df99e6ebSAnton Blanchard #define vs53 53 708df99e6ebSAnton Blanchard #define vs54 54 709df99e6ebSAnton Blanchard #define vs55 55 710df99e6ebSAnton Blanchard #define vs56 56 711df99e6ebSAnton Blanchard #define vs57 57 712df99e6ebSAnton Blanchard #define vs58 58 713df99e6ebSAnton Blanchard #define vs59 59 714df99e6ebSAnton Blanchard #define vs60 60 715df99e6ebSAnton Blanchard #define vs61 61 716df99e6ebSAnton Blanchard #define vs62 62 717df99e6ebSAnton Blanchard #define vs63 63 718b8b572e1SStephen Rothwell 719b8b572e1SStephen Rothwell /* SPE Registers (EVPRs) */ 720b8b572e1SStephen Rothwell 721b8b572e1SStephen Rothwell #define evr0 0 722b8b572e1SStephen Rothwell #define evr1 1 723b8b572e1SStephen Rothwell #define evr2 2 724b8b572e1SStephen Rothwell #define evr3 3 725b8b572e1SStephen Rothwell #define evr4 4 726b8b572e1SStephen Rothwell #define evr5 5 727b8b572e1SStephen Rothwell #define evr6 6 728b8b572e1SStephen Rothwell #define evr7 7 729b8b572e1SStephen Rothwell #define evr8 8 730b8b572e1SStephen Rothwell #define evr9 9 731b8b572e1SStephen Rothwell #define evr10 10 732b8b572e1SStephen Rothwell #define evr11 11 733b8b572e1SStephen Rothwell #define evr12 12 734b8b572e1SStephen Rothwell #define evr13 13 735b8b572e1SStephen Rothwell #define evr14 14 736b8b572e1SStephen Rothwell #define evr15 15 737b8b572e1SStephen Rothwell #define evr16 16 738b8b572e1SStephen Rothwell #define evr17 17 739b8b572e1SStephen Rothwell #define evr18 18 740b8b572e1SStephen Rothwell #define evr19 19 741b8b572e1SStephen Rothwell #define evr20 20 742b8b572e1SStephen Rothwell #define evr21 21 743b8b572e1SStephen Rothwell #define evr22 22 744b8b572e1SStephen Rothwell #define evr23 23 745b8b572e1SStephen Rothwell #define evr24 24 746b8b572e1SStephen Rothwell #define evr25 25 747b8b572e1SStephen Rothwell #define evr26 26 748b8b572e1SStephen Rothwell #define evr27 27 749b8b572e1SStephen Rothwell #define evr28 28 750b8b572e1SStephen Rothwell #define evr29 29 751b8b572e1SStephen Rothwell #define evr30 30 752b8b572e1SStephen Rothwell #define evr31 31 753b8b572e1SStephen Rothwell 7547fa95f9aSNicholas Piggin #define RFSCV .long 0x4c0000a4 7557fa95f9aSNicholas Piggin 7565c0484e2SBenjamin Herrenschmidt /* 7575c0484e2SBenjamin Herrenschmidt * Create an endian fixup trampoline 7585c0484e2SBenjamin Herrenschmidt * 7595c0484e2SBenjamin Herrenschmidt * This starts with a "tdi 0,0,0x48" instruction which is 7605c0484e2SBenjamin Herrenschmidt * essentially a "trap never", and thus akin to a nop. 7615c0484e2SBenjamin Herrenschmidt * 7625c0484e2SBenjamin Herrenschmidt * The opcode for this instruction read with the wrong endian 7635c0484e2SBenjamin Herrenschmidt * however results in a b . + 8 7645c0484e2SBenjamin Herrenschmidt * 7655c0484e2SBenjamin Herrenschmidt * So essentially we use that trick to execute the following 7665c0484e2SBenjamin Herrenschmidt * trampoline in "reverse endian" if we are running with the 7675c0484e2SBenjamin Herrenschmidt * MSR_LE bit set the "wrong" way for whatever endianness the 7685c0484e2SBenjamin Herrenschmidt * kernel is built for. 7695c0484e2SBenjamin Herrenschmidt */ 770b8b572e1SStephen Rothwell 771e0d68273SChristophe Leroy #ifdef CONFIG_PPC_BOOK3E_64 7725c0484e2SBenjamin Herrenschmidt #define FIXUP_ENDIAN 7735c0484e2SBenjamin Herrenschmidt #else 7748ca9c08dSNicholas Piggin /* 775db10f550SRandy Dunlap * This version may be used in HV or non-HV context. 7768ca9c08dSNicholas Piggin * MSR[EE] must be disabled. 7778ca9c08dSNicholas Piggin */ 7785c0484e2SBenjamin Herrenschmidt #define FIXUP_ENDIAN \ 7795c0484e2SBenjamin Herrenschmidt tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 780f848ea7fSNicholas Piggin b 191f; /* Skip trampoline if endian is good */ \ 7815c0484e2SBenjamin Herrenschmidt .long 0xa600607d; /* mfmsr r11 */ \ 7825c0484e2SBenjamin Herrenschmidt .long 0x01006b69; /* xori r11,r11,1 */ \ 783f1fe5252SNicholas Piggin .long 0x00004039; /* li r10,0 */ \ 784f1fe5252SNicholas Piggin .long 0x6401417d; /* mtmsrd r10,1 */ \ 785f1fe5252SNicholas Piggin .long 0x05009f42; /* bcl 20,31,$+4 */ \ 786f1fe5252SNicholas Piggin .long 0xa602487d; /* mflr r10 */ \ 787f1fe5252SNicholas Piggin .long 0x14004a39; /* addi r10,r10,20 */ \ 7885c0484e2SBenjamin Herrenschmidt .long 0xa6035a7d; /* mtsrr0 r10 */ \ 7895c0484e2SBenjamin Herrenschmidt .long 0xa6037b7d; /* mtsrr1 r11 */ \ 790f848ea7fSNicholas Piggin .long 0x2400004c; /* rfid */ \ 791f848ea7fSNicholas Piggin 191: 792f1fe5252SNicholas Piggin 7938ca9c08dSNicholas Piggin /* 7948ca9c08dSNicholas Piggin * This version that may only be used with MSR[HV]=1 7958ca9c08dSNicholas Piggin * - Does not clear MSR[RI], so more robust. 7968ca9c08dSNicholas Piggin * - Slightly smaller and faster. 7978ca9c08dSNicholas Piggin */ 7988ca9c08dSNicholas Piggin #define FIXUP_ENDIAN_HV \ 7998ca9c08dSNicholas Piggin tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ 8008ca9c08dSNicholas Piggin b 191f; /* Skip trampoline if endian is good */ \ 8018ca9c08dSNicholas Piggin .long 0xa600607d; /* mfmsr r11 */ \ 8028ca9c08dSNicholas Piggin .long 0x01006b69; /* xori r11,r11,1 */ \ 8038ca9c08dSNicholas Piggin .long 0x05009f42; /* bcl 20,31,$+4 */ \ 8048ca9c08dSNicholas Piggin .long 0xa602487d; /* mflr r10 */ \ 8058ca9c08dSNicholas Piggin .long 0x14004a39; /* addi r10,r10,20 */ \ 8068ca9c08dSNicholas Piggin .long 0xa64b5a7d; /* mthsrr0 r10 */ \ 8078ca9c08dSNicholas Piggin .long 0xa64b7b7d; /* mthsrr1 r11 */ \ 8088ca9c08dSNicholas Piggin .long 0x2402004c; /* hrfid */ \ 8098ca9c08dSNicholas Piggin 191: 8108ca9c08dSNicholas Piggin 811e0d68273SChristophe Leroy #endif /* !CONFIG_PPC_BOOK3E_64 */ 812e3f2c6c3SMichael Ellerman 8135c0484e2SBenjamin Herrenschmidt #endif /* __ASSEMBLY__ */ 814e3f2c6c3SMichael Ellerman 815325678fdSNicholas Piggin #define SOFT_MASK_TABLE(_start, _end) \ 816325678fdSNicholas Piggin stringify_in_c(.section __soft_mask_table,"a";)\ 817325678fdSNicholas Piggin stringify_in_c(.balign 8;) \ 818325678fdSNicholas Piggin stringify_in_c(.llong (_start);) \ 819325678fdSNicholas Piggin stringify_in_c(.llong (_end);) \ 820325678fdSNicholas Piggin stringify_in_c(.previous) 821325678fdSNicholas Piggin 822f23699c9SNicholas Piggin #define RESTART_TABLE(_start, _end, _target) \ 823f23699c9SNicholas Piggin stringify_in_c(.section __restart_table,"a";)\ 824f23699c9SNicholas Piggin stringify_in_c(.balign 8;) \ 825f23699c9SNicholas Piggin stringify_in_c(.llong (_start);) \ 826f23699c9SNicholas Piggin stringify_in_c(.llong (_end);) \ 827f23699c9SNicholas Piggin stringify_in_c(.llong (_target);) \ 828f23699c9SNicholas Piggin stringify_in_c(.previous) 829f23699c9SNicholas Piggin 8303e731858SChristophe Leroy #ifdef CONFIG_PPC_E500 8311cbf8990SDiana Craciun #define BTB_FLUSH(reg) \ 8321cbf8990SDiana Craciun lis reg,BUCSR_INIT@h; \ 8331cbf8990SDiana Craciun ori reg,reg,BUCSR_INIT@l; \ 8341cbf8990SDiana Craciun mtspr SPRN_BUCSR,reg; \ 8351cbf8990SDiana Craciun isync; 8361cbf8990SDiana Craciun #else 8371cbf8990SDiana Craciun #define BTB_FLUSH(reg) 8383e731858SChristophe Leroy #endif /* CONFIG_PPC_E500 */ 8391cbf8990SDiana Craciun 840*ac9c8901SNicholas Miehlbradt #if defined(CONFIG_PPC64_ELF_ABI_V1) 841*ac9c8901SNicholas Miehlbradt #define STACK_FRAME_PARAMS 48 842*ac9c8901SNicholas Miehlbradt #elif defined(CONFIG_PPC64_ELF_ABI_V2) 843*ac9c8901SNicholas Miehlbradt #define STACK_FRAME_PARAMS 32 844*ac9c8901SNicholas Miehlbradt #elif defined(CONFIG_PPC32) 845*ac9c8901SNicholas Miehlbradt #define STACK_FRAME_PARAMS 8 846*ac9c8901SNicholas Miehlbradt #endif 847*ac9c8901SNicholas Miehlbradt 848b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_PPC_ASM_H */ 849