1b8b572e1SStephen Rothwell /* 2b8b572e1SStephen Rothwell * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 3b8b572e1SStephen Rothwell */ 4b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_PPC_ASM_H 5b8b572e1SStephen Rothwell #define _ASM_POWERPC_PPC_ASM_H 6b8b572e1SStephen Rothwell 79203fc9cSTim Abbott #include <linux/init.h> 8b8b572e1SStephen Rothwell #include <linux/stringify.h> 9b8b572e1SStephen Rothwell #include <asm/asm-compat.h> 10b8b572e1SStephen Rothwell #include <asm/processor.h> 1116c57b36SKumar Gala #include <asm/ppc-opcode.h> 12b8b572e1SStephen Rothwell 13b8b572e1SStephen Rothwell #ifndef __ASSEMBLY__ 14b8b572e1SStephen Rothwell #error __FILE__ should only be used in assembler files 15b8b572e1SStephen Rothwell #else 16b8b572e1SStephen Rothwell 17b8b572e1SStephen Rothwell #define SZL (BITS_PER_LONG/8) 18b8b572e1SStephen Rothwell 19b8b572e1SStephen Rothwell /* 20b8b572e1SStephen Rothwell * Stuff for accurate CPU time accounting. 21b8b572e1SStephen Rothwell * These macros handle transitions between user and system state 22b8b572e1SStephen Rothwell * in exception entry and exit and accumulate time to the 23b8b572e1SStephen Rothwell * user_time and system_time fields in the paca. 24b8b572e1SStephen Rothwell */ 25b8b572e1SStephen Rothwell 26b8b572e1SStephen Rothwell #ifndef CONFIG_VIRT_CPU_ACCOUNTING 27b8b572e1SStephen Rothwell #define ACCOUNT_CPU_USER_ENTRY(ra, rb) 28b8b572e1SStephen Rothwell #define ACCOUNT_CPU_USER_EXIT(ra, rb) 29b8b572e1SStephen Rothwell #else 30b8b572e1SStephen Rothwell #define ACCOUNT_CPU_USER_ENTRY(ra, rb) \ 31b8b572e1SStephen Rothwell beq 2f; /* if from kernel mode */ \ 32b8b572e1SStephen Rothwell BEGIN_FTR_SECTION; \ 33b8b572e1SStephen Rothwell mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 34b8b572e1SStephen Rothwell END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 35b8b572e1SStephen Rothwell BEGIN_FTR_SECTION; \ 36b8b572e1SStephen Rothwell MFTB(ra); /* or get TB if no PURR */ \ 37b8b572e1SStephen Rothwell END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 38b8b572e1SStephen Rothwell ld rb,PACA_STARTPURR(r13); \ 39b8b572e1SStephen Rothwell std ra,PACA_STARTPURR(r13); \ 40b8b572e1SStephen Rothwell subf rb,rb,ra; /* subtract start value */ \ 41b8b572e1SStephen Rothwell ld ra,PACA_USER_TIME(r13); \ 42b8b572e1SStephen Rothwell add ra,ra,rb; /* add on to user time */ \ 43b8b572e1SStephen Rothwell std ra,PACA_USER_TIME(r13); \ 44b8b572e1SStephen Rothwell 2: 45b8b572e1SStephen Rothwell 46b8b572e1SStephen Rothwell #define ACCOUNT_CPU_USER_EXIT(ra, rb) \ 47b8b572e1SStephen Rothwell BEGIN_FTR_SECTION; \ 48b8b572e1SStephen Rothwell mfspr ra,SPRN_PURR; /* get processor util. reg */ \ 49b8b572e1SStephen Rothwell END_FTR_SECTION_IFSET(CPU_FTR_PURR); \ 50b8b572e1SStephen Rothwell BEGIN_FTR_SECTION; \ 51b8b572e1SStephen Rothwell MFTB(ra); /* or get TB if no PURR */ \ 52b8b572e1SStephen Rothwell END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \ 53b8b572e1SStephen Rothwell ld rb,PACA_STARTPURR(r13); \ 54b8b572e1SStephen Rothwell std ra,PACA_STARTPURR(r13); \ 55b8b572e1SStephen Rothwell subf rb,rb,ra; /* subtract start value */ \ 56b8b572e1SStephen Rothwell ld ra,PACA_SYSTEM_TIME(r13); \ 57b8b572e1SStephen Rothwell add ra,ra,rb; /* add on to user time */ \ 58b8b572e1SStephen Rothwell std ra,PACA_SYSTEM_TIME(r13); 59b8b572e1SStephen Rothwell #endif 60b8b572e1SStephen Rothwell 61b8b572e1SStephen Rothwell /* 62b8b572e1SStephen Rothwell * Macros for storing registers into and loading registers from 63b8b572e1SStephen Rothwell * exception frames. 64b8b572e1SStephen Rothwell */ 65b8b572e1SStephen Rothwell #ifdef __powerpc64__ 66b8b572e1SStephen Rothwell #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) 67b8b572e1SStephen Rothwell #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) 68b8b572e1SStephen Rothwell #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) 69b8b572e1SStephen Rothwell #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) 70b8b572e1SStephen Rothwell #else 71b8b572e1SStephen Rothwell #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 72b8b572e1SStephen Rothwell #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 73b8b572e1SStephen Rothwell #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ 74b8b572e1SStephen Rothwell SAVE_10GPRS(22, base) 75b8b572e1SStephen Rothwell #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ 76b8b572e1SStephen Rothwell REST_10GPRS(22, base) 77b8b572e1SStephen Rothwell #endif 78b8b572e1SStephen Rothwell 79b8b572e1SStephen Rothwell #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 80b8b572e1SStephen Rothwell #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 81b8b572e1SStephen Rothwell #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 82b8b572e1SStephen Rothwell #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 83b8b572e1SStephen Rothwell #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 84b8b572e1SStephen Rothwell #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 85b8b572e1SStephen Rothwell #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 86b8b572e1SStephen Rothwell #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 87b8b572e1SStephen Rothwell 88b8b572e1SStephen Rothwell #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 89b8b572e1SStephen Rothwell #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 90b8b572e1SStephen Rothwell #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 91b8b572e1SStephen Rothwell #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) 92b8b572e1SStephen Rothwell #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) 93b8b572e1SStephen Rothwell #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) 94b8b572e1SStephen Rothwell #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*TS_FPRWIDTH*(n)(base) 95b8b572e1SStephen Rothwell #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) 96b8b572e1SStephen Rothwell #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) 97b8b572e1SStephen Rothwell #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) 98b8b572e1SStephen Rothwell #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) 99b8b572e1SStephen Rothwell #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 100b8b572e1SStephen Rothwell 10123e55f92SMichael Wolf #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,base,b 102b8b572e1SStephen Rothwell #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 103b8b572e1SStephen Rothwell #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) 104b8b572e1SStephen Rothwell #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) 105b8b572e1SStephen Rothwell #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) 106b8b572e1SStephen Rothwell #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) 10723e55f92SMichael Wolf #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,base,b 108b8b572e1SStephen Rothwell #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 109b8b572e1SStephen Rothwell #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) 110b8b572e1SStephen Rothwell #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) 111b8b572e1SStephen Rothwell #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) 112b8b572e1SStephen Rothwell #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) 113b8b572e1SStephen Rothwell 114b8b572e1SStephen Rothwell /* Save the lower 32 VSRs in the thread VSR region */ 11523e55f92SMichael Wolf #define SAVE_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); STXVD2X(n,base,b) 116b8b572e1SStephen Rothwell #define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) 117b8b572e1SStephen Rothwell #define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) 118b8b572e1SStephen Rothwell #define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) 119b8b572e1SStephen Rothwell #define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) 120b8b572e1SStephen Rothwell #define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) 12123e55f92SMichael Wolf #define REST_VSR(n,b,base) li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b) 122b8b572e1SStephen Rothwell #define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) 123b8b572e1SStephen Rothwell #define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) 124b8b572e1SStephen Rothwell #define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) 125b8b572e1SStephen Rothwell #define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) 126b8b572e1SStephen Rothwell #define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) 127b8b572e1SStephen Rothwell /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */ 12823e55f92SMichael Wolf #define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,base,b) 129b8b572e1SStephen Rothwell #define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base) 130b8b572e1SStephen Rothwell #define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base) 131b8b572e1SStephen Rothwell #define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base) 132b8b572e1SStephen Rothwell #define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base) 133b8b572e1SStephen Rothwell #define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base) 13423e55f92SMichael Wolf #define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b) 135b8b572e1SStephen Rothwell #define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base) 136b8b572e1SStephen Rothwell #define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base) 137b8b572e1SStephen Rothwell #define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base) 138b8b572e1SStephen Rothwell #define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base) 139b8b572e1SStephen Rothwell #define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base) 140b8b572e1SStephen Rothwell 141b8b572e1SStephen Rothwell #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) 142b8b572e1SStephen Rothwell #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) 143b8b572e1SStephen Rothwell #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) 144b8b572e1SStephen Rothwell #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base) 145b8b572e1SStephen Rothwell #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base) 146b8b572e1SStephen Rothwell #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base) 147b8b572e1SStephen Rothwell #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n 148b8b572e1SStephen Rothwell #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) 149b8b572e1SStephen Rothwell #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base) 150b8b572e1SStephen Rothwell #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base) 151b8b572e1SStephen Rothwell #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base) 152b8b572e1SStephen Rothwell #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base) 153b8b572e1SStephen Rothwell 154b8b572e1SStephen Rothwell /* Macros to adjust thread priority for hardware multithreading */ 155b8b572e1SStephen Rothwell #define HMT_VERY_LOW or 31,31,31 # very low priority 156b8b572e1SStephen Rothwell #define HMT_LOW or 1,1,1 157b8b572e1SStephen Rothwell #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority 158b8b572e1SStephen Rothwell #define HMT_MEDIUM or 2,2,2 159b8b572e1SStephen Rothwell #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority 160b8b572e1SStephen Rothwell #define HMT_HIGH or 3,3,3 161b8b572e1SStephen Rothwell 162b8b572e1SStephen Rothwell #ifdef __KERNEL__ 163b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 164b8b572e1SStephen Rothwell 165b8b572e1SStephen Rothwell #define XGLUE(a,b) a##b 166b8b572e1SStephen Rothwell #define GLUE(a,b) XGLUE(a,b) 167b8b572e1SStephen Rothwell 168b8b572e1SStephen Rothwell #define _GLOBAL(name) \ 169b8b572e1SStephen Rothwell .section ".text"; \ 170b8b572e1SStephen Rothwell .align 2 ; \ 171b8b572e1SStephen Rothwell .globl name; \ 172b8b572e1SStephen Rothwell .globl GLUE(.,name); \ 173b8b572e1SStephen Rothwell .section ".opd","aw"; \ 174b8b572e1SStephen Rothwell name: \ 175b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 176b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 177b8b572e1SStephen Rothwell .quad 0; \ 178b8b572e1SStephen Rothwell .previous; \ 179b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 180b8b572e1SStephen Rothwell GLUE(.,name): 181b8b572e1SStephen Rothwell 182b8b572e1SStephen Rothwell #define _INIT_GLOBAL(name) \ 1839203fc9cSTim Abbott __REF; \ 184b8b572e1SStephen Rothwell .align 2 ; \ 185b8b572e1SStephen Rothwell .globl name; \ 186b8b572e1SStephen Rothwell .globl GLUE(.,name); \ 187b8b572e1SStephen Rothwell .section ".opd","aw"; \ 188b8b572e1SStephen Rothwell name: \ 189b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 190b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 191b8b572e1SStephen Rothwell .quad 0; \ 192b8b572e1SStephen Rothwell .previous; \ 193b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 194b8b572e1SStephen Rothwell GLUE(.,name): 195b8b572e1SStephen Rothwell 196b8b572e1SStephen Rothwell #define _KPROBE(name) \ 197b8b572e1SStephen Rothwell .section ".kprobes.text","a"; \ 198b8b572e1SStephen Rothwell .align 2 ; \ 199b8b572e1SStephen Rothwell .globl name; \ 200b8b572e1SStephen Rothwell .globl GLUE(.,name); \ 201b8b572e1SStephen Rothwell .section ".opd","aw"; \ 202b8b572e1SStephen Rothwell name: \ 203b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 204b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 205b8b572e1SStephen Rothwell .quad 0; \ 206b8b572e1SStephen Rothwell .previous; \ 207b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 208b8b572e1SStephen Rothwell GLUE(.,name): 209b8b572e1SStephen Rothwell 210b8b572e1SStephen Rothwell #define _STATIC(name) \ 211b8b572e1SStephen Rothwell .section ".text"; \ 212b8b572e1SStephen Rothwell .align 2 ; \ 213b8b572e1SStephen Rothwell .section ".opd","aw"; \ 214b8b572e1SStephen Rothwell name: \ 215b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 216b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 217b8b572e1SStephen Rothwell .quad 0; \ 218b8b572e1SStephen Rothwell .previous; \ 219b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 220b8b572e1SStephen Rothwell GLUE(.,name): 221b8b572e1SStephen Rothwell 222b8b572e1SStephen Rothwell #define _INIT_STATIC(name) \ 2239203fc9cSTim Abbott __REF; \ 224b8b572e1SStephen Rothwell .align 2 ; \ 225b8b572e1SStephen Rothwell .section ".opd","aw"; \ 226b8b572e1SStephen Rothwell name: \ 227b8b572e1SStephen Rothwell .quad GLUE(.,name); \ 228b8b572e1SStephen Rothwell .quad .TOC.@tocbase; \ 229b8b572e1SStephen Rothwell .quad 0; \ 230b8b572e1SStephen Rothwell .previous; \ 231b8b572e1SStephen Rothwell .type GLUE(.,name),@function; \ 232b8b572e1SStephen Rothwell GLUE(.,name): 233b8b572e1SStephen Rothwell 234b8b572e1SStephen Rothwell #else /* 32-bit */ 235b8b572e1SStephen Rothwell 236b8b572e1SStephen Rothwell #define _ENTRY(n) \ 237b8b572e1SStephen Rothwell .globl n; \ 238b8b572e1SStephen Rothwell n: 239b8b572e1SStephen Rothwell 240b8b572e1SStephen Rothwell #define _GLOBAL(n) \ 241b8b572e1SStephen Rothwell .text; \ 242b8b572e1SStephen Rothwell .stabs __stringify(n:F-1),N_FUN,0,0,n;\ 243b8b572e1SStephen Rothwell .globl n; \ 244b8b572e1SStephen Rothwell n: 245b8b572e1SStephen Rothwell 246b8b572e1SStephen Rothwell #define _KPROBE(n) \ 247b8b572e1SStephen Rothwell .section ".kprobes.text","a"; \ 248b8b572e1SStephen Rothwell .globl n; \ 249b8b572e1SStephen Rothwell n: 250b8b572e1SStephen Rothwell 251b8b572e1SStephen Rothwell #endif 252b8b572e1SStephen Rothwell 253b8b572e1SStephen Rothwell /* 254b8b572e1SStephen Rothwell * LOAD_REG_IMMEDIATE(rn, expr) 255b8b572e1SStephen Rothwell * Loads the value of the constant expression 'expr' into register 'rn' 256b8b572e1SStephen Rothwell * using immediate instructions only. Use this when it's important not 257b8b572e1SStephen Rothwell * to reference other data (i.e. on ppc64 when the TOC pointer is not 258e31aa453SPaul Mackerras * valid) and when 'expr' is a constant or absolute address. 259b8b572e1SStephen Rothwell * 260b8b572e1SStephen Rothwell * LOAD_REG_ADDR(rn, name) 261b8b572e1SStephen Rothwell * Loads the address of label 'name' into register 'rn'. Use this when 262b8b572e1SStephen Rothwell * you don't particularly need immediate instructions only, but you need 263b8b572e1SStephen Rothwell * the whole address in one register (e.g. it's a structure address and 264b8b572e1SStephen Rothwell * you want to access various offsets within it). On ppc32 this is 265b8b572e1SStephen Rothwell * identical to LOAD_REG_IMMEDIATE. 266b8b572e1SStephen Rothwell * 267b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE(rn, name) 268b8b572e1SStephen Rothwell * ADDROFF(name) 269b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE loads part of the address of label 'name' into 270b8b572e1SStephen Rothwell * register 'rn'. ADDROFF(name) returns the remainder of the address as 271b8b572e1SStephen Rothwell * a constant expression. ADDROFF(name) is a signed expression < 16 bits 272b8b572e1SStephen Rothwell * in size, so is suitable for use directly as an offset in load and store 273b8b572e1SStephen Rothwell * instructions. Use this when loading/storing a single word or less as: 274b8b572e1SStephen Rothwell * LOAD_REG_ADDRBASE(rX, name) 275b8b572e1SStephen Rothwell * ld rY,ADDROFF(name)(rX) 276b8b572e1SStephen Rothwell */ 277b8b572e1SStephen Rothwell #ifdef __powerpc64__ 278b8b572e1SStephen Rothwell #define LOAD_REG_IMMEDIATE(reg,expr) \ 279b8b572e1SStephen Rothwell lis (reg),(expr)@highest; \ 280b8b572e1SStephen Rothwell ori (reg),(reg),(expr)@higher; \ 281b8b572e1SStephen Rothwell rldicr (reg),(reg),32,31; \ 282b8b572e1SStephen Rothwell oris (reg),(reg),(expr)@h; \ 283b8b572e1SStephen Rothwell ori (reg),(reg),(expr)@l; 284b8b572e1SStephen Rothwell 285b8b572e1SStephen Rothwell #define LOAD_REG_ADDR(reg,name) \ 286b8b572e1SStephen Rothwell ld (reg),name@got(r2) 287b8b572e1SStephen Rothwell 288b8b572e1SStephen Rothwell #define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) 289b8b572e1SStephen Rothwell #define ADDROFF(name) 0 290b8b572e1SStephen Rothwell 291b8b572e1SStephen Rothwell /* offsets for stack frame layout */ 292b8b572e1SStephen Rothwell #define LRSAVE 16 293b8b572e1SStephen Rothwell 294b8b572e1SStephen Rothwell #else /* 32-bit */ 295b8b572e1SStephen Rothwell 296b8b572e1SStephen Rothwell #define LOAD_REG_IMMEDIATE(reg,expr) \ 297b8b572e1SStephen Rothwell lis (reg),(expr)@ha; \ 298b8b572e1SStephen Rothwell addi (reg),(reg),(expr)@l; 299b8b572e1SStephen Rothwell 300b8b572e1SStephen Rothwell #define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE(reg, name) 301b8b572e1SStephen Rothwell 302b8b572e1SStephen Rothwell #define LOAD_REG_ADDRBASE(reg, name) lis (reg),name@ha 303b8b572e1SStephen Rothwell #define ADDROFF(name) name@l 304b8b572e1SStephen Rothwell 305b8b572e1SStephen Rothwell /* offsets for stack frame layout */ 306b8b572e1SStephen Rothwell #define LRSAVE 4 307b8b572e1SStephen Rothwell 308b8b572e1SStephen Rothwell #endif 309b8b572e1SStephen Rothwell 310b8b572e1SStephen Rothwell /* various errata or part fixups */ 311b8b572e1SStephen Rothwell #ifdef CONFIG_PPC601_SYNC_FIX 312b8b572e1SStephen Rothwell #define SYNC \ 313b8b572e1SStephen Rothwell BEGIN_FTR_SECTION \ 314b8b572e1SStephen Rothwell sync; \ 315b8b572e1SStephen Rothwell isync; \ 316b8b572e1SStephen Rothwell END_FTR_SECTION_IFSET(CPU_FTR_601) 317b8b572e1SStephen Rothwell #define SYNC_601 \ 318b8b572e1SStephen Rothwell BEGIN_FTR_SECTION \ 319b8b572e1SStephen Rothwell sync; \ 320b8b572e1SStephen Rothwell END_FTR_SECTION_IFSET(CPU_FTR_601) 321b8b572e1SStephen Rothwell #define ISYNC_601 \ 322b8b572e1SStephen Rothwell BEGIN_FTR_SECTION \ 323b8b572e1SStephen Rothwell isync; \ 324b8b572e1SStephen Rothwell END_FTR_SECTION_IFSET(CPU_FTR_601) 325b8b572e1SStephen Rothwell #else 326b8b572e1SStephen Rothwell #define SYNC 327b8b572e1SStephen Rothwell #define SYNC_601 328b8b572e1SStephen Rothwell #define ISYNC_601 329b8b572e1SStephen Rothwell #endif 330b8b572e1SStephen Rothwell 331b8b572e1SStephen Rothwell #ifdef CONFIG_PPC_CELL 332b8b572e1SStephen Rothwell #define MFTB(dest) \ 333b8b572e1SStephen Rothwell 90: mftb dest; \ 334b8b572e1SStephen Rothwell BEGIN_FTR_SECTION_NESTED(96); \ 335b8b572e1SStephen Rothwell cmpwi dest,0; \ 336b8b572e1SStephen Rothwell beq- 90b; \ 337b8b572e1SStephen Rothwell END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) 338b8b572e1SStephen Rothwell #else 339b8b572e1SStephen Rothwell #define MFTB(dest) mftb dest 340b8b572e1SStephen Rothwell #endif 341b8b572e1SStephen Rothwell 342b8b572e1SStephen Rothwell #ifndef CONFIG_SMP 343b8b572e1SStephen Rothwell #define TLBSYNC 344b8b572e1SStephen Rothwell #else /* CONFIG_SMP */ 345b8b572e1SStephen Rothwell /* tlbsync is not implemented on 601 */ 346b8b572e1SStephen Rothwell #define TLBSYNC \ 347b8b572e1SStephen Rothwell BEGIN_FTR_SECTION \ 348b8b572e1SStephen Rothwell tlbsync; \ 349b8b572e1SStephen Rothwell sync; \ 350b8b572e1SStephen Rothwell END_FTR_SECTION_IFCLR(CPU_FTR_601) 351b8b572e1SStephen Rothwell #endif 352b8b572e1SStephen Rothwell 353b8b572e1SStephen Rothwell 354b8b572e1SStephen Rothwell /* 355b8b572e1SStephen Rothwell * This instruction is not implemented on the PPC 603 or 601; however, on 356b8b572e1SStephen Rothwell * the 403GCX and 405GP tlbia IS defined and tlbie is not. 357b8b572e1SStephen Rothwell * All of these instructions exist in the 8xx, they have magical powers, 358b8b572e1SStephen Rothwell * and they must be used. 359b8b572e1SStephen Rothwell */ 360b8b572e1SStephen Rothwell 361b8b572e1SStephen Rothwell #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) 362b8b572e1SStephen Rothwell #define tlbia \ 363b8b572e1SStephen Rothwell li r4,1024; \ 364b8b572e1SStephen Rothwell mtctr r4; \ 365b8b572e1SStephen Rothwell lis r4,KERNELBASE@h; \ 366b8b572e1SStephen Rothwell 0: tlbie r4; \ 367b8b572e1SStephen Rothwell addi r4,r4,0x1000; \ 368b8b572e1SStephen Rothwell bdnz 0b 369b8b572e1SStephen Rothwell #endif 370b8b572e1SStephen Rothwell 371b8b572e1SStephen Rothwell 372b8b572e1SStephen Rothwell #ifdef CONFIG_IBM440EP_ERR42 373b8b572e1SStephen Rothwell #define PPC440EP_ERR42 isync 374b8b572e1SStephen Rothwell #else 375b8b572e1SStephen Rothwell #define PPC440EP_ERR42 376b8b572e1SStephen Rothwell #endif 377b8b572e1SStephen Rothwell 37844c58cccSBenjamin Herrenschmidt /* 37944c58cccSBenjamin Herrenschmidt * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them 38044c58cccSBenjamin Herrenschmidt * keep the address intact to be compatible with code shared with 38144c58cccSBenjamin Herrenschmidt * 32-bit classic. 38244c58cccSBenjamin Herrenschmidt * 38344c58cccSBenjamin Herrenschmidt * On the other hand, I find it useful to have them behave as expected 38444c58cccSBenjamin Herrenschmidt * by their name (ie always do the addition) on 64-bit BookE 38544c58cccSBenjamin Herrenschmidt */ 38644c58cccSBenjamin Herrenschmidt #if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) 387b8b572e1SStephen Rothwell #define toreal(rd) 388b8b572e1SStephen Rothwell #define fromreal(rd) 389b8b572e1SStephen Rothwell 390b8b572e1SStephen Rothwell /* 391b8b572e1SStephen Rothwell * We use addis to ensure compatibility with the "classic" ppc versions of 392b8b572e1SStephen Rothwell * these macros, which use rs = 0 to get the tophys offset in rd, rather than 393b8b572e1SStephen Rothwell * converting the address in r0, and so this version has to do that too 394b8b572e1SStephen Rothwell * (i.e. set register rd to 0 when rs == 0). 395b8b572e1SStephen Rothwell */ 396b8b572e1SStephen Rothwell #define tophys(rd,rs) \ 397b8b572e1SStephen Rothwell addis rd,rs,0 398b8b572e1SStephen Rothwell 399b8b572e1SStephen Rothwell #define tovirt(rd,rs) \ 400b8b572e1SStephen Rothwell addis rd,rs,0 401b8b572e1SStephen Rothwell 402b8b572e1SStephen Rothwell #elif defined(CONFIG_PPC64) 403b8b572e1SStephen Rothwell #define toreal(rd) /* we can access c000... in real mode */ 404b8b572e1SStephen Rothwell #define fromreal(rd) 405b8b572e1SStephen Rothwell 406b8b572e1SStephen Rothwell #define tophys(rd,rs) \ 407b8b572e1SStephen Rothwell clrldi rd,rs,2 408b8b572e1SStephen Rothwell 409b8b572e1SStephen Rothwell #define tovirt(rd,rs) \ 410b8b572e1SStephen Rothwell rotldi rd,rs,16; \ 411b8b572e1SStephen Rothwell ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ 412b8b572e1SStephen Rothwell rotldi rd,rd,48 413b8b572e1SStephen Rothwell #else 414b8b572e1SStephen Rothwell /* 415b8b572e1SStephen Rothwell * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 416b8b572e1SStephen Rothwell * physical base address of RAM at compile time. 417b8b572e1SStephen Rothwell */ 418b8b572e1SStephen Rothwell #define toreal(rd) tophys(rd,rd) 419b8b572e1SStephen Rothwell #define fromreal(rd) tovirt(rd,rd) 420b8b572e1SStephen Rothwell 421b8b572e1SStephen Rothwell #define tophys(rd,rs) \ 422ccdcef72SDale Farnsworth 0: addis rd,rs,-PAGE_OFFSET@h; \ 423b8b572e1SStephen Rothwell .section ".vtop_fixup","aw"; \ 424b8b572e1SStephen Rothwell .align 1; \ 425b8b572e1SStephen Rothwell .long 0b; \ 426b8b572e1SStephen Rothwell .previous 427b8b572e1SStephen Rothwell 428b8b572e1SStephen Rothwell #define tovirt(rd,rs) \ 429ccdcef72SDale Farnsworth 0: addis rd,rs,PAGE_OFFSET@h; \ 430b8b572e1SStephen Rothwell .section ".ptov_fixup","aw"; \ 431b8b572e1SStephen Rothwell .align 1; \ 432b8b572e1SStephen Rothwell .long 0b; \ 433b8b572e1SStephen Rothwell .previous 434b8b572e1SStephen Rothwell #endif 435b8b572e1SStephen Rothwell 43644c58cccSBenjamin Herrenschmidt #ifdef CONFIG_PPC_BOOK3S_64 437b8b572e1SStephen Rothwell #define RFI rfid 438b8b572e1SStephen Rothwell #define MTMSRD(r) mtmsrd r 439b8b572e1SStephen Rothwell #else 440b8b572e1SStephen Rothwell #define FIX_SRR1(ra, rb) 441b8b572e1SStephen Rothwell #ifndef CONFIG_40x 442b8b572e1SStephen Rothwell #define RFI rfi 443b8b572e1SStephen Rothwell #else 444b8b572e1SStephen Rothwell #define RFI rfi; b . /* Prevent prefetch past rfi */ 445b8b572e1SStephen Rothwell #endif 446b8b572e1SStephen Rothwell #define MTMSRD(r) mtmsr r 447b8b572e1SStephen Rothwell #define CLR_TOP32(r) 448b8b572e1SStephen Rothwell #endif 449b8b572e1SStephen Rothwell 450b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 451b8b572e1SStephen Rothwell 452b8b572e1SStephen Rothwell /* The boring bits... */ 453b8b572e1SStephen Rothwell 454b8b572e1SStephen Rothwell /* Condition Register Bit Fields */ 455b8b572e1SStephen Rothwell 456b8b572e1SStephen Rothwell #define cr0 0 457b8b572e1SStephen Rothwell #define cr1 1 458b8b572e1SStephen Rothwell #define cr2 2 459b8b572e1SStephen Rothwell #define cr3 3 460b8b572e1SStephen Rothwell #define cr4 4 461b8b572e1SStephen Rothwell #define cr5 5 462b8b572e1SStephen Rothwell #define cr6 6 463b8b572e1SStephen Rothwell #define cr7 7 464b8b572e1SStephen Rothwell 465b8b572e1SStephen Rothwell 466b8b572e1SStephen Rothwell /* General Purpose Registers (GPRs) */ 467b8b572e1SStephen Rothwell 468b8b572e1SStephen Rothwell #define r0 0 469b8b572e1SStephen Rothwell #define r1 1 470b8b572e1SStephen Rothwell #define r2 2 471b8b572e1SStephen Rothwell #define r3 3 472b8b572e1SStephen Rothwell #define r4 4 473b8b572e1SStephen Rothwell #define r5 5 474b8b572e1SStephen Rothwell #define r6 6 475b8b572e1SStephen Rothwell #define r7 7 476b8b572e1SStephen Rothwell #define r8 8 477b8b572e1SStephen Rothwell #define r9 9 478b8b572e1SStephen Rothwell #define r10 10 479b8b572e1SStephen Rothwell #define r11 11 480b8b572e1SStephen Rothwell #define r12 12 481b8b572e1SStephen Rothwell #define r13 13 482b8b572e1SStephen Rothwell #define r14 14 483b8b572e1SStephen Rothwell #define r15 15 484b8b572e1SStephen Rothwell #define r16 16 485b8b572e1SStephen Rothwell #define r17 17 486b8b572e1SStephen Rothwell #define r18 18 487b8b572e1SStephen Rothwell #define r19 19 488b8b572e1SStephen Rothwell #define r20 20 489b8b572e1SStephen Rothwell #define r21 21 490b8b572e1SStephen Rothwell #define r22 22 491b8b572e1SStephen Rothwell #define r23 23 492b8b572e1SStephen Rothwell #define r24 24 493b8b572e1SStephen Rothwell #define r25 25 494b8b572e1SStephen Rothwell #define r26 26 495b8b572e1SStephen Rothwell #define r27 27 496b8b572e1SStephen Rothwell #define r28 28 497b8b572e1SStephen Rothwell #define r29 29 498b8b572e1SStephen Rothwell #define r30 30 499b8b572e1SStephen Rothwell #define r31 31 500b8b572e1SStephen Rothwell 501b8b572e1SStephen Rothwell 502b8b572e1SStephen Rothwell /* Floating Point Registers (FPRs) */ 503b8b572e1SStephen Rothwell 504b8b572e1SStephen Rothwell #define fr0 0 505b8b572e1SStephen Rothwell #define fr1 1 506b8b572e1SStephen Rothwell #define fr2 2 507b8b572e1SStephen Rothwell #define fr3 3 508b8b572e1SStephen Rothwell #define fr4 4 509b8b572e1SStephen Rothwell #define fr5 5 510b8b572e1SStephen Rothwell #define fr6 6 511b8b572e1SStephen Rothwell #define fr7 7 512b8b572e1SStephen Rothwell #define fr8 8 513b8b572e1SStephen Rothwell #define fr9 9 514b8b572e1SStephen Rothwell #define fr10 10 515b8b572e1SStephen Rothwell #define fr11 11 516b8b572e1SStephen Rothwell #define fr12 12 517b8b572e1SStephen Rothwell #define fr13 13 518b8b572e1SStephen Rothwell #define fr14 14 519b8b572e1SStephen Rothwell #define fr15 15 520b8b572e1SStephen Rothwell #define fr16 16 521b8b572e1SStephen Rothwell #define fr17 17 522b8b572e1SStephen Rothwell #define fr18 18 523b8b572e1SStephen Rothwell #define fr19 19 524b8b572e1SStephen Rothwell #define fr20 20 525b8b572e1SStephen Rothwell #define fr21 21 526b8b572e1SStephen Rothwell #define fr22 22 527b8b572e1SStephen Rothwell #define fr23 23 528b8b572e1SStephen Rothwell #define fr24 24 529b8b572e1SStephen Rothwell #define fr25 25 530b8b572e1SStephen Rothwell #define fr26 26 531b8b572e1SStephen Rothwell #define fr27 27 532b8b572e1SStephen Rothwell #define fr28 28 533b8b572e1SStephen Rothwell #define fr29 29 534b8b572e1SStephen Rothwell #define fr30 30 535b8b572e1SStephen Rothwell #define fr31 31 536b8b572e1SStephen Rothwell 537b8b572e1SStephen Rothwell /* AltiVec Registers (VPRs) */ 538b8b572e1SStephen Rothwell 539b8b572e1SStephen Rothwell #define vr0 0 540b8b572e1SStephen Rothwell #define vr1 1 541b8b572e1SStephen Rothwell #define vr2 2 542b8b572e1SStephen Rothwell #define vr3 3 543b8b572e1SStephen Rothwell #define vr4 4 544b8b572e1SStephen Rothwell #define vr5 5 545b8b572e1SStephen Rothwell #define vr6 6 546b8b572e1SStephen Rothwell #define vr7 7 547b8b572e1SStephen Rothwell #define vr8 8 548b8b572e1SStephen Rothwell #define vr9 9 549b8b572e1SStephen Rothwell #define vr10 10 550b8b572e1SStephen Rothwell #define vr11 11 551b8b572e1SStephen Rothwell #define vr12 12 552b8b572e1SStephen Rothwell #define vr13 13 553b8b572e1SStephen Rothwell #define vr14 14 554b8b572e1SStephen Rothwell #define vr15 15 555b8b572e1SStephen Rothwell #define vr16 16 556b8b572e1SStephen Rothwell #define vr17 17 557b8b572e1SStephen Rothwell #define vr18 18 558b8b572e1SStephen Rothwell #define vr19 19 559b8b572e1SStephen Rothwell #define vr20 20 560b8b572e1SStephen Rothwell #define vr21 21 561b8b572e1SStephen Rothwell #define vr22 22 562b8b572e1SStephen Rothwell #define vr23 23 563b8b572e1SStephen Rothwell #define vr24 24 564b8b572e1SStephen Rothwell #define vr25 25 565b8b572e1SStephen Rothwell #define vr26 26 566b8b572e1SStephen Rothwell #define vr27 27 567b8b572e1SStephen Rothwell #define vr28 28 568b8b572e1SStephen Rothwell #define vr29 29 569b8b572e1SStephen Rothwell #define vr30 30 570b8b572e1SStephen Rothwell #define vr31 31 571b8b572e1SStephen Rothwell 572b8b572e1SStephen Rothwell /* VSX Registers (VSRs) */ 573b8b572e1SStephen Rothwell 574b8b572e1SStephen Rothwell #define vsr0 0 575b8b572e1SStephen Rothwell #define vsr1 1 576b8b572e1SStephen Rothwell #define vsr2 2 577b8b572e1SStephen Rothwell #define vsr3 3 578b8b572e1SStephen Rothwell #define vsr4 4 579b8b572e1SStephen Rothwell #define vsr5 5 580b8b572e1SStephen Rothwell #define vsr6 6 581b8b572e1SStephen Rothwell #define vsr7 7 582b8b572e1SStephen Rothwell #define vsr8 8 583b8b572e1SStephen Rothwell #define vsr9 9 584b8b572e1SStephen Rothwell #define vsr10 10 585b8b572e1SStephen Rothwell #define vsr11 11 586b8b572e1SStephen Rothwell #define vsr12 12 587b8b572e1SStephen Rothwell #define vsr13 13 588b8b572e1SStephen Rothwell #define vsr14 14 589b8b572e1SStephen Rothwell #define vsr15 15 590b8b572e1SStephen Rothwell #define vsr16 16 591b8b572e1SStephen Rothwell #define vsr17 17 592b8b572e1SStephen Rothwell #define vsr18 18 593b8b572e1SStephen Rothwell #define vsr19 19 594b8b572e1SStephen Rothwell #define vsr20 20 595b8b572e1SStephen Rothwell #define vsr21 21 596b8b572e1SStephen Rothwell #define vsr22 22 597b8b572e1SStephen Rothwell #define vsr23 23 598b8b572e1SStephen Rothwell #define vsr24 24 599b8b572e1SStephen Rothwell #define vsr25 25 600b8b572e1SStephen Rothwell #define vsr26 26 601b8b572e1SStephen Rothwell #define vsr27 27 602b8b572e1SStephen Rothwell #define vsr28 28 603b8b572e1SStephen Rothwell #define vsr29 29 604b8b572e1SStephen Rothwell #define vsr30 30 605b8b572e1SStephen Rothwell #define vsr31 31 606b8b572e1SStephen Rothwell #define vsr32 32 607b8b572e1SStephen Rothwell #define vsr33 33 608b8b572e1SStephen Rothwell #define vsr34 34 609b8b572e1SStephen Rothwell #define vsr35 35 610b8b572e1SStephen Rothwell #define vsr36 36 611b8b572e1SStephen Rothwell #define vsr37 37 612b8b572e1SStephen Rothwell #define vsr38 38 613b8b572e1SStephen Rothwell #define vsr39 39 614b8b572e1SStephen Rothwell #define vsr40 40 615b8b572e1SStephen Rothwell #define vsr41 41 616b8b572e1SStephen Rothwell #define vsr42 42 617b8b572e1SStephen Rothwell #define vsr43 43 618b8b572e1SStephen Rothwell #define vsr44 44 619b8b572e1SStephen Rothwell #define vsr45 45 620b8b572e1SStephen Rothwell #define vsr46 46 621b8b572e1SStephen Rothwell #define vsr47 47 622b8b572e1SStephen Rothwell #define vsr48 48 623b8b572e1SStephen Rothwell #define vsr49 49 624b8b572e1SStephen Rothwell #define vsr50 50 625b8b572e1SStephen Rothwell #define vsr51 51 626b8b572e1SStephen Rothwell #define vsr52 52 627b8b572e1SStephen Rothwell #define vsr53 53 628b8b572e1SStephen Rothwell #define vsr54 54 629b8b572e1SStephen Rothwell #define vsr55 55 630b8b572e1SStephen Rothwell #define vsr56 56 631b8b572e1SStephen Rothwell #define vsr57 57 632b8b572e1SStephen Rothwell #define vsr58 58 633b8b572e1SStephen Rothwell #define vsr59 59 634b8b572e1SStephen Rothwell #define vsr60 60 635b8b572e1SStephen Rothwell #define vsr61 61 636b8b572e1SStephen Rothwell #define vsr62 62 637b8b572e1SStephen Rothwell #define vsr63 63 638b8b572e1SStephen Rothwell 639b8b572e1SStephen Rothwell /* SPE Registers (EVPRs) */ 640b8b572e1SStephen Rothwell 641b8b572e1SStephen Rothwell #define evr0 0 642b8b572e1SStephen Rothwell #define evr1 1 643b8b572e1SStephen Rothwell #define evr2 2 644b8b572e1SStephen Rothwell #define evr3 3 645b8b572e1SStephen Rothwell #define evr4 4 646b8b572e1SStephen Rothwell #define evr5 5 647b8b572e1SStephen Rothwell #define evr6 6 648b8b572e1SStephen Rothwell #define evr7 7 649b8b572e1SStephen Rothwell #define evr8 8 650b8b572e1SStephen Rothwell #define evr9 9 651b8b572e1SStephen Rothwell #define evr10 10 652b8b572e1SStephen Rothwell #define evr11 11 653b8b572e1SStephen Rothwell #define evr12 12 654b8b572e1SStephen Rothwell #define evr13 13 655b8b572e1SStephen Rothwell #define evr14 14 656b8b572e1SStephen Rothwell #define evr15 15 657b8b572e1SStephen Rothwell #define evr16 16 658b8b572e1SStephen Rothwell #define evr17 17 659b8b572e1SStephen Rothwell #define evr18 18 660b8b572e1SStephen Rothwell #define evr19 19 661b8b572e1SStephen Rothwell #define evr20 20 662b8b572e1SStephen Rothwell #define evr21 21 663b8b572e1SStephen Rothwell #define evr22 22 664b8b572e1SStephen Rothwell #define evr23 23 665b8b572e1SStephen Rothwell #define evr24 24 666b8b572e1SStephen Rothwell #define evr25 25 667b8b572e1SStephen Rothwell #define evr26 26 668b8b572e1SStephen Rothwell #define evr27 27 669b8b572e1SStephen Rothwell #define evr28 28 670b8b572e1SStephen Rothwell #define evr29 29 671b8b572e1SStephen Rothwell #define evr30 30 672b8b572e1SStephen Rothwell #define evr31 31 673b8b572e1SStephen Rothwell 674b8b572e1SStephen Rothwell /* some stab codes */ 675b8b572e1SStephen Rothwell #define N_FUN 36 676b8b572e1SStephen Rothwell #define N_RSYM 64 677b8b572e1SStephen Rothwell #define N_SLINE 68 678b8b572e1SStephen Rothwell #define N_SO 100 679b8b572e1SStephen Rothwell 680b8b572e1SStephen Rothwell #endif /* __ASSEMBLY__ */ 681b8b572e1SStephen Rothwell 682b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_PPC_ASM_H */ 683