1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2009 Freescale Semiconductor, Inc.
4  *
5  * provides masks and opcode images for use by code generation, emulation
6  * and for instructions that older assemblers might not know about
7  */
8 #ifndef _ASM_POWERPC_PPC_OPCODE_H
9 #define _ASM_POWERPC_PPC_OPCODE_H
10 
11 #include <asm/asm-const.h>
12 
13 #define	__REG_R0	0
14 #define	__REG_R1	1
15 #define	__REG_R2	2
16 #define	__REG_R3	3
17 #define	__REG_R4	4
18 #define	__REG_R5	5
19 #define	__REG_R6	6
20 #define	__REG_R7	7
21 #define	__REG_R8	8
22 #define	__REG_R9	9
23 #define	__REG_R10	10
24 #define	__REG_R11	11
25 #define	__REG_R12	12
26 #define	__REG_R13	13
27 #define	__REG_R14	14
28 #define	__REG_R15	15
29 #define	__REG_R16	16
30 #define	__REG_R17	17
31 #define	__REG_R18	18
32 #define	__REG_R19	19
33 #define	__REG_R20	20
34 #define	__REG_R21	21
35 #define	__REG_R22	22
36 #define	__REG_R23	23
37 #define	__REG_R24	24
38 #define	__REG_R25	25
39 #define	__REG_R26	26
40 #define	__REG_R27	27
41 #define	__REG_R28	28
42 #define	__REG_R29	29
43 #define	__REG_R30	30
44 #define	__REG_R31	31
45 
46 #define	__REGA0_0	0
47 #define	__REGA0_R1	1
48 #define	__REGA0_R2	2
49 #define	__REGA0_R3	3
50 #define	__REGA0_R4	4
51 #define	__REGA0_R5	5
52 #define	__REGA0_R6	6
53 #define	__REGA0_R7	7
54 #define	__REGA0_R8	8
55 #define	__REGA0_R9	9
56 #define	__REGA0_R10	10
57 #define	__REGA0_R11	11
58 #define	__REGA0_R12	12
59 #define	__REGA0_R13	13
60 #define	__REGA0_R14	14
61 #define	__REGA0_R15	15
62 #define	__REGA0_R16	16
63 #define	__REGA0_R17	17
64 #define	__REGA0_R18	18
65 #define	__REGA0_R19	19
66 #define	__REGA0_R20	20
67 #define	__REGA0_R21	21
68 #define	__REGA0_R22	22
69 #define	__REGA0_R23	23
70 #define	__REGA0_R24	24
71 #define	__REGA0_R25	25
72 #define	__REGA0_R26	26
73 #define	__REGA0_R27	27
74 #define	__REGA0_R28	28
75 #define	__REGA0_R29	29
76 #define	__REGA0_R30	30
77 #define	__REGA0_R31	31
78 
79 #define IMM_L(i)               ((uintptr_t)(i) & 0xffff)
80 #define IMM_DS(i)              ((uintptr_t)(i) & 0xfffc)
81 #define IMM_DQ(i)              ((uintptr_t)(i) & 0xfff0)
82 #define IMM_D0(i)              (((uintptr_t)(i) >> 16) & 0x3ffff)
83 #define IMM_D1(i)              IMM_L(i)
84 
85 /*
86  * 16-bit immediate helper macros: HA() is for use with sign-extending instrs
87  * (e.g. LD, ADDI).  If the bottom 16 bits is "-ve", add another bit into the
88  * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
89  */
90 #define IMM_H(i)                ((uintptr_t)(i)>>16)
91 #define IMM_HA(i)               (((uintptr_t)(i)>>16) +                       \
92 					(((uintptr_t)(i) & 0x8000) >> 15))
93 
94 
95 /* opcode and xopcode for instructions */
96 #define OP_TRAP 3
97 #define OP_TRAP_64 2
98 
99 #define OP_31_XOP_TRAP      4
100 #define OP_31_XOP_LDX       21
101 #define OP_31_XOP_LWZX      23
102 #define OP_31_XOP_LDUX      53
103 #define OP_31_XOP_DCBST     54
104 #define OP_31_XOP_LWZUX     55
105 #define OP_31_XOP_TRAP_64   68
106 #define OP_31_XOP_DCBF      86
107 #define OP_31_XOP_LBZX      87
108 #define OP_31_XOP_STDX      149
109 #define OP_31_XOP_STWX      151
110 #define OP_31_XOP_STDUX     181
111 #define OP_31_XOP_STWUX     183
112 #define OP_31_XOP_STBX      215
113 #define OP_31_XOP_LBZUX     119
114 #define OP_31_XOP_STBUX     247
115 #define OP_31_XOP_LHZX      279
116 #define OP_31_XOP_LHZUX     311
117 #define OP_31_XOP_MSGSNDP   142
118 #define OP_31_XOP_MSGCLRP   174
119 #define OP_31_XOP_TLBIE     306
120 #define OP_31_XOP_MFSPR     339
121 #define OP_31_XOP_LWAX      341
122 #define OP_31_XOP_LHAX      343
123 #define OP_31_XOP_LWAUX     373
124 #define OP_31_XOP_LHAUX     375
125 #define OP_31_XOP_STHX      407
126 #define OP_31_XOP_STHUX     439
127 #define OP_31_XOP_MTSPR     467
128 #define OP_31_XOP_DCBI      470
129 #define OP_31_XOP_LDBRX     532
130 #define OP_31_XOP_LWBRX     534
131 #define OP_31_XOP_TLBSYNC   566
132 #define OP_31_XOP_STDBRX    660
133 #define OP_31_XOP_STWBRX    662
134 #define OP_31_XOP_STFSX	    663
135 #define OP_31_XOP_STFSUX    695
136 #define OP_31_XOP_STFDX     727
137 #define OP_31_XOP_STFDUX    759
138 #define OP_31_XOP_LHBRX     790
139 #define OP_31_XOP_LFIWAX    855
140 #define OP_31_XOP_LFIWZX    887
141 #define OP_31_XOP_STHBRX    918
142 #define OP_31_XOP_STFIWX    983
143 
144 /* VSX Scalar Load Instructions */
145 #define OP_31_XOP_LXSDX         588
146 #define OP_31_XOP_LXSSPX        524
147 #define OP_31_XOP_LXSIWAX       76
148 #define OP_31_XOP_LXSIWZX       12
149 
150 /* VSX Scalar Store Instructions */
151 #define OP_31_XOP_STXSDX        716
152 #define OP_31_XOP_STXSSPX       652
153 #define OP_31_XOP_STXSIWX       140
154 
155 /* VSX Vector Load Instructions */
156 #define OP_31_XOP_LXVD2X        844
157 #define OP_31_XOP_LXVW4X        780
158 
159 /* VSX Vector Load and Splat Instruction */
160 #define OP_31_XOP_LXVDSX        332
161 
162 /* VSX Vector Store Instructions */
163 #define OP_31_XOP_STXVD2X       972
164 #define OP_31_XOP_STXVW4X       908
165 
166 #define OP_31_XOP_LFSX          535
167 #define OP_31_XOP_LFSUX         567
168 #define OP_31_XOP_LFDX          599
169 #define OP_31_XOP_LFDUX		631
170 
171 /* VMX Vector Load Instructions */
172 #define OP_31_XOP_LVX           103
173 
174 /* VMX Vector Store Instructions */
175 #define OP_31_XOP_STVX          231
176 
177 /* Prefixed Instructions */
178 #define OP_PREFIX		1
179 
180 #define OP_31   31
181 #define OP_LWZ  32
182 #define OP_STFS 52
183 #define OP_STFSU 53
184 #define OP_STFD 54
185 #define OP_STFDU 55
186 #define OP_LD   58
187 #define OP_LWZU 33
188 #define OP_LBZ  34
189 #define OP_LBZU 35
190 #define OP_STW  36
191 #define OP_STWU 37
192 #define OP_STD  62
193 #define OP_STB  38
194 #define OP_STBU 39
195 #define OP_LHZ  40
196 #define OP_LHZU 41
197 #define OP_LHA  42
198 #define OP_LHAU 43
199 #define OP_STH  44
200 #define OP_STHU 45
201 #define OP_LMW  46
202 #define OP_STMW 47
203 #define OP_LFS  48
204 #define OP_LFSU 49
205 #define OP_LFD  50
206 #define OP_LFDU 51
207 #define OP_STFS 52
208 #define OP_STFSU 53
209 #define OP_STFD  54
210 #define OP_STFDU 55
211 #define OP_LQ    56
212 
213 /* sorted alphabetically */
214 #define PPC_INST_BCCTR_FLUSH		0x4c400420
215 #define PPC_INST_COPY			0x7c20060c
216 #define PPC_INST_DCBA			0x7c0005ec
217 #define PPC_INST_DCBA_MASK		0xfc0007fe
218 #define PPC_INST_ISEL			0x7c00001e
219 #define PPC_INST_ISEL_MASK		0xfc00003e
220 #define PPC_INST_LSWI			0x7c0004aa
221 #define PPC_INST_LSWX			0x7c00042a
222 #define PPC_INST_LWSYNC			0x7c2004ac
223 #define PPC_INST_SYNC			0x7c0004ac
224 #define PPC_INST_SYNC_MASK		0xfc0007fe
225 #define PPC_INST_ISYNC			0x4c00012c
226 #define PPC_INST_MCRXR			0x7c000400
227 #define PPC_INST_MCRXR_MASK		0xfc0007fe
228 #define PPC_INST_MFSPR_PVR		0x7c1f42a6
229 #define PPC_INST_MFSPR_PVR_MASK		0xfc1ffffe
230 #define PPC_INST_MTMSRD			0x7c000164
231 #define PPC_INST_NOP			0x60000000
232 #define PPC_INST_POPCNTB		0x7c0000f4
233 #define PPC_INST_POPCNTB_MASK		0xfc0007fe
234 #define PPC_INST_RFEBB			0x4c000124
235 #define PPC_INST_RFID			0x4c000024
236 #define PPC_INST_MFSPR_DSCR		0x7c1102a6
237 #define PPC_INST_MFSPR_DSCR_MASK	0xfc1ffffe
238 #define PPC_INST_MTSPR_DSCR		0x7c1103a6
239 #define PPC_INST_MTSPR_DSCR_MASK	0xfc1ffffe
240 #define PPC_INST_MFSPR_DSCR_USER	0x7c0302a6
241 #define PPC_INST_MFSPR_DSCR_USER_MASK	0xfc1ffffe
242 #define PPC_INST_MTSPR_DSCR_USER	0x7c0303a6
243 #define PPC_INST_MTSPR_DSCR_USER_MASK	0xfc1ffffe
244 #define PPC_INST_SC			0x44000002
245 #define PPC_INST_STRING			0x7c00042a
246 #define PPC_INST_STRING_MASK		0xfc0007fe
247 #define PPC_INST_STRING_GEN_MASK	0xfc00067e
248 #define PPC_INST_STSWI			0x7c0005aa
249 #define PPC_INST_STSWX			0x7c00052a
250 #define PPC_INST_TRECHKPT		0x7c0007dd
251 #define PPC_INST_TRECLAIM		0x7c00075d
252 #define PPC_INST_TSR			0x7c0005dd
253 #define PPC_INST_LD			0xe8000000
254 #define PPC_INST_STD			0xf8000000
255 #define PPC_INST_MFLR			0x7c0802a6
256 #define PPC_INST_MTCTR			0x7c0903a6
257 #define PPC_INST_ADDI			0x38000000
258 #define PPC_INST_ADDIS			0x3c000000
259 #define PPC_INST_ADD			0x7c000214
260 #define PPC_INST_BLR			0x4e800020
261 #define PPC_INST_BCTR			0x4e800420
262 #define PPC_INST_BCTRL			0x4e800421
263 #define PPC_INST_DIVD			0x7c0003d2
264 #define PPC_INST_RLDICR			0x78000004
265 #define PPC_INST_ORI			0x60000000
266 #define PPC_INST_ORIS			0x64000000
267 #define PPC_INST_BRANCH			0x48000000
268 #define PPC_INST_BL			0x48000001
269 #define PPC_INST_BRANCH_COND		0x40800000
270 
271 /* Prefixes */
272 #define PPC_INST_LFS			0xc0000000
273 #define PPC_INST_STFS			0xd0000000
274 #define PPC_INST_LFD			0xc8000000
275 #define PPC_INST_STFD			0xd8000000
276 #define PPC_PREFIX_MLS			0x06000000
277 #define PPC_PREFIX_8LS			0x04000000
278 
279 /* Prefixed instructions */
280 #define PPC_INST_PLD			0xe4000000
281 #define PPC_INST_PSTD			0xf4000000
282 
283 /* macros to insert fields into opcodes */
284 #define ___PPC_RA(a)	(((a) & 0x1f) << 16)
285 #define ___PPC_RB(b)	(((b) & 0x1f) << 11)
286 #define ___PPC_RC(c)	(((c) & 0x1f) << 6)
287 #define ___PPC_RS(s)	(((s) & 0x1f) << 21)
288 #define ___PPC_RT(t)	___PPC_RS(t)
289 #define ___PPC_R(r)	(((r) & 0x1) << 16)
290 #define ___PPC_PRS(prs)	(((prs) & 0x1) << 17)
291 #define ___PPC_RIC(ric)	(((ric) & 0x3) << 18)
292 #define __PPC_RA(a)	___PPC_RA(__REG_##a)
293 #define __PPC_RA0(a)	___PPC_RA(__REGA0_##a)
294 #define __PPC_RB(b)	___PPC_RB(__REG_##b)
295 #define __PPC_RS(s)	___PPC_RS(__REG_##s)
296 #define __PPC_RT(t)	___PPC_RT(__REG_##t)
297 #define __PPC_XA(a)	((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
298 #define __PPC_XB(b)	((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
299 #define __PPC_XS(s)	((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
300 #define __PPC_XT(s)	__PPC_XS(s)
301 #define __PPC_XSP(s)	((((s) & 0x1e) | (((s) >> 5) & 0x1)) << 21)
302 #define __PPC_XTP(s)	__PPC_XSP(s)
303 #define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
304 #define __PPC_WC(w)	(((w) & 0x3) << 21)
305 #define __PPC_WS(w)	(((w) & 0x1f) << 11)
306 #define __PPC_SH(s)	__PPC_WS(s)
307 #define __PPC_SH64(s)	(__PPC_SH(s) | (((s) & 0x20) >> 4))
308 #define __PPC_MB(s)	___PPC_RC(s)
309 #define __PPC_ME(s)	(((s) & 0x1f) << 1)
310 #define __PPC_MB64(s)	(__PPC_MB(s) | ((s) & 0x20))
311 #define __PPC_ME64(s)	__PPC_MB64(s)
312 #define __PPC_BI(s)	(((s) & 0x1f) << 16)
313 #define __PPC_CT(t)	(((t) & 0x0f) << 21)
314 #define __PPC_SPR(r)	((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11))
315 #define __PPC_RC21	(0x1 << 10)
316 #define __PPC_PRFX_R(r)	(((r) & 0x1) << 20)
317 
318 /*
319  * Both low and high 16 bits are added as SIGNED additions, so if low 16 bits
320  * has high bit set, high 16 bits must be adjusted. These macros do that (stolen
321  * from binutils).
322  */
323 #define PPC_LO(v)	((v) & 0xffff)
324 #define PPC_HI(v)	(((v) >> 16) & 0xffff)
325 #define PPC_HA(v)	PPC_HI((v) + 0x8000)
326 
327 /*
328  * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
329  * larx with EH set as an illegal instruction.
330  */
331 #ifdef CONFIG_PPC64
332 #define __PPC_EH(eh)	(((eh) & 0x1) << 0)
333 #else
334 #define __PPC_EH(eh)	0
335 #endif
336 
337 /* Base instruction encoding */
338 #define PPC_RAW_CP_ABORT		(0x7c00068c)
339 #define PPC_RAW_COPY(a, b)		(PPC_INST_COPY | ___PPC_RA(a) | ___PPC_RB(b))
340 #define PPC_RAW_DARN(t, l)		(0x7c0005e6 | ___PPC_RT(t) | (((l) & 0x3) << 16))
341 #define PPC_RAW_DCBAL(a, b)		(0x7c2005ec | __PPC_RA(a) | __PPC_RB(b))
342 #define PPC_RAW_DCBZL(a, b)		(0x7c2007ec | __PPC_RA(a) | __PPC_RB(b))
343 #define PPC_RAW_LQARX(t, a, b, eh)	(0x7c000228 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
344 #define PPC_RAW_LDARX(t, a, b, eh)	(0x7c0000a8 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
345 #define PPC_RAW_LWARX(t, a, b, eh)	(0x7c000028 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | __PPC_EH(eh))
346 #define PPC_RAW_PHWSYNC			(0x7c8004ac)
347 #define PPC_RAW_PLWSYNC			(0x7ca004ac)
348 #define PPC_RAW_STQCX(t, a, b)		(0x7c00016d | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
349 #define PPC_RAW_MADDHD(t, a, b, c)	(0x10000030 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
350 #define PPC_RAW_MADDHDU(t, a, b, c)	(0x10000031 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
351 #define PPC_RAW_MADDLD(t, a, b, c)	(0x10000033 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | ___PPC_RC(c))
352 #define PPC_RAW_MSGSND(b)		(0x7c00019c | ___PPC_RB(b))
353 #define PPC_RAW_MSGSYNC			(0x7c0006ec)
354 #define PPC_RAW_MSGCLR(b)		(0x7c0001dc | ___PPC_RB(b))
355 #define PPC_RAW_MSGSNDP(b)		(0x7c00011c | ___PPC_RB(b))
356 #define PPC_RAW_MSGCLRP(b)		(0x7c00015c | ___PPC_RB(b))
357 #define PPC_RAW_PASTE(a, b)		(0x7c20070d | ___PPC_RA(a) | ___PPC_RB(b))
358 #define PPC_RAW_POPCNTB(a, s)		(PPC_INST_POPCNTB | __PPC_RA(a) | __PPC_RS(s))
359 #define PPC_RAW_POPCNTD(a, s)		(0x7c0003f4 | __PPC_RA(a) | __PPC_RS(s))
360 #define PPC_RAW_POPCNTW(a, s)		(0x7c0002f4 | __PPC_RA(a) | __PPC_RS(s))
361 #define PPC_RAW_RFCI			(0x4c000066)
362 #define PPC_RAW_RFDI			(0x4c00004e)
363 #define PPC_RAW_RFMCI			(0x4c00004c)
364 #define PPC_RAW_TLBILX(t, a, b)		(0x7c000024 | __PPC_T_TLB(t) | 	__PPC_RA0(a) | __PPC_RB(b))
365 #define PPC_RAW_WAIT(w)			(0x7c00007c | __PPC_WC(w))
366 #define PPC_RAW_TLBIE(lp, a)		(0x7c000264 | ___PPC_RB(a) | ___PPC_RS(lp))
367 #define PPC_RAW_TLBIE_5(rb, rs, ric, prs, r) \
368 	(0x7c000264 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
369 #define PPC_RAW_TLBIEL(rb, rs, ric, prs, r) \
370 	(0x7c000224 | ___PPC_RB(rb) | ___PPC_RS(rs) | ___PPC_RIC(ric) | ___PPC_PRS(prs) | ___PPC_R(r))
371 #define PPC_RAW_TLBSRX_DOT(a, b)	(0x7c0006a5 | __PPC_RA0(a) | __PPC_RB(b))
372 #define PPC_RAW_TLBIVAX(a, b)		(0x7c000624 | __PPC_RA0(a) | __PPC_RB(b))
373 #define PPC_RAW_ERATWE(s, a, w)		(0x7c0001a6 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
374 #define PPC_RAW_ERATRE(s, a, w)		(0x7c000166 | __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
375 #define PPC_RAW_ERATILX(t, a, b)	(0x7c000066 | __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
376 #define PPC_RAW_ERATIVAX(s, a, b)	(0x7c000666 | __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
377 #define PPC_RAW_ERATSX(t, a, w)		(0x7c000126 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
378 #define PPC_RAW_ERATSX_DOT(t, a, w)	(0x7c000127 | __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
379 #define PPC_RAW_SLBFEE_DOT(t, b)	(0x7c0007a7 | __PPC_RT(t) | __PPC_RB(b))
380 #define __PPC_RAW_SLBFEE_DOT(t, b)	(0x7c0007a7 | ___PPC_RT(t) | ___PPC_RB(b))
381 #define PPC_RAW_ICBT(c, a, b)		(0x7c00002c | __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b))
382 #define PPC_RAW_LBZCIX(t, a, b)		(0x7c0006aa | __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
383 #define PPC_RAW_STBCIX(s, a, b)		(0x7c0007aa | __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
384 #define PPC_RAW_DCBFPS(a, b)		(0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (4 << 21))
385 #define PPC_RAW_DCBSTPS(a, b)		(0x7c0000ac | ___PPC_RA(a) | ___PPC_RB(b) | (6 << 21))
386 /*
387  * Define what the VSX XX1 form instructions will look like, then add
388  * the 128 bit load store instructions based on that.
389  */
390 #define VSX_XX1(s, a, b)		(__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
391 #define VSX_XX3(t, a, b)		(__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
392 #define PPC_RAW_STXVD2X(s, a, b)	(0x7c000798 | VSX_XX1((s), a, b))
393 #define PPC_RAW_LXVD2X(s, a, b)		(0x7c000698 | VSX_XX1((s), a, b))
394 #define PPC_RAW_MFVRD(a, t)		(0x7c000066 | VSX_XX1((t) + 32, a, R0))
395 #define PPC_RAW_MTVRD(t, a)		(0x7c000166 | VSX_XX1((t) + 32, a, R0))
396 #define PPC_RAW_VPMSUMW(t, a, b)	(0x10000488 | VSX_XX3((t), a, b))
397 #define PPC_RAW_VPMSUMD(t, a, b)	(0x100004c8 | VSX_XX3((t), a, b))
398 #define PPC_RAW_XXLOR(t, a, b)		(0xf0000490 | VSX_XX3((t), a, b))
399 #define PPC_RAW_XXSWAPD(t, a)		(0xf0000250 | VSX_XX3((t), a, a))
400 #define PPC_RAW_XVCPSGNDP(t, a, b)	((0xf0000780 | VSX_XX3((t), (a), (b))))
401 #define PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc) \
402 	((0x1000002d | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | (((vrc) & 0x1f) << 6)))
403 #define PPC_RAW_LXVP(xtp, a, i)		(0x18000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_DQ(i))
404 #define PPC_RAW_STXVP(xsp, a, i)	(0x18000001 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_DQ(i))
405 #define PPC_RAW_LXVPX(xtp, a, b)	(0x7c00029a | __PPC_XTP(xtp) | ___PPC_RA(a) | ___PPC_RB(b))
406 #define PPC_RAW_STXVPX(xsp, a, b)	(0x7c00039a | __PPC_XSP(xsp) | ___PPC_RA(a) | ___PPC_RB(b))
407 #define PPC_RAW_PLXVP(xtp, i, a, pr) \
408 	((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xe8000000 | __PPC_XTP(xtp) | ___PPC_RA(a) | IMM_D1(i)))
409 #define PPC_RAW_PSTXVP(xsp, i, a, pr) \
410 	((PPC_PREFIX_8LS | __PPC_PRFX_R(pr) | IMM_D0(i)) << 32 | (0xf8000000 | __PPC_XSP(xsp) | ___PPC_RA(a) | IMM_D1(i)))
411 #define PPC_RAW_NAP			(0x4c000364)
412 #define PPC_RAW_SLEEP			(0x4c0003a4)
413 #define PPC_RAW_WINKLE			(0x4c0003e4)
414 #define PPC_RAW_STOP			(0x4c0002e4)
415 #define PPC_RAW_CLRBHRB			(0x7c00035c)
416 #define PPC_RAW_MFBHRBE(r, n)		(0x7c00025c | __PPC_RT(r) | (((n) & 0x3ff) << 11))
417 #define PPC_RAW_TRECHKPT		(PPC_INST_TRECHKPT)
418 #define PPC_RAW_TRECLAIM(r)		(PPC_INST_TRECLAIM | __PPC_RA(r))
419 #define PPC_RAW_TABORT(r)		(0x7c00071d | __PPC_RA(r))
420 #define TMRN(x)				((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6))
421 #define PPC_RAW_MTTMR(tmr, r)		(0x7c0003dc | TMRN(tmr) | ___PPC_RS(r))
422 #define PPC_RAW_MFTMR(tmr, r)		(0x7c0002dc | TMRN(tmr) | ___PPC_RT(r))
423 #define PPC_RAW_ICSWX(s, a, b)		(0x7c00032d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
424 #define PPC_RAW_ICSWEPX(s, a, b)	(0x7c00076d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
425 #define PPC_RAW_SLBIA(IH)		(0x7c0003e4 | (((IH) & 0x7) << 21))
426 #define PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb) \
427 	(0x100000c7 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
428 #define PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb) \
429 	(0x10000006 | ___PPC_RT(vrt) | ___PPC_RA(vra) | ___PPC_RB(vrb) | __PPC_RC21)
430 #define PPC_RAW_LD(r, base, i)		(PPC_INST_LD | ___PPC_RT(r) | ___PPC_RA(base) | IMM_DS(i))
431 #define PPC_RAW_LWZ(r, base, i)		(0x80000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
432 #define PPC_RAW_LWZX(t, a, b)		(0x7c00002e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
433 #define PPC_RAW_STD(r, base, i)		(PPC_INST_STD | ___PPC_RS(r) | ___PPC_RA(base) | IMM_DS(i))
434 #define PPC_RAW_STDCX(s, a, b)		(0x7c0001ad | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
435 #define PPC_RAW_LFSX(t, a, b)		(0x7c00042e | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
436 #define PPC_RAW_STFSX(s, a, b)		(0x7c00052e | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
437 #define PPC_RAW_LFDX(t, a, b)		(0x7c0004ae | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
438 #define PPC_RAW_STFDX(s, a, b)		(0x7c0005ae | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
439 #define PPC_RAW_LVX(t, a, b)		(0x7c0000ce | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
440 #define PPC_RAW_STVX(s, a, b)		(0x7c0001ce | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
441 #define PPC_RAW_ADDE(t, a, b)		(0x7c000114 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
442 #define PPC_RAW_ADDZE(t, a)		(0x7c000194 | ___PPC_RT(t) | ___PPC_RA(a))
443 #define PPC_RAW_ADDME(t, a)		(0x7c0001d4 | ___PPC_RT(t) | ___PPC_RA(a))
444 #define PPC_RAW_ADD(t, a, b)		(PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
445 #define PPC_RAW_ADD_DOT(t, a, b)	(PPC_INST_ADD | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
446 #define PPC_RAW_ADDC(t, a, b)		(0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
447 #define PPC_RAW_ADDC_DOT(t, a, b)	(0x7c000014 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
448 #define PPC_RAW_NOP()			(PPC_INST_NOP)
449 #define PPC_RAW_BLR()			(PPC_INST_BLR)
450 #define PPC_RAW_BLRL()			(0x4e800021)
451 #define PPC_RAW_MTLR(r)			(0x7c0803a6 | ___PPC_RT(r))
452 #define PPC_RAW_MFLR(t)			(PPC_INST_MFLR | ___PPC_RT(t))
453 #define PPC_RAW_BCTR()			(PPC_INST_BCTR)
454 #define PPC_RAW_MTCTR(r)		(PPC_INST_MTCTR | ___PPC_RT(r))
455 #define PPC_RAW_ADDI(d, a, i)		(PPC_INST_ADDI | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
456 #define PPC_RAW_LI(r, i)		PPC_RAW_ADDI(r, 0, i)
457 #define PPC_RAW_ADDIS(d, a, i)		(PPC_INST_ADDIS | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
458 #define PPC_RAW_ADDIC(d, a, i)		(0x30000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
459 #define PPC_RAW_ADDIC_DOT(d, a, i)	(0x34000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
460 #define PPC_RAW_LIS(r, i)		PPC_RAW_ADDIS(r, 0, i)
461 #define PPC_RAW_STDX(r, base, b)	(0x7c00012a | ___PPC_RS(r) | ___PPC_RA(base) | ___PPC_RB(b))
462 #define PPC_RAW_STDU(r, base, i)	(0xf8000001 | ___PPC_RS(r) | ___PPC_RA(base) | ((i) & 0xfffc))
463 #define PPC_RAW_STW(r, base, i)		(0x90000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
464 #define PPC_RAW_STWU(r, base, i)	(0x94000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
465 #define PPC_RAW_STH(r, base, i)		(0xb0000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
466 #define PPC_RAW_STB(r, base, i)		(0x98000000 | ___PPC_RS(r) | ___PPC_RA(base) | IMM_L(i))
467 #define PPC_RAW_LBZ(r, base, i)		(0x88000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
468 #define PPC_RAW_LDX(r, base, b)		(0x7c00002a | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
469 #define PPC_RAW_LHZ(r, base, i)		(0xa0000000 | ___PPC_RT(r) | ___PPC_RA(base) | IMM_L(i))
470 #define PPC_RAW_LHBRX(r, base, b)	(0x7c00062c | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
471 #define PPC_RAW_LDBRX(r, base, b)	(0x7c000428 | ___PPC_RT(r) | ___PPC_RA(base) | ___PPC_RB(b))
472 #define PPC_RAW_STWCX(s, a, b)		(0x7c00012d | ___PPC_RS(s) | ___PPC_RA(a) | ___PPC_RB(b))
473 #define PPC_RAW_CMPWI(a, i)		(0x2c000000 | ___PPC_RA(a) | IMM_L(i))
474 #define PPC_RAW_CMPDI(a, i)		(0x2c200000 | ___PPC_RA(a) | IMM_L(i))
475 #define PPC_RAW_CMPW(a, b)		(0x7c000000 | ___PPC_RA(a) | ___PPC_RB(b))
476 #define PPC_RAW_CMPD(a, b)		(0x7c200000 | ___PPC_RA(a) | ___PPC_RB(b))
477 #define PPC_RAW_CMPLWI(a, i)		(0x28000000 | ___PPC_RA(a) | IMM_L(i))
478 #define PPC_RAW_CMPLDI(a, i)		(0x28200000 | ___PPC_RA(a) | IMM_L(i))
479 #define PPC_RAW_CMPLW(a, b)		(0x7c000040 | ___PPC_RA(a) | ___PPC_RB(b))
480 #define PPC_RAW_CMPLD(a, b)		(0x7c200040 | ___PPC_RA(a) | ___PPC_RB(b))
481 #define PPC_RAW_SUB(d, a, b)		(0x7c000050 | ___PPC_RT(d) | ___PPC_RB(a) | ___PPC_RA(b))
482 #define PPC_RAW_SUBFC(d, a, b)		(0x7c000010 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
483 #define PPC_RAW_SUBFE(d, a, b)		(0x7c000110 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
484 #define PPC_RAW_SUBFIC(d, a, i)		(0x20000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
485 #define PPC_RAW_SUBFZE(d, a)		(0x7c000190 | ___PPC_RT(d) | ___PPC_RA(a))
486 #define PPC_RAW_MULD(d, a, b)		(0x7c0001d2 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
487 #define PPC_RAW_MULW(d, a, b)		(0x7c0001d6 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
488 #define PPC_RAW_MULHWU(d, a, b)		(0x7c000016 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
489 #define PPC_RAW_MULI(d, a, i)		(0x1c000000 | ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i))
490 #define PPC_RAW_DIVWU(d, a, b)		(0x7c000396 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
491 #define PPC_RAW_DIVDU(d, a, b)		(0x7c000392 | ___PPC_RT(d) | ___PPC_RA(a) | ___PPC_RB(b))
492 #define PPC_RAW_DIVDE(t, a, b)		(0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
493 #define PPC_RAW_DIVDE_DOT(t, a, b)	(0x7c000352 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
494 #define PPC_RAW_DIVDEU(t, a, b)		(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b))
495 #define PPC_RAW_DIVDEU_DOT(t, a, b)	(0x7c000312 | ___PPC_RT(t) | ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
496 #define PPC_RAW_AND(d, a, b)		(0x7c000038 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
497 #define PPC_RAW_ANDI(d, a, i)		(0x70000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
498 #define PPC_RAW_ANDIS(d, a, i)		(0x74000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
499 #define PPC_RAW_AND_DOT(d, a, b)	(0x7c000039 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
500 #define PPC_RAW_OR(d, a, b)		(0x7c000378 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
501 #define PPC_RAW_MR(d, a)		PPC_RAW_OR(d, a, a)
502 #define PPC_RAW_ORI(d, a, i)		(PPC_INST_ORI | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
503 #define PPC_RAW_ORIS(d, a, i)		(PPC_INST_ORIS | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
504 #define PPC_RAW_NOR(d, a, b)		(0x7c0000f8 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
505 #define PPC_RAW_XOR(d, a, b)		(0x7c000278 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(b))
506 #define PPC_RAW_XORI(d, a, i)		(0x68000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
507 #define PPC_RAW_XORIS(d, a, i)		(0x6c000000 | ___PPC_RA(d) | ___PPC_RS(a) | IMM_L(i))
508 #define PPC_RAW_EXTSW(d, a)		(0x7c0007b4 | ___PPC_RA(d) | ___PPC_RS(a))
509 #define PPC_RAW_SLW(d, a, s)		(0x7c000030 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
510 #define PPC_RAW_SLD(d, a, s)		(0x7c000036 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
511 #define PPC_RAW_SRW(d, a, s)		(0x7c000430 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
512 #define PPC_RAW_SRAW(d, a, s)		(0x7c000630 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
513 #define PPC_RAW_SRAWI(d, a, i)		(0x7c000670 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i))
514 #define PPC_RAW_SRD(d, a, s)		(0x7c000436 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
515 #define PPC_RAW_SRAD(d, a, s)		(0x7c000634 | ___PPC_RA(d) | ___PPC_RS(a) | ___PPC_RB(s))
516 #define PPC_RAW_SRADI(d, a, i)		(0x7c000674 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i))
517 #define PPC_RAW_RLWINM(d, a, i, mb, me)	(0x54000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
518 #define PPC_RAW_RLWINM_DOT(d, a, i, mb, me) \
519 					(0x54000001 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
520 #define PPC_RAW_RLWIMI(d, a, i, mb, me) (0x50000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH(i) | __PPC_MB(mb) | __PPC_ME(me))
521 #define PPC_RAW_RLDICL(d, a, i, mb)     (0x78000000 | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_MB64(mb))
522 #define PPC_RAW_RLDICR(d, a, i, me)     (PPC_INST_RLDICR | ___PPC_RA(d) | ___PPC_RS(a) | __PPC_SH64(i) | __PPC_ME64(me))
523 
524 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */
525 #define PPC_RAW_SLWI(d, a, i)		PPC_RAW_RLWINM(d, a, i, 0, 31-(i))
526 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
527 #define PPC_RAW_SRWI(d, a, i)		PPC_RAW_RLWINM(d, a, 32-(i), i, 31)
528 /* sldi = rldicr Rx, Ry, n, 63-n */
529 #define PPC_RAW_SLDI(d, a, i)		PPC_RAW_RLDICR(d, a, i, 63-(i))
530 /* sldi = rldicl Rx, Ry, 64-n, n */
531 #define PPC_RAW_SRDI(d, a, i)		PPC_RAW_RLDICL(d, a, 64-(i), i)
532 
533 #define PPC_RAW_NEG(d, a)		(0x7c0000d0 | ___PPC_RT(d) | ___PPC_RA(a))
534 
535 #define PPC_RAW_MFSPR(d, spr)		(0x7c0002a6 | ___PPC_RT(d) | __PPC_SPR(spr))
536 
537 /* Deal with instructions that older assemblers aren't aware of */
538 #define	PPC_BCCTR_FLUSH		stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
539 #define	PPC_CP_ABORT		stringify_in_c(.long PPC_RAW_CP_ABORT)
540 #define	PPC_COPY(a, b)		stringify_in_c(.long PPC_RAW_COPY(a, b))
541 #define PPC_DARN(t, l)		stringify_in_c(.long PPC_RAW_DARN(t, l))
542 #define	PPC_DCBAL(a, b)		stringify_in_c(.long PPC_RAW_DCBAL(a, b))
543 #define	PPC_DCBZL(a, b)		stringify_in_c(.long PPC_RAW_DCBZL(a, b))
544 #define	PPC_DIVDE(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDE(t, a, b))
545 #define	PPC_DIVDEU(t, a, b)	stringify_in_c(.long PPC_RAW_DIVDEU(t, a, b))
546 #define PPC_LQARX(t, a, b, eh)	stringify_in_c(.long PPC_RAW_LQARX(t, a, b, eh))
547 #define PPC_LDARX(t, a, b, eh)	stringify_in_c(.long PPC_RAW_LDARX(t, a, b, eh))
548 #define PPC_LWARX(t, a, b, eh)	stringify_in_c(.long PPC_RAW_LWARX(t, a, b, eh))
549 #define PPC_STQCX(t, a, b)	stringify_in_c(.long PPC_RAW_STQCX(t, a, b))
550 #define PPC_MADDHD(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDHD(t, a, b, c))
551 #define PPC_MADDHDU(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDHDU(t, a, b, c))
552 #define PPC_MADDLD(t, a, b, c)	stringify_in_c(.long PPC_RAW_MADDLD(t, a, b, c))
553 #define PPC_MSGSND(b)		stringify_in_c(.long PPC_RAW_MSGSND(b))
554 #define PPC_MSGSYNC		stringify_in_c(.long PPC_RAW_MSGSYNC)
555 #define PPC_MSGCLR(b)		stringify_in_c(.long PPC_RAW_MSGCLR(b))
556 #define PPC_MSGSNDP(b)		stringify_in_c(.long PPC_RAW_MSGSNDP(b))
557 #define PPC_MSGCLRP(b)		stringify_in_c(.long PPC_RAW_MSGCLRP(b))
558 #define PPC_PASTE(a, b)		stringify_in_c(.long PPC_RAW_PASTE(a, b))
559 #define PPC_POPCNTB(a, s)	stringify_in_c(.long PPC_RAW_POPCNTB(a, s))
560 #define PPC_POPCNTD(a, s)	stringify_in_c(.long PPC_RAW_POPCNTD(a, s))
561 #define PPC_POPCNTW(a, s)	stringify_in_c(.long PPC_RAW_POPCNTW(a, s))
562 #define PPC_RFCI		stringify_in_c(.long PPC_RAW_RFCI)
563 #define PPC_RFDI		stringify_in_c(.long PPC_RAW_RFDI)
564 #define PPC_RFMCI		stringify_in_c(.long PPC_RAW_RFMCI)
565 #define PPC_TLBILX(t, a, b)	stringify_in_c(.long PPC_RAW_TLBILX(t, a, b))
566 #define PPC_TLBILX_ALL(a, b)	PPC_TLBILX(0, a, b)
567 #define PPC_TLBILX_PID(a, b)	PPC_TLBILX(1, a, b)
568 #define PPC_TLBILX_VA(a, b)	PPC_TLBILX(3, a, b)
569 #define PPC_WAIT(w)		stringify_in_c(.long PPC_RAW_WAIT(w))
570 #define PPC_TLBIE(lp, a) 	stringify_in_c(.long PPC_RAW_TLBIE(lp, a))
571 #define	PPC_TLBIE_5(rb, rs, ric, prs, r) \
572 				stringify_in_c(.long PPC_RAW_TLBIE_5(rb, rs, ric, prs, r))
573 #define	PPC_TLBIEL(rb,rs,ric,prs,r) \
574 				stringify_in_c(.long PPC_RAW_TLBIEL(rb, rs, ric, prs, r))
575 #define PPC_TLBSRX_DOT(a, b)	stringify_in_c(.long PPC_RAW_TLBSRX_DOT(a, b))
576 #define PPC_TLBIVAX(a, b)	stringify_in_c(.long PPC_RAW_TLBIVAX(a, b))
577 
578 #define PPC_ERATWE(s, a, w)	stringify_in_c(.long PPC_RAW_ERATWE(s, a, w))
579 #define PPC_ERATRE(s, a, w)	stringify_in_c(.long PPC_RAW_ERATRE(a, a, w))
580 #define PPC_ERATILX(t, a, b)	stringify_in_c(.long PPC_RAW_ERATILX(t, a, b))
581 #define PPC_ERATIVAX(s, a, b)	stringify_in_c(.long PPC_RAW_ERATIVAX(s, a, b))
582 #define PPC_ERATSX(t, a, w)	stringify_in_c(.long PPC_RAW_ERATSX(t, a, w))
583 #define PPC_ERATSX_DOT(t, a, w)	stringify_in_c(.long PPC_RAW_ERATSX_DOT(t, a, w))
584 #define PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long PPC_RAW_SLBFEE_DOT(t, b))
585 #define __PPC_SLBFEE_DOT(t, b)	stringify_in_c(.long __PPC_RAW_SLBFEE_DOT(t, b))
586 #define PPC_ICBT(c, a, b)	stringify_in_c(.long PPC_RAW_ICBT(c, a, b))
587 /* PASemi instructions */
588 #define LBZCIX(t, a, b)		stringify_in_c(.long PPC_RAW_LBZCIX(t, a, b))
589 #define STBCIX(s, a, b)		stringify_in_c(.long PPC_RAW_STBCIX(s, a, b))
590 #define PPC_DCBFPS(a, b)	stringify_in_c(.long PPC_RAW_DCBFPS(a, b))
591 #define PPC_DCBSTPS(a, b)	stringify_in_c(.long PPC_RAW_DCBSTPS(a, b))
592 #define PPC_PHWSYNC		stringify_in_c(.long PPC_RAW_PHWSYNC)
593 #define PPC_PLWSYNC		stringify_in_c(.long PPC_RAW_PLWSYNC)
594 #define STXVD2X(s, a, b)	stringify_in_c(.long PPC_RAW_STXVD2X(s, a, b))
595 #define LXVD2X(s, a, b)		stringify_in_c(.long PPC_RAW_LXVD2X(s, a, b))
596 #define MFVRD(a, t)		stringify_in_c(.long PPC_RAW_MFVRD(a, t))
597 #define MTVRD(t, a)		stringify_in_c(.long PPC_RAW_MTVRD(t, a))
598 #define VPMSUMW(t, a, b)	stringify_in_c(.long PPC_RAW_VPMSUMW(t, a, b))
599 #define VPMSUMD(t, a, b)	stringify_in_c(.long PPC_RAW_VPMSUMD(t, a, b))
600 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_RAW_XXLOR(t, a, b))
601 #define XXSWAPD(t, a)		stringify_in_c(.long PPC_RAW_XXSWAPD(t, a))
602 #define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_RAW_XVCPSGNDP(t, a, b)))
603 
604 #define VPERMXOR(vrt, vra, vrb, vrc)				\
605 	stringify_in_c(.long (PPC_RAW_VPERMXOR(vrt, vra, vrb, vrc)))
606 
607 #define PPC_NAP			stringify_in_c(.long PPC_RAW_NAP)
608 #define PPC_SLEEP		stringify_in_c(.long PPC_RAW_SLEEP)
609 #define PPC_WINKLE		stringify_in_c(.long PPC_RAW_WINKLE)
610 
611 #define PPC_STOP		stringify_in_c(.long PPC_RAW_STOP)
612 
613 /* BHRB instructions */
614 #define PPC_CLRBHRB		stringify_in_c(.long PPC_RAW_CLRBHRB)
615 #define PPC_MFBHRBE(r, n)	stringify_in_c(.long PPC_RAW_MFBHRBE(r, n))
616 
617 /* Transactional memory instructions */
618 #define TRECHKPT		stringify_in_c(.long PPC_RAW_TRECHKPT)
619 #define TRECLAIM(r)		stringify_in_c(.long PPC_RAW_TRECLAIM(r))
620 #define TABORT(r)		stringify_in_c(.long PPC_RAW_TABORT(r))
621 
622 /* book3e thread control instructions */
623 #define MTTMR(tmr, r)		stringify_in_c(.long PPC_RAW_MTTMR(tmr, r))
624 #define MFTMR(tmr, r)		stringify_in_c(.long PPC_RAW_MFTMR(tmr, r))
625 
626 /* Coprocessor instructions */
627 #define PPC_ICSWX(s, a, b)	stringify_in_c(.long PPC_RAW_ICSWX(s, a, b))
628 #define PPC_ICSWEPX(s, a, b)	stringify_in_c(.long PPC_RAW_ICSWEPX(s, a, b))
629 
630 #define PPC_SLBIA(IH)	stringify_in_c(.long PPC_RAW_SLBIA(IH))
631 
632 /*
633  * These may only be used on ISA v3.0 or later (aka. CPU_FTR_ARCH_300, radix
634  * implies CPU_FTR_ARCH_300). USER/GUEST invalidates may only be used by radix
635  * mode (on HPT these would also invalidate various SLBEs which may not be
636  * desired).
637  */
638 #define PPC_ISA_3_0_INVALIDATE_ERAT	PPC_SLBIA(7)
639 #define PPC_RADIX_INVALIDATE_ERAT_USER	PPC_SLBIA(3)
640 #define PPC_RADIX_INVALIDATE_ERAT_GUEST	PPC_SLBIA(6)
641 
642 #define VCMPEQUD_RC(vrt, vra, vrb)	stringify_in_c(.long PPC_RAW_VCMPEQUD_RC(vrt, vra, vrb))
643 
644 #define VCMPEQUB_RC(vrt, vra, vrb)	stringify_in_c(.long PPC_RAW_VCMPEQUB_RC(vrt, vra, vrb))
645 
646 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
647