1 /* 2 * Copyright 2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 7 * 2 of the License, or (at your option) any later version. 8 * 9 * provides masks and opcode images for use by code generation, emulation 10 * and for instructions that older assemblers might not know about 11 */ 12 #ifndef _ASM_POWERPC_PPC_OPCODE_H 13 #define _ASM_POWERPC_PPC_OPCODE_H 14 15 #include <linux/stringify.h> 16 #include <asm/asm-compat.h> 17 18 #define __REG_R0 0 19 #define __REG_R1 1 20 #define __REG_R2 2 21 #define __REG_R3 3 22 #define __REG_R4 4 23 #define __REG_R5 5 24 #define __REG_R6 6 25 #define __REG_R7 7 26 #define __REG_R8 8 27 #define __REG_R9 9 28 #define __REG_R10 10 29 #define __REG_R11 11 30 #define __REG_R12 12 31 #define __REG_R13 13 32 #define __REG_R14 14 33 #define __REG_R15 15 34 #define __REG_R16 16 35 #define __REG_R17 17 36 #define __REG_R18 18 37 #define __REG_R19 19 38 #define __REG_R20 20 39 #define __REG_R21 21 40 #define __REG_R22 22 41 #define __REG_R23 23 42 #define __REG_R24 24 43 #define __REG_R25 25 44 #define __REG_R26 26 45 #define __REG_R27 27 46 #define __REG_R28 28 47 #define __REG_R29 29 48 #define __REG_R30 30 49 #define __REG_R31 31 50 51 #define __REGA0_0 0 52 #define __REGA0_R1 1 53 #define __REGA0_R2 2 54 #define __REGA0_R3 3 55 #define __REGA0_R4 4 56 #define __REGA0_R5 5 57 #define __REGA0_R6 6 58 #define __REGA0_R7 7 59 #define __REGA0_R8 8 60 #define __REGA0_R9 9 61 #define __REGA0_R10 10 62 #define __REGA0_R11 11 63 #define __REGA0_R12 12 64 #define __REGA0_R13 13 65 #define __REGA0_R14 14 66 #define __REGA0_R15 15 67 #define __REGA0_R16 16 68 #define __REGA0_R17 17 69 #define __REGA0_R18 18 70 #define __REGA0_R19 19 71 #define __REGA0_R20 20 72 #define __REGA0_R21 21 73 #define __REGA0_R22 22 74 #define __REGA0_R23 23 75 #define __REGA0_R24 24 76 #define __REGA0_R25 25 77 #define __REGA0_R26 26 78 #define __REGA0_R27 27 79 #define __REGA0_R28 28 80 #define __REGA0_R29 29 81 #define __REGA0_R30 30 82 #define __REGA0_R31 31 83 84 /* opcode and xopcode for instructions */ 85 #define OP_TRAP 3 86 #define OP_TRAP_64 2 87 88 #define OP_31_XOP_TRAP 4 89 #define OP_31_XOP_LDX 21 90 #define OP_31_XOP_LWZX 23 91 #define OP_31_XOP_LDUX 53 92 #define OP_31_XOP_DCBST 54 93 #define OP_31_XOP_LWZUX 55 94 #define OP_31_XOP_TRAP_64 68 95 #define OP_31_XOP_DCBF 86 96 #define OP_31_XOP_LBZX 87 97 #define OP_31_XOP_STDX 149 98 #define OP_31_XOP_STWX 151 99 #define OP_31_XOP_STDUX 181 100 #define OP_31_XOP_STWUX 183 101 #define OP_31_XOP_STBX 215 102 #define OP_31_XOP_LBZUX 119 103 #define OP_31_XOP_STBUX 247 104 #define OP_31_XOP_LHZX 279 105 #define OP_31_XOP_LHZUX 311 106 #define OP_31_XOP_MSGSNDP 142 107 #define OP_31_XOP_MSGCLRP 174 108 #define OP_31_XOP_MFSPR 339 109 #define OP_31_XOP_LWAX 341 110 #define OP_31_XOP_LHAX 343 111 #define OP_31_XOP_LWAUX 373 112 #define OP_31_XOP_LHAUX 375 113 #define OP_31_XOP_STHX 407 114 #define OP_31_XOP_STHUX 439 115 #define OP_31_XOP_MTSPR 467 116 #define OP_31_XOP_DCBI 470 117 #define OP_31_XOP_LDBRX 532 118 #define OP_31_XOP_LWBRX 534 119 #define OP_31_XOP_TLBSYNC 566 120 #define OP_31_XOP_STDBRX 660 121 #define OP_31_XOP_STWBRX 662 122 #define OP_31_XOP_STFSX 663 123 #define OP_31_XOP_STFSUX 695 124 #define OP_31_XOP_STFDX 727 125 #define OP_31_XOP_STFDUX 759 126 #define OP_31_XOP_LHBRX 790 127 #define OP_31_XOP_LFIWAX 855 128 #define OP_31_XOP_LFIWZX 887 129 #define OP_31_XOP_STHBRX 918 130 #define OP_31_XOP_STFIWX 983 131 132 /* VSX Scalar Load Instructions */ 133 #define OP_31_XOP_LXSDX 588 134 #define OP_31_XOP_LXSSPX 524 135 #define OP_31_XOP_LXSIWAX 76 136 #define OP_31_XOP_LXSIWZX 12 137 138 /* VSX Scalar Store Instructions */ 139 #define OP_31_XOP_STXSDX 716 140 #define OP_31_XOP_STXSSPX 652 141 #define OP_31_XOP_STXSIWX 140 142 143 /* VSX Vector Load Instructions */ 144 #define OP_31_XOP_LXVD2X 844 145 #define OP_31_XOP_LXVW4X 780 146 147 /* VSX Vector Load and Splat Instruction */ 148 #define OP_31_XOP_LXVDSX 332 149 150 /* VSX Vector Store Instructions */ 151 #define OP_31_XOP_STXVD2X 972 152 #define OP_31_XOP_STXVW4X 908 153 154 #define OP_31_XOP_LFSX 535 155 #define OP_31_XOP_LFSUX 567 156 #define OP_31_XOP_LFDX 599 157 #define OP_31_XOP_LFDUX 631 158 159 /* VMX Vector Load Instructions */ 160 #define OP_31_XOP_LVX 103 161 162 /* VMX Vector Store Instructions */ 163 #define OP_31_XOP_STVX 231 164 165 #define OP_LWZ 32 166 #define OP_STFS 52 167 #define OP_STFSU 53 168 #define OP_STFD 54 169 #define OP_STFDU 55 170 #define OP_LD 58 171 #define OP_LWZU 33 172 #define OP_LBZ 34 173 #define OP_LBZU 35 174 #define OP_STW 36 175 #define OP_STWU 37 176 #define OP_STD 62 177 #define OP_STB 38 178 #define OP_STBU 39 179 #define OP_LHZ 40 180 #define OP_LHZU 41 181 #define OP_LHA 42 182 #define OP_LHAU 43 183 #define OP_STH 44 184 #define OP_STHU 45 185 #define OP_LMW 46 186 #define OP_STMW 47 187 #define OP_LFS 48 188 #define OP_LFSU 49 189 #define OP_LFD 50 190 #define OP_LFDU 51 191 #define OP_STFS 52 192 #define OP_STFSU 53 193 #define OP_STFD 54 194 #define OP_STFDU 55 195 #define OP_LQ 56 196 197 /* sorted alphabetically */ 198 #define PPC_INST_BHRBE 0x7c00025c 199 #define PPC_INST_CLRBHRB 0x7c00035c 200 #define PPC_INST_COPY 0x7c20060c 201 #define PPC_INST_CP_ABORT 0x7c00068c 202 #define PPC_INST_DARN 0x7c0005e6 203 #define PPC_INST_DCBA 0x7c0005ec 204 #define PPC_INST_DCBA_MASK 0xfc0007fe 205 #define PPC_INST_DCBAL 0x7c2005ec 206 #define PPC_INST_DCBZL 0x7c2007ec 207 #define PPC_INST_ICBT 0x7c00002c 208 #define PPC_INST_ICSWX 0x7c00032d 209 #define PPC_INST_ICSWEPX 0x7c00076d 210 #define PPC_INST_ISEL 0x7c00001e 211 #define PPC_INST_ISEL_MASK 0xfc00003e 212 #define PPC_INST_LDARX 0x7c0000a8 213 #define PPC_INST_STDCX 0x7c0001ad 214 #define PPC_INST_LQARX 0x7c000228 215 #define PPC_INST_STQCX 0x7c00016d 216 #define PPC_INST_LSWI 0x7c0004aa 217 #define PPC_INST_LSWX 0x7c00042a 218 #define PPC_INST_LWARX 0x7c000028 219 #define PPC_INST_STWCX 0x7c00012d 220 #define PPC_INST_LWSYNC 0x7c2004ac 221 #define PPC_INST_SYNC 0x7c0004ac 222 #define PPC_INST_SYNC_MASK 0xfc0007fe 223 #define PPC_INST_ISYNC 0x4c00012c 224 #define PPC_INST_LXVD2X 0x7c000698 225 #define PPC_INST_MCRXR 0x7c000400 226 #define PPC_INST_MCRXR_MASK 0xfc0007fe 227 #define PPC_INST_MFSPR_PVR 0x7c1f42a6 228 #define PPC_INST_MFSPR_PVR_MASK 0xfc1ffffe 229 #define PPC_INST_MFTMR 0x7c0002dc 230 #define PPC_INST_MSGSND 0x7c00019c 231 #define PPC_INST_MSGCLR 0x7c0001dc 232 #define PPC_INST_MSGSYNC 0x7c0006ec 233 #define PPC_INST_MSGSNDP 0x7c00011c 234 #define PPC_INST_MSGCLRP 0x7c00015c 235 #define PPC_INST_MTTMR 0x7c0003dc 236 #define PPC_INST_NOP 0x60000000 237 #define PPC_INST_PASTE 0x7c20070d 238 #define PPC_INST_POPCNTB 0x7c0000f4 239 #define PPC_INST_POPCNTB_MASK 0xfc0007fe 240 #define PPC_INST_POPCNTD 0x7c0003f4 241 #define PPC_INST_POPCNTW 0x7c0002f4 242 #define PPC_INST_RFCI 0x4c000066 243 #define PPC_INST_RFDI 0x4c00004e 244 #define PPC_INST_RFMCI 0x4c00004c 245 #define PPC_INST_MFSPR 0x7c0002a6 246 #define PPC_INST_MFSPR_DSCR 0x7c1102a6 247 #define PPC_INST_MFSPR_DSCR_MASK 0xfc1ffffe 248 #define PPC_INST_MTSPR_DSCR 0x7c1103a6 249 #define PPC_INST_MTSPR_DSCR_MASK 0xfc1ffffe 250 #define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6 251 #define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1ffffe 252 #define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6 253 #define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1ffffe 254 #define PPC_INST_MFVSRD 0x7c000066 255 #define PPC_INST_MTVSRD 0x7c000166 256 #define PPC_INST_SLBFEE 0x7c0007a7 257 #define PPC_INST_SLBIA 0x7c0003e4 258 259 #define PPC_INST_STRING 0x7c00042a 260 #define PPC_INST_STRING_MASK 0xfc0007fe 261 #define PPC_INST_STRING_GEN_MASK 0xfc00067e 262 263 #define PPC_INST_STSWI 0x7c0005aa 264 #define PPC_INST_STSWX 0x7c00052a 265 #define PPC_INST_STXVD2X 0x7c000798 266 #define PPC_INST_TLBIE 0x7c000264 267 #define PPC_INST_TLBIEL 0x7c000224 268 #define PPC_INST_TLBILX 0x7c000024 269 #define PPC_INST_WAIT 0x7c00007c 270 #define PPC_INST_TLBIVAX 0x7c000624 271 #define PPC_INST_TLBSRX_DOT 0x7c0006a5 272 #define PPC_INST_VPMSUMW 0x10000488 273 #define PPC_INST_VPMSUMD 0x100004c8 274 #define PPC_INST_XXLOR 0xf0000490 275 #define PPC_INST_XXSWAPD 0xf0000250 276 #define PPC_INST_XVCPSGNDP 0xf0000780 277 #define PPC_INST_TRECHKPT 0x7c0007dd 278 #define PPC_INST_TRECLAIM 0x7c00075d 279 #define PPC_INST_TABORT 0x7c00071d 280 281 #define PPC_INST_NAP 0x4c000364 282 #define PPC_INST_SLEEP 0x4c0003a4 283 #define PPC_INST_WINKLE 0x4c0003e4 284 285 #define PPC_INST_STOP 0x4c0002e4 286 287 /* A2 specific instructions */ 288 #define PPC_INST_ERATWE 0x7c0001a6 289 #define PPC_INST_ERATRE 0x7c000166 290 #define PPC_INST_ERATILX 0x7c000066 291 #define PPC_INST_ERATIVAX 0x7c000666 292 #define PPC_INST_ERATSX 0x7c000126 293 #define PPC_INST_ERATSX_DOT 0x7c000127 294 295 /* Misc instructions for BPF compiler */ 296 #define PPC_INST_LBZ 0x88000000 297 #define PPC_INST_LD 0xe8000000 298 #define PPC_INST_LHZ 0xa0000000 299 #define PPC_INST_LWZ 0x80000000 300 #define PPC_INST_LHBRX 0x7c00062c 301 #define PPC_INST_LDBRX 0x7c000428 302 #define PPC_INST_STB 0x98000000 303 #define PPC_INST_STH 0xb0000000 304 #define PPC_INST_STD 0xf8000000 305 #define PPC_INST_STDU 0xf8000001 306 #define PPC_INST_STW 0x90000000 307 #define PPC_INST_STWU 0x94000000 308 #define PPC_INST_MFLR 0x7c0802a6 309 #define PPC_INST_MTLR 0x7c0803a6 310 #define PPC_INST_MTCTR 0x7c0903a6 311 #define PPC_INST_CMPWI 0x2c000000 312 #define PPC_INST_CMPDI 0x2c200000 313 #define PPC_INST_CMPW 0x7c000000 314 #define PPC_INST_CMPD 0x7c200000 315 #define PPC_INST_CMPLW 0x7c000040 316 #define PPC_INST_CMPLD 0x7c200040 317 #define PPC_INST_CMPLWI 0x28000000 318 #define PPC_INST_CMPLDI 0x28200000 319 #define PPC_INST_ADDI 0x38000000 320 #define PPC_INST_ADDIS 0x3c000000 321 #define PPC_INST_ADD 0x7c000214 322 #define PPC_INST_SUB 0x7c000050 323 #define PPC_INST_BLR 0x4e800020 324 #define PPC_INST_BLRL 0x4e800021 325 #define PPC_INST_BCTR 0x4e800420 326 #define PPC_INST_MULLD 0x7c0001d2 327 #define PPC_INST_MULLW 0x7c0001d6 328 #define PPC_INST_MULHWU 0x7c000016 329 #define PPC_INST_MULLI 0x1c000000 330 #define PPC_INST_DIVWU 0x7c000396 331 #define PPC_INST_DIVD 0x7c0003d2 332 #define PPC_INST_RLWINM 0x54000000 333 #define PPC_INST_RLWIMI 0x50000000 334 #define PPC_INST_RLDICL 0x78000000 335 #define PPC_INST_RLDICR 0x78000004 336 #define PPC_INST_SLW 0x7c000030 337 #define PPC_INST_SLD 0x7c000036 338 #define PPC_INST_SRW 0x7c000430 339 #define PPC_INST_SRD 0x7c000436 340 #define PPC_INST_SRAD 0x7c000634 341 #define PPC_INST_SRADI 0x7c000674 342 #define PPC_INST_AND 0x7c000038 343 #define PPC_INST_ANDDOT 0x7c000039 344 #define PPC_INST_OR 0x7c000378 345 #define PPC_INST_XOR 0x7c000278 346 #define PPC_INST_ANDI 0x70000000 347 #define PPC_INST_ORI 0x60000000 348 #define PPC_INST_ORIS 0x64000000 349 #define PPC_INST_XORI 0x68000000 350 #define PPC_INST_XORIS 0x6c000000 351 #define PPC_INST_NEG 0x7c0000d0 352 #define PPC_INST_EXTSW 0x7c0007b4 353 #define PPC_INST_BRANCH 0x48000000 354 #define PPC_INST_BRANCH_COND 0x40800000 355 #define PPC_INST_LBZCIX 0x7c0006aa 356 #define PPC_INST_STBCIX 0x7c0007aa 357 #define PPC_INST_LWZX 0x7c00002e 358 #define PPC_INST_LFSX 0x7c00042e 359 #define PPC_INST_STFSX 0x7c00052e 360 #define PPC_INST_LFDX 0x7c0004ae 361 #define PPC_INST_STFDX 0x7c0005ae 362 #define PPC_INST_LVX 0x7c0000ce 363 #define PPC_INST_STVX 0x7c0001ce 364 365 /* macros to insert fields into opcodes */ 366 #define ___PPC_RA(a) (((a) & 0x1f) << 16) 367 #define ___PPC_RB(b) (((b) & 0x1f) << 11) 368 #define ___PPC_RS(s) (((s) & 0x1f) << 21) 369 #define ___PPC_RT(t) ___PPC_RS(t) 370 #define ___PPC_R(r) (((r) & 0x1) << 16) 371 #define ___PPC_PRS(prs) (((prs) & 0x1) << 17) 372 #define ___PPC_RIC(ric) (((ric) & 0x3) << 18) 373 #define __PPC_RA(a) ___PPC_RA(__REG_##a) 374 #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a) 375 #define __PPC_RB(b) ___PPC_RB(__REG_##b) 376 #define __PPC_RS(s) ___PPC_RS(__REG_##s) 377 #define __PPC_RT(t) ___PPC_RT(__REG_##t) 378 #define __PPC_XA(a) ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3)) 379 #define __PPC_XB(b) ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4)) 380 #define __PPC_XS(s) ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5)) 381 #define __PPC_XT(s) __PPC_XS(s) 382 #define __PPC_T_TLB(t) (((t) & 0x3) << 21) 383 #define __PPC_WC(w) (((w) & 0x3) << 21) 384 #define __PPC_WS(w) (((w) & 0x1f) << 11) 385 #define __PPC_SH(s) __PPC_WS(s) 386 #define __PPC_SH64(s) (__PPC_SH(s) | (((s) & 0x20) >> 4)) 387 #define __PPC_MB(s) (((s) & 0x1f) << 6) 388 #define __PPC_ME(s) (((s) & 0x1f) << 1) 389 #define __PPC_MB64(s) (__PPC_MB(s) | ((s) & 0x20)) 390 #define __PPC_ME64(s) __PPC_MB64(s) 391 #define __PPC_BI(s) (((s) & 0x1f) << 16) 392 #define __PPC_CT(t) (((t) & 0x0f) << 21) 393 #define __PPC_SPR(r) ((((r) & 0x1f) << 16) | ((((r) >> 5) & 0x1f) << 11)) 394 395 /* 396 * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a 397 * larx with EH set as an illegal instruction. 398 */ 399 #ifdef CONFIG_PPC64 400 #define __PPC_EH(eh) (((eh) & 0x1) << 0) 401 #else 402 #define __PPC_EH(eh) 0 403 #endif 404 405 /* Deal with instructions that older assemblers aren't aware of */ 406 #define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT) 407 #define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \ 408 ___PPC_RA(a) | ___PPC_RB(b)) 409 #define PPC_DARN(t, l) stringify_in_c(.long PPC_INST_DARN | \ 410 ___PPC_RT(t) | \ 411 (((l) & 0x3) << 16)) 412 #define PPC_DCBAL(a, b) stringify_in_c(.long PPC_INST_DCBAL | \ 413 __PPC_RA(a) | __PPC_RB(b)) 414 #define PPC_DCBZL(a, b) stringify_in_c(.long PPC_INST_DCBZL | \ 415 __PPC_RA(a) | __PPC_RB(b)) 416 #define PPC_LQARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LQARX | \ 417 ___PPC_RT(t) | ___PPC_RA(a) | \ 418 ___PPC_RB(b) | __PPC_EH(eh)) 419 #define PPC_LDARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LDARX | \ 420 ___PPC_RT(t) | ___PPC_RA(a) | \ 421 ___PPC_RB(b) | __PPC_EH(eh)) 422 #define PPC_LWARX(t, a, b, eh) stringify_in_c(.long PPC_INST_LWARX | \ 423 ___PPC_RT(t) | ___PPC_RA(a) | \ 424 ___PPC_RB(b) | __PPC_EH(eh)) 425 #define PPC_STQCX(t, a, b) stringify_in_c(.long PPC_INST_STQCX | \ 426 ___PPC_RT(t) | ___PPC_RA(a) | \ 427 ___PPC_RB(b)) 428 #define PPC_MSGSND(b) stringify_in_c(.long PPC_INST_MSGSND | \ 429 ___PPC_RB(b)) 430 #define PPC_MSGSYNC stringify_in_c(.long PPC_INST_MSGSYNC) 431 #define PPC_MSGCLR(b) stringify_in_c(.long PPC_INST_MSGCLR | \ 432 ___PPC_RB(b)) 433 #define PPC_MSGSNDP(b) stringify_in_c(.long PPC_INST_MSGSNDP | \ 434 ___PPC_RB(b)) 435 #define PPC_MSGCLRP(b) stringify_in_c(.long PPC_INST_MSGCLRP | \ 436 ___PPC_RB(b)) 437 #define PPC_PASTE(a, b) stringify_in_c(.long PPC_INST_PASTE | \ 438 ___PPC_RA(a) | ___PPC_RB(b)) 439 #define PPC_POPCNTB(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \ 440 __PPC_RA(a) | __PPC_RS(s)) 441 #define PPC_POPCNTD(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \ 442 __PPC_RA(a) | __PPC_RS(s)) 443 #define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \ 444 __PPC_RA(a) | __PPC_RS(s)) 445 #define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI) 446 #define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI) 447 #define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI) 448 #define PPC_TLBILX(t, a, b) stringify_in_c(.long PPC_INST_TLBILX | \ 449 __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b)) 450 #define PPC_TLBILX_ALL(a, b) PPC_TLBILX(0, a, b) 451 #define PPC_TLBILX_PID(a, b) PPC_TLBILX(1, a, b) 452 #define PPC_TLBILX_VA(a, b) PPC_TLBILX(3, a, b) 453 #define PPC_WAIT(w) stringify_in_c(.long PPC_INST_WAIT | \ 454 __PPC_WC(w)) 455 #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ 456 ___PPC_RB(a) | ___PPC_RS(lp)) 457 #define PPC_TLBIE_5(rb,rs,ric,prs,r) \ 458 stringify_in_c(.long PPC_INST_TLBIE | \ 459 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 460 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 461 ___PPC_R(r)) 462 #define PPC_TLBIEL(rb,rs,ric,prs,r) \ 463 stringify_in_c(.long PPC_INST_TLBIEL | \ 464 ___PPC_RB(rb) | ___PPC_RS(rs) | \ 465 ___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 466 ___PPC_R(r)) 467 #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ 468 __PPC_RA0(a) | __PPC_RB(b)) 469 #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ 470 __PPC_RA0(a) | __PPC_RB(b)) 471 472 #define PPC_ERATWE(s, a, w) stringify_in_c(.long PPC_INST_ERATWE | \ 473 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 474 #define PPC_ERATRE(s, a, w) stringify_in_c(.long PPC_INST_ERATRE | \ 475 __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w)) 476 #define PPC_ERATILX(t, a, b) stringify_in_c(.long PPC_INST_ERATILX | \ 477 __PPC_T_TLB(t) | __PPC_RA0(a) | \ 478 __PPC_RB(b)) 479 #define PPC_ERATIVAX(s, a, b) stringify_in_c(.long PPC_INST_ERATIVAX | \ 480 __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b)) 481 #define PPC_ERATSX(t, a, w) stringify_in_c(.long PPC_INST_ERATSX | \ 482 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 483 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \ 484 __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b)) 485 #define PPC_SLBFEE_DOT(t, b) stringify_in_c(.long PPC_INST_SLBFEE | \ 486 __PPC_RT(t) | __PPC_RB(b)) 487 #define PPC_ICBT(c,a,b) stringify_in_c(.long PPC_INST_ICBT | \ 488 __PPC_CT(c) | __PPC_RA0(a) | __PPC_RB(b)) 489 /* PASemi instructions */ 490 #define LBZCIX(t,a,b) stringify_in_c(.long PPC_INST_LBZCIX | \ 491 __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b)) 492 #define STBCIX(s,a,b) stringify_in_c(.long PPC_INST_STBCIX | \ 493 __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b)) 494 495 /* 496 * Define what the VSX XX1 form instructions will look like, then add 497 * the 128 bit load store instructions based on that. 498 */ 499 #define VSX_XX1(s, a, b) (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b)) 500 #define VSX_XX3(t, a, b) (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b)) 501 #define STXVD2X(s, a, b) stringify_in_c(.long PPC_INST_STXVD2X | \ 502 VSX_XX1((s), a, b)) 503 #define LXVD2X(s, a, b) stringify_in_c(.long PPC_INST_LXVD2X | \ 504 VSX_XX1((s), a, b)) 505 #define MFVRD(a, t) stringify_in_c(.long PPC_INST_MFVSRD | \ 506 VSX_XX1((t)+32, a, R0)) 507 #define MTVRD(t, a) stringify_in_c(.long PPC_INST_MTVSRD | \ 508 VSX_XX1((t)+32, a, R0)) 509 #define VPMSUMW(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMW | \ 510 VSX_XX3((t), a, b)) 511 #define VPMSUMD(t, a, b) stringify_in_c(.long PPC_INST_VPMSUMD | \ 512 VSX_XX3((t), a, b)) 513 #define XXLOR(t, a, b) stringify_in_c(.long PPC_INST_XXLOR | \ 514 VSX_XX3((t), a, b)) 515 #define XXSWAPD(t, a) stringify_in_c(.long PPC_INST_XXSWAPD | \ 516 VSX_XX3((t), a, a)) 517 #define XVCPSGNDP(t, a, b) stringify_in_c(.long (PPC_INST_XVCPSGNDP | \ 518 VSX_XX3((t), (a), (b)))) 519 520 #define PPC_NAP stringify_in_c(.long PPC_INST_NAP) 521 #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP) 522 #define PPC_WINKLE stringify_in_c(.long PPC_INST_WINKLE) 523 524 #define PPC_STOP stringify_in_c(.long PPC_INST_STOP) 525 526 /* BHRB instructions */ 527 #define PPC_CLRBHRB stringify_in_c(.long PPC_INST_CLRBHRB) 528 #define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \ 529 __PPC_RT(r) | \ 530 (((n) & 0x3ff) << 11)) 531 532 /* Transactional memory instructions */ 533 #define TRECHKPT stringify_in_c(.long PPC_INST_TRECHKPT) 534 #define TRECLAIM(r) stringify_in_c(.long PPC_INST_TRECLAIM \ 535 | __PPC_RA(r)) 536 #define TABORT(r) stringify_in_c(.long PPC_INST_TABORT \ 537 | __PPC_RA(r)) 538 539 /* book3e thread control instructions */ 540 #define TMRN(x) ((((x) & 0x1f) << 16) | (((x) & 0x3e0) << 6)) 541 #define MTTMR(tmr, r) stringify_in_c(.long PPC_INST_MTTMR | \ 542 TMRN(tmr) | ___PPC_RS(r)) 543 #define MFTMR(tmr, r) stringify_in_c(.long PPC_INST_MFTMR | \ 544 TMRN(tmr) | ___PPC_RT(r)) 545 546 /* Coprocessor instructions */ 547 #define PPC_ICSWX(s, a, b) stringify_in_c(.long PPC_INST_ICSWX | \ 548 ___PPC_RS(s) | \ 549 ___PPC_RA(a) | \ 550 ___PPC_RB(b)) 551 #define PPC_ICSWEPX(s, a, b) stringify_in_c(.long PPC_INST_ICSWEPX | \ 552 ___PPC_RS(s) | \ 553 ___PPC_RA(a) | \ 554 ___PPC_RB(b)) 555 556 #define PPC_SLBIA(IH) stringify_in_c(.long PPC_INST_SLBIA | \ 557 ((IH & 0x7) << 21)) 558 #define PPC_INVALIDATE_ERAT PPC_SLBIA(7) 559 560 #endif /* _ASM_POWERPC_PPC_OPCODE_H */ 561