1 /* 2 * Performance event support - PowerPC classic/server specific definitions. 3 * 4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/types.h> 13 #include <asm/hw_irq.h> 14 #include <linux/device.h> 15 #include <uapi/asm/perf_event.h> 16 17 /* Update perf_event_print_debug() if this changes */ 18 #define MAX_HWEVENTS 8 19 #define MAX_EVENT_ALTERNATIVES 8 20 #define MAX_LIMITED_HWCOUNTERS 2 21 22 /* 23 * This struct provides the constants and functions needed to 24 * describe the PMU on a particular POWER-family CPU. 25 */ 26 struct power_pmu { 27 const char *name; 28 int n_counter; 29 int max_alternatives; 30 unsigned long add_fields; 31 unsigned long test_adder; 32 int (*compute_mmcr)(u64 events[], int n_ev, 33 unsigned int hwc[], unsigned long mmcr[]); 34 int (*get_constraint)(u64 event_id, unsigned long *mskp, 35 unsigned long *valp); 36 int (*get_alternatives)(u64 event_id, unsigned int flags, 37 u64 alt[]); 38 u64 (*bhrb_filter_map)(u64 branch_sample_type); 39 void (*config_bhrb)(u64 pmu_bhrb_filter); 40 void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]); 41 int (*limited_pmc_event)(u64 event_id); 42 u32 flags; 43 const struct attribute_group **attr_groups; 44 int n_generic; 45 int *generic_events; 46 int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] 47 [PERF_COUNT_HW_CACHE_OP_MAX] 48 [PERF_COUNT_HW_CACHE_RESULT_MAX]; 49 50 /* BHRB entries in the PMU */ 51 int bhrb_nr; 52 }; 53 54 /* 55 * Values for power_pmu.flags 56 */ 57 #define PPMU_LIMITED_PMC5_6 0x00000001 /* PMC5/6 have limited function */ 58 #define PPMU_ALT_SIPR 0x00000002 /* uses alternate posn for SIPR/HV */ 59 #define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */ 60 #define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */ 61 #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */ 62 #define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */ 63 #define PPMU_HAS_SIER 0x00000040 /* Has SIER */ 64 #define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */ 65 #define PPMU_EBB 0x00000100 /* supports event based branch */ 66 67 /* 68 * Values for flags to get_alternatives() 69 */ 70 #define PPMU_LIMITED_PMC_OK 1 /* can put this on a limited PMC */ 71 #define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */ 72 #define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */ 73 74 extern int register_power_pmu(struct power_pmu *); 75 76 struct pt_regs; 77 extern unsigned long perf_misc_flags(struct pt_regs *regs); 78 extern unsigned long perf_instruction_pointer(struct pt_regs *regs); 79 extern unsigned long int read_bhrb(int n); 80 81 /* 82 * Only override the default definitions in include/linux/perf_event.h 83 * if we have hardware PMU support. 84 */ 85 #ifdef CONFIG_PPC_PERF_CTRS 86 #define perf_misc_flags(regs) perf_misc_flags(regs) 87 #endif 88 89 /* 90 * The power_pmu.get_constraint function returns a 32/64-bit value and 91 * a 32/64-bit mask that express the constraints between this event_id and 92 * other events. 93 * 94 * The value and mask are divided up into (non-overlapping) bitfields 95 * of three different types: 96 * 97 * Select field: this expresses the constraint that some set of bits 98 * in MMCR* needs to be set to a specific value for this event_id. For a 99 * select field, the mask contains 1s in every bit of the field, and 100 * the value contains a unique value for each possible setting of the 101 * MMCR* bits. The constraint checking code will ensure that two events 102 * that set the same field in their masks have the same value in their 103 * value dwords. 104 * 105 * Add field: this expresses the constraint that there can be at most 106 * N events in a particular class. A field of k bits can be used for 107 * N <= 2^(k-1) - 1. The mask has the most significant bit of the field 108 * set (and the other bits 0), and the value has only the least significant 109 * bit of the field set. In addition, the 'add_fields' and 'test_adder' 110 * in the struct power_pmu for this processor come into play. The 111 * add_fields value contains 1 in the LSB of the field, and the 112 * test_adder contains 2^(k-1) - 1 - N in the field. 113 * 114 * NAND field: this expresses the constraint that you may not have events 115 * in all of a set of classes. (For example, on PPC970, you can't select 116 * events from the FPU, ISU and IDU simultaneously, although any two are 117 * possible.) For N classes, the field is N+1 bits wide, and each class 118 * is assigned one bit from the least-significant N bits. The mask has 119 * only the most-significant bit set, and the value has only the bit 120 * for the event_id's class set. The test_adder has the least significant 121 * bit set in the field. 122 * 123 * If an event_id is not subject to the constraint expressed by a particular 124 * field, then it will have 0 in both the mask and value for that field. 125 */ 126 127 extern ssize_t power_events_sysfs_show(struct device *dev, 128 struct device_attribute *attr, char *page); 129 130 /* 131 * EVENT_VAR() is same as PMU_EVENT_VAR with a suffix. 132 * 133 * Having a suffix allows us to have aliases in sysfs - eg: the generic 134 * event 'cpu-cycles' can have two entries in sysfs: 'cpu-cycles' and 135 * 'PM_CYC' where the latter is the name by which the event is known in 136 * POWER CPU specification. 137 */ 138 #define EVENT_VAR(_id, _suffix) event_attr_##_id##_suffix 139 #define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr 140 141 #define EVENT_ATTR(_name, _id, _suffix) \ 142 PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_##_id, \ 143 power_events_sysfs_show) 144 145 #define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g) 146 #define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g) 147 148 #define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p) 149 #define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p) 150