1 #ifndef __ASM_POWERPC_PCI_H 2 #define __ASM_POWERPC_PCI_H 3 #ifdef __KERNEL__ 4 5 /* 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/types.h> 13 #include <linux/slab.h> 14 #include <linux/string.h> 15 #include <linux/dma-mapping.h> 16 17 #include <asm/machdep.h> 18 #include <asm/scatterlist.h> 19 #include <asm/io.h> 20 #include <asm/prom.h> 21 #include <asm/pci-bridge.h> 22 23 #include <asm-generic/pci-dma-compat.h> 24 25 #define PCIBIOS_MIN_IO 0x1000 26 #define PCIBIOS_MIN_MEM 0x10000000 27 28 struct pci_dev; 29 30 /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ 31 #define IOBASE_BRIDGE_NUMBER 0 32 #define IOBASE_MEMORY 1 33 #define IOBASE_IO 2 34 #define IOBASE_ISA_IO 3 35 #define IOBASE_ISA_MEM 4 36 37 /* 38 * Set this to 1 if you want the kernel to re-assign all PCI 39 * bus numbers (don't do that on ppc64 yet !) 40 */ 41 #define pcibios_assign_all_busses() \ 42 (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS)) 43 #define pcibios_scan_all_fns(a, b) 0 44 45 static inline void pcibios_set_master(struct pci_dev *dev) 46 { 47 /* No special bus mastering setup handling */ 48 } 49 50 static inline void pcibios_penalize_isa_irq(int irq, int active) 51 { 52 /* We don't do dynamic PCI IRQ allocation */ 53 } 54 55 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 56 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 57 { 58 if (ppc_md.pci_get_legacy_ide_irq) 59 return ppc_md.pci_get_legacy_ide_irq(dev, channel); 60 return channel ? 15 : 14; 61 } 62 63 #ifdef CONFIG_PCI 64 extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); 65 extern struct dma_mapping_ops *get_pci_dma_ops(void); 66 #else /* CONFIG_PCI */ 67 #define set_pci_dma_ops(d) 68 #define get_pci_dma_ops() NULL 69 #endif 70 71 #ifdef CONFIG_PPC64 72 73 /* 74 * We want to avoid touching the cacheline size or MWI bit. 75 * pSeries firmware sets the cacheline size (which is not the cpu cacheline 76 * size in all cases) and hardware treats MWI the same as memory write. 77 */ 78 #define PCI_DISABLE_MWI 79 80 #ifdef CONFIG_PCI 81 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 82 enum pci_dma_burst_strategy *strat, 83 unsigned long *strategy_parameter) 84 { 85 unsigned long cacheline_size; 86 u8 byte; 87 88 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 89 if (byte == 0) 90 cacheline_size = 1024; 91 else 92 cacheline_size = (int) byte * 4; 93 94 *strat = PCI_DMA_BURST_MULTIPLE; 95 *strategy_parameter = cacheline_size; 96 } 97 #endif 98 99 #else /* 32-bit */ 100 101 #ifdef CONFIG_PCI 102 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 103 enum pci_dma_burst_strategy *strat, 104 unsigned long *strategy_parameter) 105 { 106 *strat = PCI_DMA_BURST_INFINITY; 107 *strategy_parameter = ~0UL; 108 } 109 #endif 110 #endif /* CONFIG_PPC64 */ 111 112 extern int pci_domain_nr(struct pci_bus *bus); 113 114 /* Decide whether to display the domain number in /proc */ 115 extern int pci_proc_domain(struct pci_bus *bus); 116 117 /* MSI arch hooks */ 118 #define arch_setup_msi_irqs arch_setup_msi_irqs 119 #define arch_teardown_msi_irqs arch_teardown_msi_irqs 120 #define arch_msi_check_device arch_msi_check_device 121 122 struct vm_area_struct; 123 /* Map a range of PCI memory or I/O space for a device into user space */ 124 int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 125 enum pci_mmap_state mmap_state, int write_combine); 126 127 /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ 128 #define HAVE_PCI_MMAP 1 129 130 extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, 131 size_t count); 132 extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, 133 size_t count); 134 extern int pci_mmap_legacy_page_range(struct pci_bus *bus, 135 struct vm_area_struct *vma, 136 enum pci_mmap_state mmap_state); 137 138 #define HAVE_PCI_LEGACY 1 139 140 #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE) 141 /* 142 * For 64-bit kernels, pci_unmap_{single,page} is not a nop. 143 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and 144 * so on are not nops. 145 * and thus... 146 */ 147 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 148 dma_addr_t ADDR_NAME; 149 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 150 __u32 LEN_NAME; 151 #define pci_unmap_addr(PTR, ADDR_NAME) \ 152 ((PTR)->ADDR_NAME) 153 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 154 (((PTR)->ADDR_NAME) = (VAL)) 155 #define pci_unmap_len(PTR, LEN_NAME) \ 156 ((PTR)->LEN_NAME) 157 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 158 (((PTR)->LEN_NAME) = (VAL)) 159 160 #else /* 32-bit && coherent */ 161 162 /* pci_unmap_{page,single} is a nop so... */ 163 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) 164 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) 165 #define pci_unmap_addr(PTR, ADDR_NAME) (0) 166 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) 167 #define pci_unmap_len(PTR, LEN_NAME) (0) 168 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 169 170 #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */ 171 172 #ifdef CONFIG_PPC64 173 174 /* The PCI address space does not equal the physical memory address 175 * space (we have an IOMMU). The IDE and SCSI device layers use 176 * this boolean for bounce buffer decisions. 177 */ 178 #define PCI_DMA_BUS_IS_PHYS (0) 179 180 #else /* 32-bit */ 181 182 /* The PCI address space does equal the physical memory 183 * address space (no IOMMU). The IDE and SCSI device layers use 184 * this boolean for bounce buffer decisions. 185 */ 186 #define PCI_DMA_BUS_IS_PHYS (1) 187 188 #endif /* CONFIG_PPC64 */ 189 190 extern void pcibios_resource_to_bus(struct pci_dev *dev, 191 struct pci_bus_region *region, 192 struct resource *res); 193 194 extern void pcibios_bus_to_resource(struct pci_dev *dev, 195 struct resource *res, 196 struct pci_bus_region *region); 197 198 static inline struct resource *pcibios_select_root(struct pci_dev *pdev, 199 struct resource *res) 200 { 201 struct resource *root = NULL; 202 203 if (res->flags & IORESOURCE_IO) 204 root = &ioport_resource; 205 if (res->flags & IORESOURCE_MEM) 206 root = &iomem_resource; 207 208 return root; 209 } 210 211 extern void pcibios_claim_one_bus(struct pci_bus *b); 212 213 extern void pcibios_finish_adding_to_bus(struct pci_bus *bus); 214 215 extern void pcibios_resource_survey(void); 216 217 extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 218 extern int remove_phb_dynamic(struct pci_controller *phb); 219 220 extern struct pci_dev *of_create_pci_dev(struct device_node *node, 221 struct pci_bus *bus, int devfn); 222 223 extern void of_scan_pci_bridge(struct device_node *node, 224 struct pci_dev *dev); 225 226 extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 227 extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); 228 229 extern int pci_read_irq_line(struct pci_dev *dev); 230 231 struct file; 232 extern pgprot_t pci_phys_mem_access_prot(struct file *file, 233 unsigned long pfn, 234 unsigned long size, 235 pgprot_t prot); 236 237 #define HAVE_ARCH_PCI_RESOURCE_TO_USER 238 extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 239 const struct resource *rsrc, 240 resource_size_t *start, resource_size_t *end); 241 242 extern void pcibios_setup_bus_devices(struct pci_bus *bus); 243 extern void pcibios_setup_bus_self(struct pci_bus *bus); 244 245 #endif /* __KERNEL__ */ 246 #endif /* __ASM_POWERPC_PCI_H */ 247