1b8b572e1SStephen Rothwell #ifndef __ASM_POWERPC_PCI_H 2b8b572e1SStephen Rothwell #define __ASM_POWERPC_PCI_H 3b8b572e1SStephen Rothwell #ifdef __KERNEL__ 4b8b572e1SStephen Rothwell 5b8b572e1SStephen Rothwell /* 6b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or 7b8b572e1SStephen Rothwell * modify it under the terms of the GNU General Public License 8b8b572e1SStephen Rothwell * as published by the Free Software Foundation; either version 9b8b572e1SStephen Rothwell * 2 of the License, or (at your option) any later version. 10b8b572e1SStephen Rothwell */ 11b8b572e1SStephen Rothwell 12b8b572e1SStephen Rothwell #include <linux/types.h> 13b8b572e1SStephen Rothwell #include <linux/slab.h> 14b8b572e1SStephen Rothwell #include <linux/string.h> 15b8b572e1SStephen Rothwell #include <linux/dma-mapping.h> 16b8b572e1SStephen Rothwell 17b8b572e1SStephen Rothwell #include <asm/machdep.h> 18b8b572e1SStephen Rothwell #include <asm/scatterlist.h> 19b8b572e1SStephen Rothwell #include <asm/io.h> 20b8b572e1SStephen Rothwell #include <asm/prom.h> 21b8b572e1SStephen Rothwell #include <asm/pci-bridge.h> 22b8b572e1SStephen Rothwell 23b8b572e1SStephen Rothwell #include <asm-generic/pci-dma-compat.h> 24b8b572e1SStephen Rothwell 25b8b572e1SStephen Rothwell #define PCIBIOS_MIN_IO 0x1000 26b8b572e1SStephen Rothwell #define PCIBIOS_MIN_MEM 0x10000000 27b8b572e1SStephen Rothwell 28b8b572e1SStephen Rothwell struct pci_dev; 29b8b572e1SStephen Rothwell 30b8b572e1SStephen Rothwell /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ 31b8b572e1SStephen Rothwell #define IOBASE_BRIDGE_NUMBER 0 32b8b572e1SStephen Rothwell #define IOBASE_MEMORY 1 33b8b572e1SStephen Rothwell #define IOBASE_IO 2 34b8b572e1SStephen Rothwell #define IOBASE_ISA_IO 3 35b8b572e1SStephen Rothwell #define IOBASE_ISA_MEM 4 36b8b572e1SStephen Rothwell 37b8b572e1SStephen Rothwell /* 38b8b572e1SStephen Rothwell * Set this to 1 if you want the kernel to re-assign all PCI 39b8b572e1SStephen Rothwell * bus numbers (don't do that on ppc64 yet !) 40b8b572e1SStephen Rothwell */ 41b8b572e1SStephen Rothwell #define pcibios_assign_all_busses() (ppc_pci_flags & \ 42b8b572e1SStephen Rothwell PPC_PCI_REASSIGN_ALL_BUS) 43b8b572e1SStephen Rothwell #define pcibios_scan_all_fns(a, b) 0 44b8b572e1SStephen Rothwell 45b8b572e1SStephen Rothwell static inline void pcibios_set_master(struct pci_dev *dev) 46b8b572e1SStephen Rothwell { 47b8b572e1SStephen Rothwell /* No special bus mastering setup handling */ 48b8b572e1SStephen Rothwell } 49b8b572e1SStephen Rothwell 50b8b572e1SStephen Rothwell static inline void pcibios_penalize_isa_irq(int irq, int active) 51b8b572e1SStephen Rothwell { 52b8b572e1SStephen Rothwell /* We don't do dynamic PCI IRQ allocation */ 53b8b572e1SStephen Rothwell } 54b8b572e1SStephen Rothwell 55b8b572e1SStephen Rothwell #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ 56b8b572e1SStephen Rothwell static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 57b8b572e1SStephen Rothwell { 58b8b572e1SStephen Rothwell if (ppc_md.pci_get_legacy_ide_irq) 59b8b572e1SStephen Rothwell return ppc_md.pci_get_legacy_ide_irq(dev, channel); 60b8b572e1SStephen Rothwell return channel ? 15 : 14; 61b8b572e1SStephen Rothwell } 62b8b572e1SStephen Rothwell 634fc665b8SBecky Bruce #ifdef CONFIG_PCI 644fc665b8SBecky Bruce extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops); 654fc665b8SBecky Bruce extern struct dma_mapping_ops *get_pci_dma_ops(void); 664fc665b8SBecky Bruce #else /* CONFIG_PCI */ 674fc665b8SBecky Bruce #define set_pci_dma_ops(d) 684fc665b8SBecky Bruce #define get_pci_dma_ops() NULL 694fc665b8SBecky Bruce #endif 704fc665b8SBecky Bruce 71b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 72b8b572e1SStephen Rothwell 73b8b572e1SStephen Rothwell /* 74b8b572e1SStephen Rothwell * We want to avoid touching the cacheline size or MWI bit. 75b8b572e1SStephen Rothwell * pSeries firmware sets the cacheline size (which is not the cpu cacheline 76b8b572e1SStephen Rothwell * size in all cases) and hardware treats MWI the same as memory write. 77b8b572e1SStephen Rothwell */ 78b8b572e1SStephen Rothwell #define PCI_DISABLE_MWI 79b8b572e1SStephen Rothwell 80b8b572e1SStephen Rothwell #ifdef CONFIG_PCI 81b8b572e1SStephen Rothwell static inline void pci_dma_burst_advice(struct pci_dev *pdev, 82b8b572e1SStephen Rothwell enum pci_dma_burst_strategy *strat, 83b8b572e1SStephen Rothwell unsigned long *strategy_parameter) 84b8b572e1SStephen Rothwell { 85b8b572e1SStephen Rothwell unsigned long cacheline_size; 86b8b572e1SStephen Rothwell u8 byte; 87b8b572e1SStephen Rothwell 88b8b572e1SStephen Rothwell pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 89b8b572e1SStephen Rothwell if (byte == 0) 90b8b572e1SStephen Rothwell cacheline_size = 1024; 91b8b572e1SStephen Rothwell else 92b8b572e1SStephen Rothwell cacheline_size = (int) byte * 4; 93b8b572e1SStephen Rothwell 94b8b572e1SStephen Rothwell *strat = PCI_DMA_BURST_MULTIPLE; 95b8b572e1SStephen Rothwell *strategy_parameter = cacheline_size; 96b8b572e1SStephen Rothwell } 97b8b572e1SStephen Rothwell #endif 98b8b572e1SStephen Rothwell 99b8b572e1SStephen Rothwell #else /* 32-bit */ 100b8b572e1SStephen Rothwell 101b8b572e1SStephen Rothwell #ifdef CONFIG_PCI 102b8b572e1SStephen Rothwell static inline void pci_dma_burst_advice(struct pci_dev *pdev, 103b8b572e1SStephen Rothwell enum pci_dma_burst_strategy *strat, 104b8b572e1SStephen Rothwell unsigned long *strategy_parameter) 105b8b572e1SStephen Rothwell { 106b8b572e1SStephen Rothwell *strat = PCI_DMA_BURST_INFINITY; 107b8b572e1SStephen Rothwell *strategy_parameter = ~0UL; 108b8b572e1SStephen Rothwell } 109b8b572e1SStephen Rothwell #endif 110b8b572e1SStephen Rothwell #endif /* CONFIG_PPC64 */ 111b8b572e1SStephen Rothwell 112b8b572e1SStephen Rothwell extern int pci_domain_nr(struct pci_bus *bus); 113b8b572e1SStephen Rothwell 114b8b572e1SStephen Rothwell /* Decide whether to display the domain number in /proc */ 115b8b572e1SStephen Rothwell extern int pci_proc_domain(struct pci_bus *bus); 116b8b572e1SStephen Rothwell 117b8b572e1SStephen Rothwell 118b8b572e1SStephen Rothwell struct vm_area_struct; 119b8b572e1SStephen Rothwell /* Map a range of PCI memory or I/O space for a device into user space */ 120b8b572e1SStephen Rothwell int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma, 121b8b572e1SStephen Rothwell enum pci_mmap_state mmap_state, int write_combine); 122b8b572e1SStephen Rothwell 123b8b572e1SStephen Rothwell /* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */ 124b8b572e1SStephen Rothwell #define HAVE_PCI_MMAP 1 125b8b572e1SStephen Rothwell 126e9f82cb7SBenjamin Herrenschmidt extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, 127e9f82cb7SBenjamin Herrenschmidt size_t count); 128e9f82cb7SBenjamin Herrenschmidt extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, 129e9f82cb7SBenjamin Herrenschmidt size_t count); 130e9f82cb7SBenjamin Herrenschmidt extern int pci_mmap_legacy_page_range(struct pci_bus *bus, 131e9f82cb7SBenjamin Herrenschmidt struct vm_area_struct *vma, 132e9f82cb7SBenjamin Herrenschmidt enum pci_mmap_state mmap_state); 133e9f82cb7SBenjamin Herrenschmidt 134e9f82cb7SBenjamin Herrenschmidt #define HAVE_PCI_LEGACY 1 135e9f82cb7SBenjamin Herrenschmidt 136b8b572e1SStephen Rothwell #if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE) 137b8b572e1SStephen Rothwell /* 138b8b572e1SStephen Rothwell * For 64-bit kernels, pci_unmap_{single,page} is not a nop. 139b8b572e1SStephen Rothwell * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and 140b8b572e1SStephen Rothwell * so on are not nops. 141b8b572e1SStephen Rothwell * and thus... 142b8b572e1SStephen Rothwell */ 143b8b572e1SStephen Rothwell #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 144b8b572e1SStephen Rothwell dma_addr_t ADDR_NAME; 145b8b572e1SStephen Rothwell #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 146b8b572e1SStephen Rothwell __u32 LEN_NAME; 147b8b572e1SStephen Rothwell #define pci_unmap_addr(PTR, ADDR_NAME) \ 148b8b572e1SStephen Rothwell ((PTR)->ADDR_NAME) 149b8b572e1SStephen Rothwell #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 150b8b572e1SStephen Rothwell (((PTR)->ADDR_NAME) = (VAL)) 151b8b572e1SStephen Rothwell #define pci_unmap_len(PTR, LEN_NAME) \ 152b8b572e1SStephen Rothwell ((PTR)->LEN_NAME) 153b8b572e1SStephen Rothwell #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 154b8b572e1SStephen Rothwell (((PTR)->LEN_NAME) = (VAL)) 155b8b572e1SStephen Rothwell 156b8b572e1SStephen Rothwell #else /* 32-bit && coherent */ 157b8b572e1SStephen Rothwell 158b8b572e1SStephen Rothwell /* pci_unmap_{page,single} is a nop so... */ 159b8b572e1SStephen Rothwell #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) 160b8b572e1SStephen Rothwell #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) 161b8b572e1SStephen Rothwell #define pci_unmap_addr(PTR, ADDR_NAME) (0) 162b8b572e1SStephen Rothwell #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) 163b8b572e1SStephen Rothwell #define pci_unmap_len(PTR, LEN_NAME) (0) 164b8b572e1SStephen Rothwell #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 165b8b572e1SStephen Rothwell 166b8b572e1SStephen Rothwell #endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */ 167b8b572e1SStephen Rothwell 168b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 169b8b572e1SStephen Rothwell 170b8b572e1SStephen Rothwell /* The PCI address space does not equal the physical memory address 171b8b572e1SStephen Rothwell * space (we have an IOMMU). The IDE and SCSI device layers use 172b8b572e1SStephen Rothwell * this boolean for bounce buffer decisions. 173b8b572e1SStephen Rothwell */ 174b8b572e1SStephen Rothwell #define PCI_DMA_BUS_IS_PHYS (0) 175b8b572e1SStephen Rothwell 176b8b572e1SStephen Rothwell #else /* 32-bit */ 177b8b572e1SStephen Rothwell 178b8b572e1SStephen Rothwell /* The PCI address space does equal the physical memory 179b8b572e1SStephen Rothwell * address space (no IOMMU). The IDE and SCSI device layers use 180b8b572e1SStephen Rothwell * this boolean for bounce buffer decisions. 181b8b572e1SStephen Rothwell */ 182b8b572e1SStephen Rothwell #define PCI_DMA_BUS_IS_PHYS (1) 183b8b572e1SStephen Rothwell 184b8b572e1SStephen Rothwell #endif /* CONFIG_PPC64 */ 185b8b572e1SStephen Rothwell 186b8b572e1SStephen Rothwell extern void pcibios_resource_to_bus(struct pci_dev *dev, 187b8b572e1SStephen Rothwell struct pci_bus_region *region, 188b8b572e1SStephen Rothwell struct resource *res); 189b8b572e1SStephen Rothwell 190b8b572e1SStephen Rothwell extern void pcibios_bus_to_resource(struct pci_dev *dev, 191b8b572e1SStephen Rothwell struct resource *res, 192b8b572e1SStephen Rothwell struct pci_bus_region *region); 193b8b572e1SStephen Rothwell 194b8b572e1SStephen Rothwell static inline struct resource *pcibios_select_root(struct pci_dev *pdev, 195b8b572e1SStephen Rothwell struct resource *res) 196b8b572e1SStephen Rothwell { 197b8b572e1SStephen Rothwell struct resource *root = NULL; 198b8b572e1SStephen Rothwell 199b8b572e1SStephen Rothwell if (res->flags & IORESOURCE_IO) 200b8b572e1SStephen Rothwell root = &ioport_resource; 201b8b572e1SStephen Rothwell if (res->flags & IORESOURCE_MEM) 202b8b572e1SStephen Rothwell root = &iomem_resource; 203b8b572e1SStephen Rothwell 204b8b572e1SStephen Rothwell return root; 205b8b572e1SStephen Rothwell } 206b8b572e1SStephen Rothwell 207b8b572e1SStephen Rothwell extern void pcibios_setup_new_device(struct pci_dev *dev); 208b8b572e1SStephen Rothwell 209b8b572e1SStephen Rothwell extern void pcibios_claim_one_bus(struct pci_bus *b); 210b8b572e1SStephen Rothwell 211e90a1318SNathan Fontenot extern void pcibios_allocate_bus_resources(struct pci_bus *bus); 212e90a1318SNathan Fontenot 213b8b572e1SStephen Rothwell extern void pcibios_resource_survey(void); 214b8b572e1SStephen Rothwell 215b8b572e1SStephen Rothwell extern struct pci_controller *init_phb_dynamic(struct device_node *dn); 216b8b572e1SStephen Rothwell 217b8b572e1SStephen Rothwell extern struct pci_dev *of_create_pci_dev(struct device_node *node, 218b8b572e1SStephen Rothwell struct pci_bus *bus, int devfn); 219b8b572e1SStephen Rothwell 220b8b572e1SStephen Rothwell extern void of_scan_pci_bridge(struct device_node *node, 221b8b572e1SStephen Rothwell struct pci_dev *dev); 222b8b572e1SStephen Rothwell 223b8b572e1SStephen Rothwell extern void of_scan_bus(struct device_node *node, struct pci_bus *bus); 2248b8da358SBenjamin Herrenschmidt extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus); 225b8b572e1SStephen Rothwell 226b8b572e1SStephen Rothwell extern int pci_read_irq_line(struct pci_dev *dev); 227b8b572e1SStephen Rothwell 228b8b572e1SStephen Rothwell struct file; 229b8b572e1SStephen Rothwell extern pgprot_t pci_phys_mem_access_prot(struct file *file, 230b8b572e1SStephen Rothwell unsigned long pfn, 231b8b572e1SStephen Rothwell unsigned long size, 232b8b572e1SStephen Rothwell pgprot_t prot); 233b8b572e1SStephen Rothwell 234b8b572e1SStephen Rothwell #define HAVE_ARCH_PCI_RESOURCE_TO_USER 235b8b572e1SStephen Rothwell extern void pci_resource_to_user(const struct pci_dev *dev, int bar, 236b8b572e1SStephen Rothwell const struct resource *rsrc, 237b8b572e1SStephen Rothwell resource_size_t *start, resource_size_t *end); 238b8b572e1SStephen Rothwell 2398b8da358SBenjamin Herrenschmidt extern void pcibios_setup_bus_devices(struct pci_bus *bus); 2408b8da358SBenjamin Herrenschmidt extern void pcibios_setup_bus_self(struct pci_bus *bus); 241e9f82cb7SBenjamin Herrenschmidt 242b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 243b8b572e1SStephen Rothwell #endif /* __ASM_POWERPC_PCI_H */ 244