1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
3 #ifdef __KERNEL__
4 /*
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version
8  * 2 of the License, or (at your option) any later version.
9  */
10 #include <linux/pci.h>
11 #include <linux/list.h>
12 #include <linux/ioport.h>
13 #include <asm-generic/pci-bridge.h>
14 
15 struct device_node;
16 
17 /*
18  * Structure of a PCI controller (host bridge)
19  */
20 struct pci_controller {
21 	struct pci_bus *bus;
22 	char is_dynamic;
23 #ifdef CONFIG_PPC64
24 	int node;
25 #endif
26 	struct device_node *dn;
27 	struct list_head list_node;
28 	struct device *parent;
29 
30 	int first_busno;
31 	int last_busno;
32 	int self_busno;
33 	struct resource busn;
34 
35 	void __iomem *io_base_virt;
36 #ifdef CONFIG_PPC64
37 	void *io_base_alloc;
38 #endif
39 	resource_size_t io_base_phys;
40 	resource_size_t pci_io_size;
41 
42 	/* Some machines (PReP) have a non 1:1 mapping of
43 	 * the PCI memory space in the CPU bus space
44 	 */
45 	resource_size_t pci_mem_offset;
46 
47 	/* Some machines have a special region to forward the ISA
48 	 * "memory" cycles such as VGA memory regions. Left to 0
49 	 * if unsupported
50 	 */
51 	resource_size_t	isa_mem_phys;
52 	resource_size_t	isa_mem_size;
53 
54 	struct pci_ops *ops;
55 	unsigned int __iomem *cfg_addr;
56 	void __iomem *cfg_data;
57 
58 	/*
59 	 * Used for variants of PCI indirect handling and possible quirks:
60 	 *  SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
61 	 *  EXT_REG - provides access to PCI-e extended registers
62 	 *  SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
63 	 *   on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
64 	 *   to determine which bus number to match on when generating type0
65 	 *   config cycles
66 	 *  NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
67 	 *   hanging if we don't have link and try to do config cycles to
68 	 *   anything but the PHB.  Only allow talking to the PHB if this is
69 	 *   set.
70 	 *  BIG_ENDIAN - cfg_addr is a big endian register
71 	 *  BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
72 	 *   the PLB4.  Effectively disable MRM commands by setting this.
73 	 */
74 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE		0x00000001
75 #define PPC_INDIRECT_TYPE_EXT_REG		0x00000002
76 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS	0x00000004
77 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK		0x00000008
78 #define PPC_INDIRECT_TYPE_BIG_ENDIAN		0x00000010
79 #define PPC_INDIRECT_TYPE_BROKEN_MRM		0x00000020
80 	u32 indirect_type;
81 	/* Currently, we limit ourselves to 1 IO range and 3 mem
82 	 * ranges since the common pci_bus structure can't handle more
83 	 */
84 	struct resource	io_resource;
85 	struct resource mem_resources[3];
86 	int global_number;		/* PCI domain number */
87 
88 	resource_size_t dma_window_base_cur;
89 	resource_size_t dma_window_size;
90 
91 #ifdef CONFIG_PPC64
92 	unsigned long buid;
93 
94 	void *private_data;
95 #endif	/* CONFIG_PPC64 */
96 };
97 
98 /* These are used for config access before all the PCI probing
99    has been done. */
100 extern int early_read_config_byte(struct pci_controller *hose, int bus,
101 			int dev_fn, int where, u8 *val);
102 extern int early_read_config_word(struct pci_controller *hose, int bus,
103 			int dev_fn, int where, u16 *val);
104 extern int early_read_config_dword(struct pci_controller *hose, int bus,
105 			int dev_fn, int where, u32 *val);
106 extern int early_write_config_byte(struct pci_controller *hose, int bus,
107 			int dev_fn, int where, u8 val);
108 extern int early_write_config_word(struct pci_controller *hose, int bus,
109 			int dev_fn, int where, u16 val);
110 extern int early_write_config_dword(struct pci_controller *hose, int bus,
111 			int dev_fn, int where, u32 val);
112 
113 extern int early_find_capability(struct pci_controller *hose, int bus,
114 				 int dev_fn, int cap);
115 
116 extern void setup_indirect_pci(struct pci_controller* hose,
117 			       resource_size_t cfg_addr,
118 			       resource_size_t cfg_data, u32 flags);
119 
120 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
121 {
122 	return bus->sysdata;
123 }
124 
125 #ifndef CONFIG_PPC64
126 
127 extern int pci_device_from_OF_node(struct device_node *node,
128 				   u8 *bus, u8 *devfn);
129 extern void pci_create_OF_bus_map(void);
130 
131 static inline int isa_vaddr_is_ioport(void __iomem *address)
132 {
133 	/* No specific ISA handling on ppc32 at this stage, it
134 	 * all goes through PCI
135 	 */
136 	return 0;
137 }
138 
139 #else	/* CONFIG_PPC64 */
140 
141 /*
142  * PCI stuff, for nodes representing PCI devices, pointed to
143  * by device_node->data.
144  */
145 struct iommu_table;
146 
147 struct pci_dn {
148 	int	busno;			/* pci bus number */
149 	int	devfn;			/* pci device and function number */
150 
151 	struct  pci_controller *phb;	/* for pci devices */
152 	struct	iommu_table *iommu_table;	/* for phb's or bridges */
153 	struct	device_node *node;	/* back-pointer to the device_node */
154 
155 	int	pci_ext_config_space;	/* for pci devices */
156 
157 	struct	pci_dev *pcidev;	/* back-pointer to the pci device */
158 #ifdef CONFIG_EEH
159 	struct eeh_dev *edev;		/* eeh device */
160 #endif
161 #define IODA_INVALID_PE		(-1)
162 #ifdef CONFIG_PPC_POWERNV
163 	int	pe_number;
164 #endif
165 };
166 
167 /* Get the pointer to a device_node's pci_dn */
168 #define PCI_DN(dn)	((struct pci_dn *) (dn)->data)
169 
170 extern void * update_dn_pci_info(struct device_node *dn, void *data);
171 
172 static inline int pci_device_from_OF_node(struct device_node *np,
173 					  u8 *bus, u8 *devfn)
174 {
175 	if (!PCI_DN(np))
176 		return -ENODEV;
177 	*bus = PCI_DN(np)->busno;
178 	*devfn = PCI_DN(np)->devfn;
179 	return 0;
180 }
181 
182 #if defined(CONFIG_EEH)
183 static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn)
184 {
185 	/*
186 	 * For those OF nodes whose parent isn't PCI bridge, they
187 	 * don't have PCI_DN actually. So we have to skip them for
188 	 * any EEH operations.
189 	 */
190 	if (!dn || !PCI_DN(dn))
191 		return NULL;
192 
193 	return PCI_DN(dn)->edev;
194 }
195 #else
196 #define of_node_to_eeh_dev(x) (NULL)
197 #endif
198 
199 /** Find the bus corresponding to the indicated device node */
200 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
201 
202 /** Remove all of the PCI devices under this bus */
203 extern void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe);
204 extern void pcibios_remove_pci_devices(struct pci_bus *bus);
205 
206 /** Discover new pci devices under this bus, and add them */
207 extern void pcibios_add_pci_devices(struct pci_bus *bus);
208 
209 
210 extern void isa_bridge_find_early(struct pci_controller *hose);
211 
212 static inline int isa_vaddr_is_ioport(void __iomem *address)
213 {
214 	/* Check if address hits the reserved legacy IO range */
215 	unsigned long ea = (unsigned long)address;
216 	return ea >= ISA_IO_BASE && ea < ISA_IO_END;
217 }
218 
219 extern int pcibios_unmap_io_space(struct pci_bus *bus);
220 extern int pcibios_map_io_space(struct pci_bus *bus);
221 
222 #ifdef CONFIG_NUMA
223 #define PHB_SET_NODE(PHB, NODE)		((PHB)->node = (NODE))
224 #else
225 #define PHB_SET_NODE(PHB, NODE)		((PHB)->node = -1)
226 #endif
227 
228 #endif	/* CONFIG_PPC64 */
229 
230 /* Get the PCI host controller for an OF device */
231 extern struct pci_controller *pci_find_hose_for_OF_device(
232 			struct device_node* node);
233 
234 /* Fill up host controller resources from the OF node */
235 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
236 			struct device_node *dev, int primary);
237 
238 /* Allocate & free a PCI host bridge structure */
239 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
240 extern void pcibios_free_controller(struct pci_controller *phb);
241 
242 #ifdef CONFIG_PCI
243 extern int pcibios_vaddr_is_ioport(void __iomem *address);
244 #else
245 static inline int pcibios_vaddr_is_ioport(void __iomem *address)
246 {
247 	return 0;
248 }
249 #endif	/* CONFIG_PCI */
250 
251 #endif	/* __KERNEL__ */
252 #endif	/* _ASM_POWERPC_PCI_BRIDGE_H */
253