1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2 #define _ASM_POWERPC_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 14 struct device_node; 15 16 enum { 17 /* Force re-assigning all resources (ignore firmware 18 * setup completely) 19 */ 20 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, 21 22 /* Re-assign all bus numbers */ 23 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, 24 25 /* Do not try to assign, just use existing setup */ 26 PPC_PCI_PROBE_ONLY = 0x00000004, 27 28 /* Don't bother with ISA alignment unless the bridge has 29 * ISA forwarding enabled 30 */ 31 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 32 33 /* Enable domain numbers in /proc */ 34 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, 35 /* ... except for domain 0 */ 36 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, 37 }; 38 #ifdef CONFIG_PCI 39 extern unsigned int ppc_pci_flags; 40 41 static inline void ppc_pci_set_flags(int flags) 42 { 43 ppc_pci_flags = flags; 44 } 45 46 static inline void ppc_pci_add_flags(int flags) 47 { 48 ppc_pci_flags |= flags; 49 } 50 51 static inline int ppc_pci_has_flag(int flag) 52 { 53 return (ppc_pci_flags & flag); 54 } 55 #else 56 static inline void ppc_pci_set_flags(int flags) { } 57 static inline void ppc_pci_add_flags(int flags) { } 58 static inline int ppc_pci_has_flag(int flag) 59 { 60 return 0; 61 } 62 #endif 63 64 65 /* 66 * Structure of a PCI controller (host bridge) 67 */ 68 struct pci_controller { 69 struct pci_bus *bus; 70 char is_dynamic; 71 #ifdef CONFIG_PPC64 72 int node; 73 #endif 74 struct device_node *dn; 75 struct list_head list_node; 76 struct device *parent; 77 78 int first_busno; 79 int last_busno; 80 #ifndef CONFIG_PPC64 81 int self_busno; 82 #endif 83 84 void __iomem *io_base_virt; 85 #ifdef CONFIG_PPC64 86 void *io_base_alloc; 87 #endif 88 resource_size_t io_base_phys; 89 #ifndef CONFIG_PPC64 90 resource_size_t pci_io_size; 91 #endif 92 93 /* Some machines (PReP) have a non 1:1 mapping of 94 * the PCI memory space in the CPU bus space 95 */ 96 resource_size_t pci_mem_offset; 97 #ifdef CONFIG_PPC64 98 unsigned long pci_io_size; 99 #endif 100 101 /* Some machines have a special region to forward the ISA 102 * "memory" cycles such as VGA memory regions. Left to 0 103 * if unsupported 104 */ 105 resource_size_t isa_mem_phys; 106 resource_size_t isa_mem_size; 107 108 struct pci_ops *ops; 109 unsigned int __iomem *cfg_addr; 110 void __iomem *cfg_data; 111 112 #ifndef CONFIG_PPC64 113 /* 114 * Used for variants of PCI indirect handling and possible quirks: 115 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 116 * EXT_REG - provides access to PCI-e extended registers 117 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS 118 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 119 * to determine which bus number to match on when generating type0 120 * config cycles 121 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 122 * hanging if we don't have link and try to do config cycles to 123 * anything but the PHB. Only allow talking to the PHB if this is 124 * set. 125 * BIG_ENDIAN - cfg_addr is a big endian register 126 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 127 * the PLB4. Effectively disable MRM commands by setting this. 128 */ 129 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 130 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 131 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 132 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 133 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 134 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 135 u32 indirect_type; 136 #endif /* !CONFIG_PPC64 */ 137 /* Currently, we limit ourselves to 1 IO range and 3 mem 138 * ranges since the common pci_bus structure can't handle more 139 */ 140 struct resource io_resource; 141 struct resource mem_resources[3]; 142 int global_number; /* PCI domain number */ 143 #ifdef CONFIG_PPC64 144 unsigned long buid; 145 unsigned long dma_window_base_cur; 146 unsigned long dma_window_size; 147 148 void *private_data; 149 #endif /* CONFIG_PPC64 */ 150 }; 151 152 #ifndef CONFIG_PPC64 153 154 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 155 { 156 return bus->sysdata; 157 } 158 159 static inline int isa_vaddr_is_ioport(void __iomem *address) 160 { 161 /* No specific ISA handling on ppc32 at this stage, it 162 * all goes through PCI 163 */ 164 return 0; 165 } 166 167 /* These are used for config access before all the PCI probing 168 has been done. */ 169 extern int early_read_config_byte(struct pci_controller *hose, int bus, 170 int dev_fn, int where, u8 *val); 171 extern int early_read_config_word(struct pci_controller *hose, int bus, 172 int dev_fn, int where, u16 *val); 173 extern int early_read_config_dword(struct pci_controller *hose, int bus, 174 int dev_fn, int where, u32 *val); 175 extern int early_write_config_byte(struct pci_controller *hose, int bus, 176 int dev_fn, int where, u8 val); 177 extern int early_write_config_word(struct pci_controller *hose, int bus, 178 int dev_fn, int where, u16 val); 179 extern int early_write_config_dword(struct pci_controller *hose, int bus, 180 int dev_fn, int where, u32 val); 181 182 extern int early_find_capability(struct pci_controller *hose, int bus, 183 int dev_fn, int cap); 184 185 extern void setup_indirect_pci(struct pci_controller* hose, 186 resource_size_t cfg_addr, 187 resource_size_t cfg_data, u32 flags); 188 extern void setup_grackle(struct pci_controller *hose); 189 #else /* CONFIG_PPC64 */ 190 191 /* 192 * PCI stuff, for nodes representing PCI devices, pointed to 193 * by device_node->data. 194 */ 195 struct iommu_table; 196 197 struct pci_dn { 198 int busno; /* pci bus number */ 199 int devfn; /* pci device and function number */ 200 201 struct pci_controller *phb; /* for pci devices */ 202 struct iommu_table *iommu_table; /* for phb's or bridges */ 203 struct device_node *node; /* back-pointer to the device_node */ 204 205 int pci_ext_config_space; /* for pci devices */ 206 207 #ifdef CONFIG_EEH 208 struct pci_dev *pcidev; /* back-pointer to the pci device */ 209 int class_code; /* pci device class */ 210 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 211 int eeh_config_addr; 212 int eeh_pe_config_addr; /* new-style partition endpoint address */ 213 int eeh_check_count; /* # times driver ignored error */ 214 int eeh_freeze_count; /* # times this device froze up. */ 215 int eeh_false_positives; /* # times this device reported #ff's */ 216 u32 config_space[16]; /* saved PCI config space */ 217 #endif 218 }; 219 220 /* Get the pointer to a device_node's pci_dn */ 221 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 222 223 extern struct device_node *fetch_dev_dn(struct pci_dev *dev); 224 225 /* Get a device_node from a pci_dev. This code must be fast except 226 * in the case where the sysdata is incorrect and needs to be fixed 227 * up (this will only happen once). 228 * In this case the sysdata will have been inherited from a PCI host 229 * bridge or a PCI-PCI bridge further up the tree, so it will point 230 * to a valid struct pci_dn, just not the one we want. 231 */ 232 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) 233 { 234 struct device_node *dn = dev->sysdata; 235 struct pci_dn *pdn = dn->data; 236 237 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number) 238 return dn; /* fast path. sysdata is good */ 239 return fetch_dev_dn(dev); 240 } 241 242 static inline int pci_device_from_OF_node(struct device_node *np, 243 u8 *bus, u8 *devfn) 244 { 245 if (!PCI_DN(np)) 246 return -ENODEV; 247 *bus = PCI_DN(np)->busno; 248 *devfn = PCI_DN(np)->devfn; 249 return 0; 250 } 251 252 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 253 { 254 if (bus->self) 255 return pci_device_to_OF_node(bus->self); 256 else 257 return bus->sysdata; /* Must be root bus (PHB) */ 258 } 259 260 /** Find the bus corresponding to the indicated device node */ 261 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); 262 263 /** Remove all of the PCI devices under this bus */ 264 extern void pcibios_remove_pci_devices(struct pci_bus *bus); 265 266 /** Discover new pci devices under this bus, and add them */ 267 extern void pcibios_add_pci_devices(struct pci_bus *bus); 268 269 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 270 { 271 struct device_node *busdn = bus->sysdata; 272 273 BUG_ON(busdn == NULL); 274 return PCI_DN(busdn)->phb; 275 } 276 277 278 extern void isa_bridge_find_early(struct pci_controller *hose); 279 280 static inline int isa_vaddr_is_ioport(void __iomem *address) 281 { 282 /* Check if address hits the reserved legacy IO range */ 283 unsigned long ea = (unsigned long)address; 284 return ea >= ISA_IO_BASE && ea < ISA_IO_END; 285 } 286 287 extern int pcibios_unmap_io_space(struct pci_bus *bus); 288 extern int pcibios_map_io_space(struct pci_bus *bus); 289 290 /* Return values for ppc_md.pci_probe_mode function */ 291 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ 292 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ 293 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ 294 295 #ifdef CONFIG_NUMA 296 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 297 #else 298 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 299 #endif 300 301 #endif /* CONFIG_PPC64 */ 302 303 /* Get the PCI host controller for an OF device */ 304 extern struct pci_controller *pci_find_hose_for_OF_device( 305 struct device_node* node); 306 307 /* Fill up host controller resources from the OF node */ 308 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 309 struct device_node *dev, int primary); 310 311 /* Allocate & free a PCI host bridge structure */ 312 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 313 extern void pcibios_free_controller(struct pci_controller *phb); 314 extern void pcibios_setup_phb_resources(struct pci_controller *hose); 315 316 #ifdef CONFIG_PCI 317 extern unsigned long pci_address_to_pio(phys_addr_t address); 318 extern int pcibios_vaddr_is_ioport(void __iomem *address); 319 #else 320 static inline unsigned long pci_address_to_pio(phys_addr_t address) 321 { 322 return (unsigned long)-1; 323 } 324 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 325 { 326 return 0; 327 } 328 #endif /* CONFIG_PCI */ 329 330 #endif /* __KERNEL__ */ 331 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 332