1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2 #define _ASM_POWERPC_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 14 struct device_node; 15 16 extern unsigned int ppc_pci_flags; 17 enum { 18 /* Force re-assigning all resources (ignore firmware 19 * setup completely) 20 */ 21 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, 22 23 /* Re-assign all bus numbers */ 24 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, 25 26 /* Do not try to assign, just use existing setup */ 27 PPC_PCI_PROBE_ONLY = 0x00000004, 28 29 /* Don't bother with ISA alignment unless the bridge has 30 * ISA forwarding enabled 31 */ 32 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 33 34 /* Enable domain numbers in /proc */ 35 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, 36 /* ... except for domain 0 */ 37 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, 38 }; 39 40 41 /* 42 * Structure of a PCI controller (host bridge) 43 */ 44 struct pci_controller { 45 struct pci_bus *bus; 46 char is_dynamic; 47 #ifdef CONFIG_PPC64 48 int node; 49 #endif 50 struct device_node *dn; 51 struct list_head list_node; 52 struct device *parent; 53 54 int first_busno; 55 int last_busno; 56 #ifndef CONFIG_PPC64 57 int self_busno; 58 #endif 59 60 void __iomem *io_base_virt; 61 #ifdef CONFIG_PPC64 62 void *io_base_alloc; 63 #endif 64 resource_size_t io_base_phys; 65 #ifndef CONFIG_PPC64 66 resource_size_t pci_io_size; 67 #endif 68 69 /* Some machines (PReP) have a non 1:1 mapping of 70 * the PCI memory space in the CPU bus space 71 */ 72 resource_size_t pci_mem_offset; 73 #ifdef CONFIG_PPC64 74 unsigned long pci_io_size; 75 #endif 76 77 /* Some machines have a special region to forward the ISA 78 * "memory" cycles such as VGA memory regions. Left to 0 79 * if unsupported 80 */ 81 resource_size_t isa_mem_phys; 82 resource_size_t isa_mem_size; 83 84 struct pci_ops *ops; 85 unsigned int __iomem *cfg_addr; 86 void __iomem *cfg_data; 87 88 #ifndef CONFIG_PPC64 89 /* 90 * Used for variants of PCI indirect handling and possible quirks: 91 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 92 * EXT_REG - provides access to PCI-e extended registers 93 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS 94 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 95 * to determine which bus number to match on when generating type0 96 * config cycles 97 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 98 * hanging if we don't have link and try to do config cycles to 99 * anything but the PHB. Only allow talking to the PHB if this is 100 * set. 101 * BIG_ENDIAN - cfg_addr is a big endian register 102 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 103 * the PLB4. Effectively disable MRM commands by setting this. 104 */ 105 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 106 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 107 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 108 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 109 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 110 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 111 u32 indirect_type; 112 #endif /* !CONFIG_PPC64 */ 113 /* Currently, we limit ourselves to 1 IO range and 3 mem 114 * ranges since the common pci_bus structure can't handle more 115 */ 116 struct resource io_resource; 117 struct resource mem_resources[3]; 118 int global_number; /* PCI domain number */ 119 #ifdef CONFIG_PPC64 120 unsigned long buid; 121 unsigned long dma_window_base_cur; 122 unsigned long dma_window_size; 123 124 void *private_data; 125 #endif /* CONFIG_PPC64 */ 126 }; 127 128 #ifndef CONFIG_PPC64 129 130 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 131 { 132 return bus->sysdata; 133 } 134 135 static inline int isa_vaddr_is_ioport(void __iomem *address) 136 { 137 /* No specific ISA handling on ppc32 at this stage, it 138 * all goes through PCI 139 */ 140 return 0; 141 } 142 143 /* These are used for config access before all the PCI probing 144 has been done. */ 145 extern int early_read_config_byte(struct pci_controller *hose, int bus, 146 int dev_fn, int where, u8 *val); 147 extern int early_read_config_word(struct pci_controller *hose, int bus, 148 int dev_fn, int where, u16 *val); 149 extern int early_read_config_dword(struct pci_controller *hose, int bus, 150 int dev_fn, int where, u32 *val); 151 extern int early_write_config_byte(struct pci_controller *hose, int bus, 152 int dev_fn, int where, u8 val); 153 extern int early_write_config_word(struct pci_controller *hose, int bus, 154 int dev_fn, int where, u16 val); 155 extern int early_write_config_dword(struct pci_controller *hose, int bus, 156 int dev_fn, int where, u32 val); 157 158 extern int early_find_capability(struct pci_controller *hose, int bus, 159 int dev_fn, int cap); 160 161 extern void setup_indirect_pci(struct pci_controller* hose, 162 resource_size_t cfg_addr, 163 resource_size_t cfg_data, u32 flags); 164 extern void setup_grackle(struct pci_controller *hose); 165 #else /* CONFIG_PPC64 */ 166 167 /* 168 * PCI stuff, for nodes representing PCI devices, pointed to 169 * by device_node->data. 170 */ 171 struct iommu_table; 172 173 struct pci_dn { 174 int busno; /* pci bus number */ 175 int devfn; /* pci device and function number */ 176 177 struct pci_controller *phb; /* for pci devices */ 178 struct iommu_table *iommu_table; /* for phb's or bridges */ 179 struct device_node *node; /* back-pointer to the device_node */ 180 181 int pci_ext_config_space; /* for pci devices */ 182 183 #ifdef CONFIG_EEH 184 struct pci_dev *pcidev; /* back-pointer to the pci device */ 185 int class_code; /* pci device class */ 186 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 187 int eeh_config_addr; 188 int eeh_pe_config_addr; /* new-style partition endpoint address */ 189 int eeh_check_count; /* # times driver ignored error */ 190 int eeh_freeze_count; /* # times this device froze up. */ 191 int eeh_false_positives; /* # times this device reported #ff's */ 192 u32 config_space[16]; /* saved PCI config space */ 193 #endif 194 }; 195 196 /* Get the pointer to a device_node's pci_dn */ 197 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 198 199 extern struct device_node *fetch_dev_dn(struct pci_dev *dev); 200 201 /* Get a device_node from a pci_dev. This code must be fast except 202 * in the case where the sysdata is incorrect and needs to be fixed 203 * up (this will only happen once). 204 * In this case the sysdata will have been inherited from a PCI host 205 * bridge or a PCI-PCI bridge further up the tree, so it will point 206 * to a valid struct pci_dn, just not the one we want. 207 */ 208 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) 209 { 210 struct device_node *dn = dev->sysdata; 211 struct pci_dn *pdn = dn->data; 212 213 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number) 214 return dn; /* fast path. sysdata is good */ 215 return fetch_dev_dn(dev); 216 } 217 218 static inline int pci_device_from_OF_node(struct device_node *np, 219 u8 *bus, u8 *devfn) 220 { 221 if (!PCI_DN(np)) 222 return -ENODEV; 223 *bus = PCI_DN(np)->busno; 224 *devfn = PCI_DN(np)->devfn; 225 return 0; 226 } 227 228 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 229 { 230 if (bus->self) 231 return pci_device_to_OF_node(bus->self); 232 else 233 return bus->sysdata; /* Must be root bus (PHB) */ 234 } 235 236 /** Find the bus corresponding to the indicated device node */ 237 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); 238 239 /** Remove all of the PCI devices under this bus */ 240 extern void pcibios_remove_pci_devices(struct pci_bus *bus); 241 242 /** Discover new pci devices under this bus, and add them */ 243 extern void pcibios_add_pci_devices(struct pci_bus *bus); 244 extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus); 245 246 extern int pcibios_remove_root_bus(struct pci_controller *phb); 247 248 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 249 { 250 struct device_node *busdn = bus->sysdata; 251 252 BUG_ON(busdn == NULL); 253 return PCI_DN(busdn)->phb; 254 } 255 256 257 extern void isa_bridge_find_early(struct pci_controller *hose); 258 259 static inline int isa_vaddr_is_ioport(void __iomem *address) 260 { 261 /* Check if address hits the reserved legacy IO range */ 262 unsigned long ea = (unsigned long)address; 263 return ea >= ISA_IO_BASE && ea < ISA_IO_END; 264 } 265 266 extern int pcibios_unmap_io_space(struct pci_bus *bus); 267 extern int pcibios_map_io_space(struct pci_bus *bus); 268 269 /* Return values for ppc_md.pci_probe_mode function */ 270 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ 271 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ 272 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ 273 274 #ifdef CONFIG_NUMA 275 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 276 #else 277 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 278 #endif 279 280 #endif /* CONFIG_PPC64 */ 281 282 /* Get the PCI host controller for an OF device */ 283 extern struct pci_controller *pci_find_hose_for_OF_device( 284 struct device_node* node); 285 286 /* Fill up host controller resources from the OF node */ 287 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 288 struct device_node *dev, int primary); 289 290 /* Allocate & free a PCI host bridge structure */ 291 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 292 extern void pcibios_free_controller(struct pci_controller *phb); 293 294 #ifdef CONFIG_PCI 295 extern unsigned long pci_address_to_pio(phys_addr_t address); 296 extern int pcibios_vaddr_is_ioport(void __iomem *address); 297 #else 298 static inline unsigned long pci_address_to_pio(phys_addr_t address) 299 { 300 return (unsigned long)-1; 301 } 302 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 303 { 304 return 0; 305 } 306 #endif /* CONFIG_PCI */ 307 308 #endif /* __KERNEL__ */ 309 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 310