1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2 #define _ASM_POWERPC_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 14 struct device_node; 15 16 /* 17 * PCI controller operations 18 */ 19 struct pci_controller_ops { 20 void (*dma_dev_setup)(struct pci_dev *pdev); 21 void (*dma_bus_setup)(struct pci_bus *bus); 22 bool (*iommu_bypass_supported)(struct pci_dev *pdev, 23 u64 mask); 24 25 int (*probe_mode)(struct pci_bus *bus); 26 27 /* Called when pci_enable_device() is called. Returns true to 28 * allow assignment/enabling of the device. */ 29 bool (*enable_device_hook)(struct pci_dev *pdev); 30 31 void (*disable_device)(struct pci_dev *pdev); 32 33 void (*release_device)(struct pci_dev *pdev); 34 35 /* Called during PCI resource reassignment */ 36 resource_size_t (*window_alignment)(struct pci_bus *bus, 37 unsigned long type); 38 void (*setup_bridge)(struct pci_bus *bus, 39 unsigned long type); 40 void (*reset_secondary_bus)(struct pci_dev *pdev); 41 42 #ifdef CONFIG_PCI_MSI 43 int (*setup_msi_irqs)(struct pci_dev *pdev, 44 int nvec, int type); 45 void (*teardown_msi_irqs)(struct pci_dev *pdev); 46 #endif 47 48 int (*dma_set_mask)(struct pci_dev *pdev, u64 dma_mask); 49 u64 (*dma_get_required_mask)(struct pci_dev *pdev); 50 51 void (*shutdown)(struct pci_controller *hose); 52 }; 53 54 /* 55 * Structure of a PCI controller (host bridge) 56 */ 57 struct pci_controller { 58 struct pci_bus *bus; 59 char is_dynamic; 60 #ifdef CONFIG_PPC64 61 int node; 62 #endif 63 struct device_node *dn; 64 struct list_head list_node; 65 struct device *parent; 66 67 int first_busno; 68 int last_busno; 69 int self_busno; 70 struct resource busn; 71 72 void __iomem *io_base_virt; 73 #ifdef CONFIG_PPC64 74 void *io_base_alloc; 75 #endif 76 resource_size_t io_base_phys; 77 resource_size_t pci_io_size; 78 79 /* Some machines have a special region to forward the ISA 80 * "memory" cycles such as VGA memory regions. Left to 0 81 * if unsupported 82 */ 83 resource_size_t isa_mem_phys; 84 resource_size_t isa_mem_size; 85 86 struct pci_controller_ops controller_ops; 87 struct pci_ops *ops; 88 unsigned int __iomem *cfg_addr; 89 void __iomem *cfg_data; 90 91 /* 92 * Used for variants of PCI indirect handling and possible quirks: 93 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 94 * EXT_REG - provides access to PCI-e extended registers 95 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 96 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 97 * to determine which bus number to match on when generating type0 98 * config cycles 99 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 100 * hanging if we don't have link and try to do config cycles to 101 * anything but the PHB. Only allow talking to the PHB if this is 102 * set. 103 * BIG_ENDIAN - cfg_addr is a big endian register 104 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 105 * the PLB4. Effectively disable MRM commands by setting this. 106 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe 107 * link status is in a RC PCIe cfg register (vs being a SoC register) 108 */ 109 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 110 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 111 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 112 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 113 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 114 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 115 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 116 u32 indirect_type; 117 /* Currently, we limit ourselves to 1 IO range and 3 mem 118 * ranges since the common pci_bus structure can't handle more 119 */ 120 struct resource io_resource; 121 struct resource mem_resources[3]; 122 resource_size_t mem_offset[3]; 123 int global_number; /* PCI domain number */ 124 125 resource_size_t dma_window_base_cur; 126 resource_size_t dma_window_size; 127 128 #ifdef CONFIG_PPC64 129 unsigned long buid; 130 struct pci_dn *pci_data; 131 #endif /* CONFIG_PPC64 */ 132 133 void *private_data; 134 struct npu *npu; 135 }; 136 137 /* These are used for config access before all the PCI probing 138 has been done. */ 139 extern int early_read_config_byte(struct pci_controller *hose, int bus, 140 int dev_fn, int where, u8 *val); 141 extern int early_read_config_word(struct pci_controller *hose, int bus, 142 int dev_fn, int where, u16 *val); 143 extern int early_read_config_dword(struct pci_controller *hose, int bus, 144 int dev_fn, int where, u32 *val); 145 extern int early_write_config_byte(struct pci_controller *hose, int bus, 146 int dev_fn, int where, u8 val); 147 extern int early_write_config_word(struct pci_controller *hose, int bus, 148 int dev_fn, int where, u16 val); 149 extern int early_write_config_dword(struct pci_controller *hose, int bus, 150 int dev_fn, int where, u32 val); 151 152 extern int early_find_capability(struct pci_controller *hose, int bus, 153 int dev_fn, int cap); 154 155 extern void setup_indirect_pci(struct pci_controller* hose, 156 resource_size_t cfg_addr, 157 resource_size_t cfg_data, u32 flags); 158 159 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, 160 int offset, int len, u32 *val); 161 162 extern int __indirect_read_config(struct pci_controller *hose, 163 unsigned char bus_number, unsigned int devfn, 164 int offset, int len, u32 *val); 165 166 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, 167 int offset, int len, u32 val); 168 169 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 170 { 171 return bus->sysdata; 172 } 173 174 #ifndef CONFIG_PPC64 175 176 extern int pci_device_from_OF_node(struct device_node *node, 177 u8 *bus, u8 *devfn); 178 extern void pci_create_OF_bus_map(void); 179 180 #else /* CONFIG_PPC64 */ 181 182 /* 183 * PCI stuff, for nodes representing PCI devices, pointed to 184 * by device_node->data. 185 */ 186 struct iommu_table; 187 188 struct pci_dn { 189 int flags; 190 #define PCI_DN_FLAG_IOV_VF 0x01 191 192 int busno; /* pci bus number */ 193 int devfn; /* pci device and function number */ 194 int vendor_id; /* Vendor ID */ 195 int device_id; /* Device ID */ 196 int class_code; /* Device class code */ 197 198 struct pci_dn *parent; 199 struct pci_controller *phb; /* for pci devices */ 200 struct iommu_table_group *table_group; /* for phb's or bridges */ 201 202 int pci_ext_config_space; /* for pci devices */ 203 #ifdef CONFIG_EEH 204 struct eeh_dev *edev; /* eeh device */ 205 #endif 206 #define IODA_INVALID_PE 0xFFFFFFFF 207 unsigned int pe_number; 208 #ifdef CONFIG_PCI_IOV 209 int vf_index; /* VF index in the PF */ 210 u16 vfs_expanded; /* number of VFs IOV BAR expanded */ 211 u16 num_vfs; /* number of VFs enabled*/ 212 unsigned int *pe_num_map; /* PE# for the first VF PE or array */ 213 bool m64_single_mode; /* Use M64 BAR in Single Mode */ 214 #define IODA_INVALID_M64 (-1) 215 int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */ 216 int last_allow_rc; /* Only used on pseries */ 217 #endif /* CONFIG_PCI_IOV */ 218 int mps; /* Maximum Payload Size */ 219 struct list_head child_list; 220 struct list_head list; 221 struct resource holes[PCI_SRIOV_NUM_BARS]; 222 }; 223 224 /* Get the pointer to a device_node's pci_dn */ 225 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 226 227 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, 228 int devfn); 229 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); 230 extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev); 231 extern void remove_dev_pci_data(struct pci_dev *pdev); 232 extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose, 233 struct device_node *dn); 234 extern void pci_remove_device_node_info(struct device_node *dn); 235 236 static inline int pci_device_from_OF_node(struct device_node *np, 237 u8 *bus, u8 *devfn) 238 { 239 if (!PCI_DN(np)) 240 return -ENODEV; 241 *bus = PCI_DN(np)->busno; 242 *devfn = PCI_DN(np)->devfn; 243 return 0; 244 } 245 246 #if defined(CONFIG_EEH) 247 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) 248 { 249 return pdn ? pdn->edev : NULL; 250 } 251 #else 252 #define pdn_to_eeh_dev(x) (NULL) 253 #endif 254 255 /** Find the bus corresponding to the indicated device node */ 256 extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn); 257 258 /** Remove all of the PCI devices under this bus */ 259 extern void pci_hp_remove_devices(struct pci_bus *bus); 260 261 /** Discover new pci devices under this bus, and add them */ 262 extern void pci_hp_add_devices(struct pci_bus *bus); 263 264 extern int pcibios_unmap_io_space(struct pci_bus *bus); 265 extern int pcibios_map_io_space(struct pci_bus *bus); 266 267 #ifdef CONFIG_NUMA 268 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 269 #else 270 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 271 #endif 272 273 #endif /* CONFIG_PPC64 */ 274 275 /* Get the PCI host controller for an OF device */ 276 extern struct pci_controller *pci_find_hose_for_OF_device( 277 struct device_node* node); 278 279 /* Fill up host controller resources from the OF node */ 280 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 281 struct device_node *dev, int primary); 282 283 /* Allocate & free a PCI host bridge structure */ 284 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 285 extern void pcibios_free_controller(struct pci_controller *phb); 286 extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge); 287 288 #ifdef CONFIG_PCI 289 extern int pcibios_vaddr_is_ioport(void __iomem *address); 290 #else 291 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 292 { 293 return 0; 294 } 295 #endif /* CONFIG_PCI */ 296 297 #endif /* __KERNEL__ */ 298 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 299