1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2 #define _ASM_POWERPC_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 14 struct device_node; 15 16 /* 17 * PCI controller operations 18 */ 19 struct pci_controller_ops { 20 void (*dma_dev_setup)(struct pci_dev *pdev); 21 void (*dma_bus_setup)(struct pci_bus *bus); 22 23 int (*probe_mode)(struct pci_bus *bus); 24 25 /* Called when pci_enable_device() is called. Returns true to 26 * allow assignment/enabling of the device. */ 27 bool (*enable_device_hook)(struct pci_dev *pdev); 28 29 void (*disable_device)(struct pci_dev *pdev); 30 31 void (*release_device)(struct pci_dev *pdev); 32 33 /* Called during PCI resource reassignment */ 34 resource_size_t (*window_alignment)(struct pci_bus *bus, 35 unsigned long type); 36 void (*setup_bridge)(struct pci_bus *bus, 37 unsigned long type); 38 void (*reset_secondary_bus)(struct pci_dev *pdev); 39 40 #ifdef CONFIG_PCI_MSI 41 int (*setup_msi_irqs)(struct pci_dev *pdev, 42 int nvec, int type); 43 void (*teardown_msi_irqs)(struct pci_dev *pdev); 44 #endif 45 46 int (*dma_set_mask)(struct pci_dev *pdev, u64 dma_mask); 47 u64 (*dma_get_required_mask)(struct pci_dev *pdev); 48 49 void (*shutdown)(struct pci_controller *hose); 50 }; 51 52 /* 53 * Structure of a PCI controller (host bridge) 54 */ 55 struct pci_controller { 56 struct pci_bus *bus; 57 char is_dynamic; 58 #ifdef CONFIG_PPC64 59 int node; 60 #endif 61 struct device_node *dn; 62 struct list_head list_node; 63 struct device *parent; 64 65 int first_busno; 66 int last_busno; 67 int self_busno; 68 struct resource busn; 69 70 void __iomem *io_base_virt; 71 #ifdef CONFIG_PPC64 72 void *io_base_alloc; 73 #endif 74 resource_size_t io_base_phys; 75 resource_size_t pci_io_size; 76 77 /* Some machines have a special region to forward the ISA 78 * "memory" cycles such as VGA memory regions. Left to 0 79 * if unsupported 80 */ 81 resource_size_t isa_mem_phys; 82 resource_size_t isa_mem_size; 83 84 struct pci_controller_ops controller_ops; 85 struct pci_ops *ops; 86 unsigned int __iomem *cfg_addr; 87 void __iomem *cfg_data; 88 89 /* 90 * Used for variants of PCI indirect handling and possible quirks: 91 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 92 * EXT_REG - provides access to PCI-e extended registers 93 * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 94 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 95 * to determine which bus number to match on when generating type0 96 * config cycles 97 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 98 * hanging if we don't have link and try to do config cycles to 99 * anything but the PHB. Only allow talking to the PHB if this is 100 * set. 101 * BIG_ENDIAN - cfg_addr is a big endian register 102 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 103 * the PLB4. Effectively disable MRM commands by setting this. 104 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe 105 * link status is in a RC PCIe cfg register (vs being a SoC register) 106 */ 107 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 108 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 109 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 110 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 111 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 112 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 113 #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 114 u32 indirect_type; 115 /* Currently, we limit ourselves to 1 IO range and 3 mem 116 * ranges since the common pci_bus structure can't handle more 117 */ 118 struct resource io_resource; 119 struct resource mem_resources[3]; 120 resource_size_t mem_offset[3]; 121 int global_number; /* PCI domain number */ 122 123 resource_size_t dma_window_base_cur; 124 resource_size_t dma_window_size; 125 126 #ifdef CONFIG_PPC64 127 unsigned long buid; 128 struct pci_dn *pci_data; 129 #endif /* CONFIG_PPC64 */ 130 131 void *private_data; 132 }; 133 134 /* These are used for config access before all the PCI probing 135 has been done. */ 136 extern int early_read_config_byte(struct pci_controller *hose, int bus, 137 int dev_fn, int where, u8 *val); 138 extern int early_read_config_word(struct pci_controller *hose, int bus, 139 int dev_fn, int where, u16 *val); 140 extern int early_read_config_dword(struct pci_controller *hose, int bus, 141 int dev_fn, int where, u32 *val); 142 extern int early_write_config_byte(struct pci_controller *hose, int bus, 143 int dev_fn, int where, u8 val); 144 extern int early_write_config_word(struct pci_controller *hose, int bus, 145 int dev_fn, int where, u16 val); 146 extern int early_write_config_dword(struct pci_controller *hose, int bus, 147 int dev_fn, int where, u32 val); 148 149 extern int early_find_capability(struct pci_controller *hose, int bus, 150 int dev_fn, int cap); 151 152 extern void setup_indirect_pci(struct pci_controller* hose, 153 resource_size_t cfg_addr, 154 resource_size_t cfg_data, u32 flags); 155 156 extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, 157 int offset, int len, u32 *val); 158 159 extern int __indirect_read_config(struct pci_controller *hose, 160 unsigned char bus_number, unsigned int devfn, 161 int offset, int len, u32 *val); 162 163 extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, 164 int offset, int len, u32 val); 165 166 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 167 { 168 return bus->sysdata; 169 } 170 171 #ifndef CONFIG_PPC64 172 173 extern int pci_device_from_OF_node(struct device_node *node, 174 u8 *bus, u8 *devfn); 175 extern void pci_create_OF_bus_map(void); 176 177 #else /* CONFIG_PPC64 */ 178 179 /* 180 * PCI stuff, for nodes representing PCI devices, pointed to 181 * by device_node->data. 182 */ 183 struct iommu_table; 184 185 struct pci_dn { 186 int flags; 187 #define PCI_DN_FLAG_IOV_VF 0x01 188 189 int busno; /* pci bus number */ 190 int devfn; /* pci device and function number */ 191 int vendor_id; /* Vendor ID */ 192 int device_id; /* Device ID */ 193 int class_code; /* Device class code */ 194 195 struct pci_dn *parent; 196 struct pci_controller *phb; /* for pci devices */ 197 struct iommu_table_group *table_group; /* for phb's or bridges */ 198 199 int pci_ext_config_space; /* for pci devices */ 200 201 struct pci_dev *pcidev; /* back-pointer to the pci device */ 202 #ifdef CONFIG_EEH 203 struct eeh_dev *edev; /* eeh device */ 204 #endif 205 #define IODA_INVALID_PE 0xFFFFFFFF 206 #ifdef CONFIG_PPC_POWERNV 207 unsigned int pe_number; 208 int vf_index; /* VF index in the PF */ 209 #ifdef CONFIG_PCI_IOV 210 u16 vfs_expanded; /* number of VFs IOV BAR expanded */ 211 u16 num_vfs; /* number of VFs enabled*/ 212 unsigned int *pe_num_map; /* PE# for the first VF PE or array */ 213 bool m64_single_mode; /* Use M64 BAR in Single Mode */ 214 #define IODA_INVALID_M64 (-1) 215 int (*m64_map)[PCI_SRIOV_NUM_BARS]; 216 #endif /* CONFIG_PCI_IOV */ 217 int mps; /* Maximum Payload Size */ 218 #endif 219 struct list_head child_list; 220 struct list_head list; 221 }; 222 223 /* Get the pointer to a device_node's pci_dn */ 224 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 225 226 extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, 227 int devfn); 228 extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); 229 extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev); 230 extern void remove_dev_pci_data(struct pci_dev *pdev); 231 extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose, 232 struct device_node *dn); 233 extern void pci_remove_device_node_info(struct device_node *dn); 234 235 static inline int pci_device_from_OF_node(struct device_node *np, 236 u8 *bus, u8 *devfn) 237 { 238 if (!PCI_DN(np)) 239 return -ENODEV; 240 *bus = PCI_DN(np)->busno; 241 *devfn = PCI_DN(np)->devfn; 242 return 0; 243 } 244 245 #if defined(CONFIG_EEH) 246 static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) 247 { 248 return pdn ? pdn->edev : NULL; 249 } 250 #else 251 #define pdn_to_eeh_dev(x) (NULL) 252 #endif 253 254 /** Find the bus corresponding to the indicated device node */ 255 extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn); 256 257 /** Remove all of the PCI devices under this bus */ 258 extern void pci_hp_remove_devices(struct pci_bus *bus); 259 260 /** Discover new pci devices under this bus, and add them */ 261 extern void pci_hp_add_devices(struct pci_bus *bus); 262 263 extern int pcibios_unmap_io_space(struct pci_bus *bus); 264 extern int pcibios_map_io_space(struct pci_bus *bus); 265 266 #ifdef CONFIG_NUMA 267 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 268 #else 269 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 270 #endif 271 272 #endif /* CONFIG_PPC64 */ 273 274 /* Get the PCI host controller for an OF device */ 275 extern struct pci_controller *pci_find_hose_for_OF_device( 276 struct device_node* node); 277 278 /* Fill up host controller resources from the OF node */ 279 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 280 struct device_node *dev, int primary); 281 282 /* Allocate & free a PCI host bridge structure */ 283 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 284 extern void pcibios_free_controller(struct pci_controller *phb); 285 extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge); 286 287 #ifdef CONFIG_PCI 288 extern int pcibios_vaddr_is_ioport(void __iomem *address); 289 #else 290 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 291 { 292 return 0; 293 } 294 #endif /* CONFIG_PCI */ 295 296 #endif /* __KERNEL__ */ 297 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 298