1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2 #define _ASM_POWERPC_PCI_BRIDGE_H 3 #ifdef __KERNEL__ 4 /* 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/ioport.h> 13 14 struct device_node; 15 16 enum { 17 /* Force re-assigning all resources (ignore firmware 18 * setup completely) 19 */ 20 PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001, 21 22 /* Re-assign all bus numbers */ 23 PPC_PCI_REASSIGN_ALL_BUS = 0x00000002, 24 25 /* Do not try to assign, just use existing setup */ 26 PPC_PCI_PROBE_ONLY = 0x00000004, 27 28 /* Don't bother with ISA alignment unless the bridge has 29 * ISA forwarding enabled 30 */ 31 PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, 32 33 /* Enable domain numbers in /proc */ 34 PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010, 35 /* ... except for domain 0 */ 36 PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020, 37 }; 38 #ifdef CONFIG_PCI 39 extern unsigned int ppc_pci_flags; 40 41 static inline void ppc_pci_set_flags(int flags) 42 { 43 ppc_pci_flags = flags; 44 } 45 46 static inline void ppc_pci_add_flags(int flags) 47 { 48 ppc_pci_flags |= flags; 49 } 50 51 static inline int ppc_pci_has_flag(int flag) 52 { 53 return (ppc_pci_flags & flag); 54 } 55 #else 56 static inline void ppc_pci_set_flags(int flags) { } 57 static inline void ppc_pci_add_flags(int flags) { } 58 static inline int ppc_pci_has_flag(int flag) 59 { 60 return 0; 61 } 62 #endif 63 64 65 /* 66 * Structure of a PCI controller (host bridge) 67 */ 68 struct pci_controller { 69 struct pci_bus *bus; 70 char is_dynamic; 71 #ifdef CONFIG_PPC64 72 int node; 73 #endif 74 struct device_node *dn; 75 struct list_head list_node; 76 struct device *parent; 77 78 int first_busno; 79 int last_busno; 80 int self_busno; 81 82 void __iomem *io_base_virt; 83 #ifdef CONFIG_PPC64 84 void *io_base_alloc; 85 #endif 86 resource_size_t io_base_phys; 87 resource_size_t pci_io_size; 88 89 /* Some machines (PReP) have a non 1:1 mapping of 90 * the PCI memory space in the CPU bus space 91 */ 92 resource_size_t pci_mem_offset; 93 94 /* Some machines have a special region to forward the ISA 95 * "memory" cycles such as VGA memory regions. Left to 0 96 * if unsupported 97 */ 98 resource_size_t isa_mem_phys; 99 resource_size_t isa_mem_size; 100 101 struct pci_ops *ops; 102 unsigned int __iomem *cfg_addr; 103 void __iomem *cfg_data; 104 105 /* 106 * Used for variants of PCI indirect handling and possible quirks: 107 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 108 * EXT_REG - provides access to PCI-e extended registers 109 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS 110 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 111 * to determine which bus number to match on when generating type0 112 * config cycles 113 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 114 * hanging if we don't have link and try to do config cycles to 115 * anything but the PHB. Only allow talking to the PHB if this is 116 * set. 117 * BIG_ENDIAN - cfg_addr is a big endian register 118 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 119 * the PLB4. Effectively disable MRM commands by setting this. 120 */ 121 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 122 #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 123 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 124 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 125 #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 126 #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 127 u32 indirect_type; 128 /* Currently, we limit ourselves to 1 IO range and 3 mem 129 * ranges since the common pci_bus structure can't handle more 130 */ 131 struct resource io_resource; 132 struct resource mem_resources[3]; 133 int global_number; /* PCI domain number */ 134 135 resource_size_t dma_window_base_cur; 136 resource_size_t dma_window_size; 137 138 #ifdef CONFIG_PPC64 139 unsigned long buid; 140 141 void *private_data; 142 #endif /* CONFIG_PPC64 */ 143 }; 144 145 /* These are used for config access before all the PCI probing 146 has been done. */ 147 extern int early_read_config_byte(struct pci_controller *hose, int bus, 148 int dev_fn, int where, u8 *val); 149 extern int early_read_config_word(struct pci_controller *hose, int bus, 150 int dev_fn, int where, u16 *val); 151 extern int early_read_config_dword(struct pci_controller *hose, int bus, 152 int dev_fn, int where, u32 *val); 153 extern int early_write_config_byte(struct pci_controller *hose, int bus, 154 int dev_fn, int where, u8 val); 155 extern int early_write_config_word(struct pci_controller *hose, int bus, 156 int dev_fn, int where, u16 val); 157 extern int early_write_config_dword(struct pci_controller *hose, int bus, 158 int dev_fn, int where, u32 val); 159 160 extern int early_find_capability(struct pci_controller *hose, int bus, 161 int dev_fn, int cap); 162 163 extern void setup_indirect_pci(struct pci_controller* hose, 164 resource_size_t cfg_addr, 165 resource_size_t cfg_data, u32 flags); 166 167 static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 168 { 169 return bus->sysdata; 170 } 171 172 #ifndef CONFIG_PPC64 173 174 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 175 { 176 struct pci_controller *host; 177 178 if (bus->self) 179 return pci_device_to_OF_node(bus->self); 180 host = pci_bus_to_host(bus); 181 return host ? host->dn : NULL; 182 } 183 184 static inline int isa_vaddr_is_ioport(void __iomem *address) 185 { 186 /* No specific ISA handling on ppc32 at this stage, it 187 * all goes through PCI 188 */ 189 return 0; 190 } 191 192 #else /* CONFIG_PPC64 */ 193 194 /* 195 * PCI stuff, for nodes representing PCI devices, pointed to 196 * by device_node->data. 197 */ 198 struct iommu_table; 199 200 struct pci_dn { 201 int busno; /* pci bus number */ 202 int devfn; /* pci device and function number */ 203 204 struct pci_controller *phb; /* for pci devices */ 205 struct iommu_table *iommu_table; /* for phb's or bridges */ 206 struct device_node *node; /* back-pointer to the device_node */ 207 208 int pci_ext_config_space; /* for pci devices */ 209 210 #ifdef CONFIG_EEH 211 struct pci_dev *pcidev; /* back-pointer to the pci device */ 212 int class_code; /* pci device class */ 213 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 214 int eeh_config_addr; 215 int eeh_pe_config_addr; /* new-style partition endpoint address */ 216 int eeh_check_count; /* # times driver ignored error */ 217 int eeh_freeze_count; /* # times this device froze up. */ 218 int eeh_false_positives; /* # times this device reported #ff's */ 219 u32 config_space[16]; /* saved PCI config space */ 220 #endif 221 }; 222 223 /* Get the pointer to a device_node's pci_dn */ 224 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 225 226 extern struct device_node *fetch_dev_dn(struct pci_dev *dev); 227 extern void * update_dn_pci_info(struct device_node *dn, void *data); 228 229 /* Get a device_node from a pci_dev. This code must be fast except 230 * in the case where the sysdata is incorrect and needs to be fixed 231 * up (this will only happen once). */ 232 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev) 233 { 234 return dev->dev.of_node ? dev->dev.of_node : fetch_dev_dn(dev); 235 } 236 237 static inline int pci_device_from_OF_node(struct device_node *np, 238 u8 *bus, u8 *devfn) 239 { 240 if (!PCI_DN(np)) 241 return -ENODEV; 242 *bus = PCI_DN(np)->busno; 243 *devfn = PCI_DN(np)->devfn; 244 return 0; 245 } 246 247 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 248 { 249 if (bus->self) 250 return pci_device_to_OF_node(bus->self); 251 else 252 return bus->dev.of_node; /* Must be root bus (PHB) */ 253 } 254 255 /** Find the bus corresponding to the indicated device node */ 256 extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); 257 258 /** Remove all of the PCI devices under this bus */ 259 extern void pcibios_remove_pci_devices(struct pci_bus *bus); 260 261 /** Discover new pci devices under this bus, and add them */ 262 extern void pcibios_add_pci_devices(struct pci_bus *bus); 263 264 265 extern void isa_bridge_find_early(struct pci_controller *hose); 266 267 static inline int isa_vaddr_is_ioport(void __iomem *address) 268 { 269 /* Check if address hits the reserved legacy IO range */ 270 unsigned long ea = (unsigned long)address; 271 return ea >= ISA_IO_BASE && ea < ISA_IO_END; 272 } 273 274 extern int pcibios_unmap_io_space(struct pci_bus *bus); 275 extern int pcibios_map_io_space(struct pci_bus *bus); 276 277 #ifdef CONFIG_NUMA 278 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 279 #else 280 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 281 #endif 282 283 #endif /* CONFIG_PPC64 */ 284 285 /* Get the PCI host controller for an OF device */ 286 extern struct pci_controller *pci_find_hose_for_OF_device( 287 struct device_node* node); 288 289 /* Fill up host controller resources from the OF node */ 290 extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 291 struct device_node *dev, int primary); 292 293 /* Allocate & free a PCI host bridge structure */ 294 extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 295 extern void pcibios_free_controller(struct pci_controller *phb); 296 extern void pcibios_setup_phb_resources(struct pci_controller *hose); 297 298 #ifdef CONFIG_PCI 299 extern int pcibios_vaddr_is_ioport(void __iomem *address); 300 #else 301 static inline int pcibios_vaddr_is_ioport(void __iomem *address) 302 { 303 return 0; 304 } 305 #endif /* CONFIG_PCI */ 306 307 #endif /* __KERNEL__ */ 308 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 309