1b8b572e1SStephen Rothwell #ifndef _ASM_POWERPC_PCI_BRIDGE_H 2b8b572e1SStephen Rothwell #define _ASM_POWERPC_PCI_BRIDGE_H 3b8b572e1SStephen Rothwell #ifdef __KERNEL__ 4b8b572e1SStephen Rothwell /* 5b8b572e1SStephen Rothwell * This program is free software; you can redistribute it and/or 6b8b572e1SStephen Rothwell * modify it under the terms of the GNU General Public License 7b8b572e1SStephen Rothwell * as published by the Free Software Foundation; either version 8b8b572e1SStephen Rothwell * 2 of the License, or (at your option) any later version. 9b8b572e1SStephen Rothwell */ 10b8b572e1SStephen Rothwell #include <linux/pci.h> 11b8b572e1SStephen Rothwell #include <linux/list.h> 12b8b572e1SStephen Rothwell #include <linux/ioport.h> 13f4ffd5e5SRob Herring #include <asm-generic/pci-bridge.h> 14b8b572e1SStephen Rothwell 15ff9df8c8SDaniel Axtens /* Return values for pci_controller_ops.probe_mode function */ 16ff9df8c8SDaniel Axtens #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ 17ff9df8c8SDaniel Axtens #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ 18ff9df8c8SDaniel Axtens #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ 19ff9df8c8SDaniel Axtens 20b8b572e1SStephen Rothwell struct device_node; 21b8b572e1SStephen Rothwell 22b8b572e1SStephen Rothwell /* 23e02def5bSDaniel Axtens * PCI controller operations 24e02def5bSDaniel Axtens */ 25e02def5bSDaniel Axtens struct pci_controller_ops { 26e02def5bSDaniel Axtens void (*dma_dev_setup)(struct pci_dev *dev); 27b122c954SDaniel Axtens void (*dma_bus_setup)(struct pci_bus *bus); 28ff9df8c8SDaniel Axtens 29ff9df8c8SDaniel Axtens int (*probe_mode)(struct pci_bus *); 30e02def5bSDaniel Axtens }; 31e02def5bSDaniel Axtens 32e02def5bSDaniel Axtens /* 33b8b572e1SStephen Rothwell * Structure of a PCI controller (host bridge) 34b8b572e1SStephen Rothwell */ 35b8b572e1SStephen Rothwell struct pci_controller { 36b8b572e1SStephen Rothwell struct pci_bus *bus; 37b8b572e1SStephen Rothwell char is_dynamic; 38b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 39b8b572e1SStephen Rothwell int node; 40b8b572e1SStephen Rothwell #endif 41b8b572e1SStephen Rothwell struct device_node *dn; 42b8b572e1SStephen Rothwell struct list_head list_node; 43b8b572e1SStephen Rothwell struct device *parent; 44b8b572e1SStephen Rothwell 45b8b572e1SStephen Rothwell int first_busno; 46b8b572e1SStephen Rothwell int last_busno; 47b8b572e1SStephen Rothwell int self_busno; 48be8e60d8SYinghai Lu struct resource busn; 49b8b572e1SStephen Rothwell 50b8b572e1SStephen Rothwell void __iomem *io_base_virt; 51b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 52b8b572e1SStephen Rothwell void *io_base_alloc; 53b8b572e1SStephen Rothwell #endif 54b8b572e1SStephen Rothwell resource_size_t io_base_phys; 55b8b572e1SStephen Rothwell resource_size_t pci_io_size; 56b8b572e1SStephen Rothwell 57e9f82cb7SBenjamin Herrenschmidt /* Some machines have a special region to forward the ISA 58e9f82cb7SBenjamin Herrenschmidt * "memory" cycles such as VGA memory regions. Left to 0 59e9f82cb7SBenjamin Herrenschmidt * if unsupported 60e9f82cb7SBenjamin Herrenschmidt */ 61e9f82cb7SBenjamin Herrenschmidt resource_size_t isa_mem_phys; 62e9f82cb7SBenjamin Herrenschmidt resource_size_t isa_mem_size; 63e9f82cb7SBenjamin Herrenschmidt 64e02def5bSDaniel Axtens struct pci_controller_ops controller_ops; 65b8b572e1SStephen Rothwell struct pci_ops *ops; 66b8b572e1SStephen Rothwell unsigned int __iomem *cfg_addr; 67b8b572e1SStephen Rothwell void __iomem *cfg_data; 68b8b572e1SStephen Rothwell 69b8b572e1SStephen Rothwell /* 70b8b572e1SStephen Rothwell * Used for variants of PCI indirect handling and possible quirks: 71b8b572e1SStephen Rothwell * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 72b8b572e1SStephen Rothwell * EXT_REG - provides access to PCI-e extended registers 7325985edcSLucas De Marchi * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS 74b8b572e1SStephen Rothwell * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 75b8b572e1SStephen Rothwell * to determine which bus number to match on when generating type0 76b8b572e1SStephen Rothwell * config cycles 77b8b572e1SStephen Rothwell * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with 78b8b572e1SStephen Rothwell * hanging if we don't have link and try to do config cycles to 79b8b572e1SStephen Rothwell * anything but the PHB. Only allow talking to the PHB if this is 80b8b572e1SStephen Rothwell * set. 81b8b572e1SStephen Rothwell * BIG_ENDIAN - cfg_addr is a big endian register 82b8b572e1SStephen Rothwell * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 83b8b572e1SStephen Rothwell * the PLB4. Effectively disable MRM commands by setting this. 8434642bbbSKumar Gala * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe 8534642bbbSKumar Gala * link status is in a RC PCIe cfg register (vs being a SoC register) 86b8b572e1SStephen Rothwell */ 87b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 88b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 89b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 90b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 91b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 92b8b572e1SStephen Rothwell #define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 9334642bbbSKumar Gala #define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040 94b8b572e1SStephen Rothwell u32 indirect_type; 95b8b572e1SStephen Rothwell /* Currently, we limit ourselves to 1 IO range and 3 mem 96b8b572e1SStephen Rothwell * ranges since the common pci_bus structure can't handle more 97b8b572e1SStephen Rothwell */ 98b8b572e1SStephen Rothwell struct resource io_resource; 99b8b572e1SStephen Rothwell struct resource mem_resources[3]; 1003fd47f06SBenjamin Herrenschmidt resource_size_t mem_offset[3]; 101b8b572e1SStephen Rothwell int global_number; /* PCI domain number */ 10289d93347SBecky Bruce 10389d93347SBecky Bruce resource_size_t dma_window_base_cur; 10489d93347SBecky Bruce resource_size_t dma_window_size; 10589d93347SBecky Bruce 106b8b572e1SStephen Rothwell #ifdef CONFIG_PPC64 107b8b572e1SStephen Rothwell unsigned long buid; 108cca87d30SGavin Shan struct pci_dn *pci_data; 10934642bbbSKumar Gala #endif /* CONFIG_PPC64 */ 110b8b572e1SStephen Rothwell 111b8b572e1SStephen Rothwell void *private_data; 112b8b572e1SStephen Rothwell }; 113b8b572e1SStephen Rothwell 114b8b572e1SStephen Rothwell /* These are used for config access before all the PCI probing 115b8b572e1SStephen Rothwell has been done. */ 116b8b572e1SStephen Rothwell extern int early_read_config_byte(struct pci_controller *hose, int bus, 117b8b572e1SStephen Rothwell int dev_fn, int where, u8 *val); 118b8b572e1SStephen Rothwell extern int early_read_config_word(struct pci_controller *hose, int bus, 119b8b572e1SStephen Rothwell int dev_fn, int where, u16 *val); 120b8b572e1SStephen Rothwell extern int early_read_config_dword(struct pci_controller *hose, int bus, 121b8b572e1SStephen Rothwell int dev_fn, int where, u32 *val); 122b8b572e1SStephen Rothwell extern int early_write_config_byte(struct pci_controller *hose, int bus, 123b8b572e1SStephen Rothwell int dev_fn, int where, u8 val); 124b8b572e1SStephen Rothwell extern int early_write_config_word(struct pci_controller *hose, int bus, 125b8b572e1SStephen Rothwell int dev_fn, int where, u16 val); 126b8b572e1SStephen Rothwell extern int early_write_config_dword(struct pci_controller *hose, int bus, 127b8b572e1SStephen Rothwell int dev_fn, int where, u32 val); 128b8b572e1SStephen Rothwell 129b8b572e1SStephen Rothwell extern int early_find_capability(struct pci_controller *hose, int bus, 130b8b572e1SStephen Rothwell int dev_fn, int cap); 131b8b572e1SStephen Rothwell 132b8b572e1SStephen Rothwell extern void setup_indirect_pci(struct pci_controller* hose, 133b8b572e1SStephen Rothwell resource_size_t cfg_addr, 134b8b572e1SStephen Rothwell resource_size_t cfg_data, u32 flags); 13589c2dd62SKumar Gala 13650d8f87dSRojhalat Ibrahim extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn, 13750d8f87dSRojhalat Ibrahim int offset, int len, u32 *val); 13850d8f87dSRojhalat Ibrahim 1396d5f6a0eSKim Phillips extern int __indirect_read_config(struct pci_controller *hose, 1406d5f6a0eSKim Phillips unsigned char bus_number, unsigned int devfn, 1416d5f6a0eSKim Phillips int offset, int len, u32 *val); 1426d5f6a0eSKim Phillips 14350d8f87dSRojhalat Ibrahim extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn, 14450d8f87dSRojhalat Ibrahim int offset, int len, u32 val); 14550d8f87dSRojhalat Ibrahim 14689c2dd62SKumar Gala static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 14789c2dd62SKumar Gala { 14889c2dd62SKumar Gala return bus->sysdata; 14989c2dd62SKumar Gala } 15089c2dd62SKumar Gala 15198d9f30cSBenjamin Herrenschmidt #ifndef CONFIG_PPC64 15298d9f30cSBenjamin Herrenschmidt 15398d9f30cSBenjamin Herrenschmidt extern int pci_device_from_OF_node(struct device_node *node, 15498d9f30cSBenjamin Herrenschmidt u8 *bus, u8 *devfn); 15598d9f30cSBenjamin Herrenschmidt extern void pci_create_OF_bus_map(void); 15698d9f30cSBenjamin Herrenschmidt 15789c2dd62SKumar Gala static inline int isa_vaddr_is_ioport(void __iomem *address) 15889c2dd62SKumar Gala { 15989c2dd62SKumar Gala /* No specific ISA handling on ppc32 at this stage, it 16089c2dd62SKumar Gala * all goes through PCI 16189c2dd62SKumar Gala */ 16289c2dd62SKumar Gala return 0; 16389c2dd62SKumar Gala } 16489c2dd62SKumar Gala 165b8b572e1SStephen Rothwell #else /* CONFIG_PPC64 */ 166b8b572e1SStephen Rothwell 167b8b572e1SStephen Rothwell /* 168b8b572e1SStephen Rothwell * PCI stuff, for nodes representing PCI devices, pointed to 169b8b572e1SStephen Rothwell * by device_node->data. 170b8b572e1SStephen Rothwell */ 171b8b572e1SStephen Rothwell struct iommu_table; 172b8b572e1SStephen Rothwell 173b8b572e1SStephen Rothwell struct pci_dn { 174cca87d30SGavin Shan int flags; 175cca87d30SGavin Shan 176b8b572e1SStephen Rothwell int busno; /* pci bus number */ 177b8b572e1SStephen Rothwell int devfn; /* pci device and function number */ 178c035ff1dSGavin Shan int vendor_id; /* Vendor ID */ 179c035ff1dSGavin Shan int device_id; /* Device ID */ 180c035ff1dSGavin Shan int class_code; /* Device class code */ 181b8b572e1SStephen Rothwell 182cca87d30SGavin Shan struct pci_dn *parent; 183b8b572e1SStephen Rothwell struct pci_controller *phb; /* for pci devices */ 184b8b572e1SStephen Rothwell struct iommu_table *iommu_table; /* for phb's or bridges */ 185b8b572e1SStephen Rothwell struct device_node *node; /* back-pointer to the device_node */ 186b8b572e1SStephen Rothwell 187b8b572e1SStephen Rothwell int pci_ext_config_space; /* for pci devices */ 188b8b572e1SStephen Rothwell 189b8b572e1SStephen Rothwell struct pci_dev *pcidev; /* back-pointer to the pci device */ 190184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_EEH 1912a0352faSGavin Shan struct eeh_dev *edev; /* eeh device */ 192b8b572e1SStephen Rothwell #endif 193184cd4a3SBenjamin Herrenschmidt #define IODA_INVALID_PE (-1) 194184cd4a3SBenjamin Herrenschmidt #ifdef CONFIG_PPC_POWERNV 195184cd4a3SBenjamin Herrenschmidt int pe_number; 196184cd4a3SBenjamin Herrenschmidt #endif 197cca87d30SGavin Shan struct list_head child_list; 198cca87d30SGavin Shan struct list_head list; 199b8b572e1SStephen Rothwell }; 200b8b572e1SStephen Rothwell 201b8b572e1SStephen Rothwell /* Get the pointer to a device_node's pci_dn */ 202b8b572e1SStephen Rothwell #define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 203b8b572e1SStephen Rothwell 204cca87d30SGavin Shan extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus, 205cca87d30SGavin Shan int devfn); 206b72c1f65SBenjamin Herrenschmidt extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); 2072eb4afb6SKumar Gala extern void *update_dn_pci_info(struct device_node *dn, void *data); 208b8b572e1SStephen Rothwell 209b8b572e1SStephen Rothwell static inline int pci_device_from_OF_node(struct device_node *np, 210b8b572e1SStephen Rothwell u8 *bus, u8 *devfn) 211b8b572e1SStephen Rothwell { 212b8b572e1SStephen Rothwell if (!PCI_DN(np)) 213b8b572e1SStephen Rothwell return -ENODEV; 214b8b572e1SStephen Rothwell *bus = PCI_DN(np)->busno; 215b8b572e1SStephen Rothwell *devfn = PCI_DN(np)->devfn; 216b8b572e1SStephen Rothwell return 0; 217b8b572e1SStephen Rothwell } 218b8b572e1SStephen Rothwell 2192a0352faSGavin Shan #if defined(CONFIG_EEH) 220e8e9b34cSGavin Shan static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn) 221e8e9b34cSGavin Shan { 222e8e9b34cSGavin Shan return pdn ? pdn->edev : NULL; 223e8e9b34cSGavin Shan } 224f8f7d63fSGavin Shan #else 225e8e9b34cSGavin Shan #define pdn_to_eeh_dev(x) (NULL) 2262a0352faSGavin Shan #endif 2272a0352faSGavin Shan 228b8b572e1SStephen Rothwell /** Find the bus corresponding to the indicated device node */ 229b8b572e1SStephen Rothwell extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn); 230b8b572e1SStephen Rothwell 231b8b572e1SStephen Rothwell /** Remove all of the PCI devices under this bus */ 232b8b572e1SStephen Rothwell extern void pcibios_remove_pci_devices(struct pci_bus *bus); 233b8b572e1SStephen Rothwell 234b8b572e1SStephen Rothwell /** Discover new pci devices under this bus, and add them */ 235b8b572e1SStephen Rothwell extern void pcibios_add_pci_devices(struct pci_bus *bus); 236b8b572e1SStephen Rothwell 237b8b572e1SStephen Rothwell 238b8b572e1SStephen Rothwell extern void isa_bridge_find_early(struct pci_controller *hose); 239b8b572e1SStephen Rothwell 240b8b572e1SStephen Rothwell static inline int isa_vaddr_is_ioport(void __iomem *address) 241b8b572e1SStephen Rothwell { 242b8b572e1SStephen Rothwell /* Check if address hits the reserved legacy IO range */ 243b8b572e1SStephen Rothwell unsigned long ea = (unsigned long)address; 244b8b572e1SStephen Rothwell return ea >= ISA_IO_BASE && ea < ISA_IO_END; 245b8b572e1SStephen Rothwell } 246b8b572e1SStephen Rothwell 247b8b572e1SStephen Rothwell extern int pcibios_unmap_io_space(struct pci_bus *bus); 248b8b572e1SStephen Rothwell extern int pcibios_map_io_space(struct pci_bus *bus); 249b8b572e1SStephen Rothwell 250b8b572e1SStephen Rothwell #ifdef CONFIG_NUMA 251b8b572e1SStephen Rothwell #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE)) 252b8b572e1SStephen Rothwell #else 253b8b572e1SStephen Rothwell #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1) 254b8b572e1SStephen Rothwell #endif 255b8b572e1SStephen Rothwell 256b8b572e1SStephen Rothwell #endif /* CONFIG_PPC64 */ 257b8b572e1SStephen Rothwell 258b8b572e1SStephen Rothwell /* Get the PCI host controller for an OF device */ 259b8b572e1SStephen Rothwell extern struct pci_controller *pci_find_hose_for_OF_device( 260b8b572e1SStephen Rothwell struct device_node* node); 261b8b572e1SStephen Rothwell 262b8b572e1SStephen Rothwell /* Fill up host controller resources from the OF node */ 263b8b572e1SStephen Rothwell extern void pci_process_bridge_OF_ranges(struct pci_controller *hose, 264b8b572e1SStephen Rothwell struct device_node *dev, int primary); 265b8b572e1SStephen Rothwell 266b8b572e1SStephen Rothwell /* Allocate & free a PCI host bridge structure */ 267b8b572e1SStephen Rothwell extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev); 268b8b572e1SStephen Rothwell extern void pcibios_free_controller(struct pci_controller *phb); 269b8b572e1SStephen Rothwell 270b8b572e1SStephen Rothwell #ifdef CONFIG_PCI 271b8b572e1SStephen Rothwell extern int pcibios_vaddr_is_ioport(void __iomem *address); 272b8b572e1SStephen Rothwell #else 273b8b572e1SStephen Rothwell static inline int pcibios_vaddr_is_ioport(void __iomem *address) 274b8b572e1SStephen Rothwell { 275b8b572e1SStephen Rothwell return 0; 276b8b572e1SStephen Rothwell } 277b8b572e1SStephen Rothwell #endif /* CONFIG_PCI */ 278b8b572e1SStephen Rothwell 279e02def5bSDaniel Axtens /* 280e02def5bSDaniel Axtens * Shims to prefer pci_controller version over ppc_md where available. 281e02def5bSDaniel Axtens */ 282e02def5bSDaniel Axtens static inline void pci_dma_dev_setup(struct pci_dev *dev) 283e02def5bSDaniel Axtens { 284e02def5bSDaniel Axtens struct pci_controller *phb = pci_bus_to_host(dev->bus); 285e02def5bSDaniel Axtens 286e02def5bSDaniel Axtens if (phb->controller_ops.dma_dev_setup) 287e02def5bSDaniel Axtens phb->controller_ops.dma_dev_setup(dev); 288e02def5bSDaniel Axtens else if (ppc_md.pci_dma_dev_setup) 289e02def5bSDaniel Axtens ppc_md.pci_dma_dev_setup(dev); 290e02def5bSDaniel Axtens } 291e02def5bSDaniel Axtens 292b122c954SDaniel Axtens static inline void pci_dma_bus_setup(struct pci_bus *bus) 293b122c954SDaniel Axtens { 294b122c954SDaniel Axtens struct pci_controller *phb = pci_bus_to_host(bus); 295b122c954SDaniel Axtens 296b122c954SDaniel Axtens if (phb->controller_ops.dma_bus_setup) 297b122c954SDaniel Axtens phb->controller_ops.dma_bus_setup(bus); 298b122c954SDaniel Axtens else if (ppc_md.pci_dma_bus_setup) 299b122c954SDaniel Axtens ppc_md.pci_dma_bus_setup(bus); 300b122c954SDaniel Axtens } 301b122c954SDaniel Axtens 302ff9df8c8SDaniel Axtens static inline int pci_probe_mode(struct pci_bus *bus) 303ff9df8c8SDaniel Axtens { 304ff9df8c8SDaniel Axtens struct pci_controller *phb = pci_bus_to_host(bus); 305ff9df8c8SDaniel Axtens 306ff9df8c8SDaniel Axtens if (phb->controller_ops.probe_mode) 307ff9df8c8SDaniel Axtens return phb->controller_ops.probe_mode(bus); 308ff9df8c8SDaniel Axtens if (ppc_md.pci_probe_mode) 309ff9df8c8SDaniel Axtens return ppc_md.pci_probe_mode(bus); 310ff9df8c8SDaniel Axtens return PCI_PROBE_NORMAL; 311ff9df8c8SDaniel Axtens } 312ff9df8c8SDaniel Axtens 313b8b572e1SStephen Rothwell #endif /* __KERNEL__ */ 314b8b572e1SStephen Rothwell #endif /* _ASM_POWERPC_PCI_BRIDGE_H */ 315