1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * This control block defines the PACA which defines the processor 4 * specific data for each logical processor on the system. 5 * There are some pointers defined that are utilized by PLIC. 6 * 7 * C 2001 PPC 64 Team, IBM Corp 8 */ 9 #ifndef _ASM_POWERPC_PACA_H 10 #define _ASM_POWERPC_PACA_H 11 #ifdef __KERNEL__ 12 13 #ifdef CONFIG_PPC64 14 15 #include <linux/cache.h> 16 #include <linux/string.h> 17 #include <asm/types.h> 18 #include <asm/lppaca.h> 19 #include <asm/mmu.h> 20 #include <asm/page.h> 21 #ifdef CONFIG_PPC_BOOK3E_64 22 #include <asm/exception-64e.h> 23 #else 24 #include <asm/exception-64s.h> 25 #endif 26 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 27 #include <asm/kvm_book3s_asm.h> 28 #endif 29 #include <asm/accounting.h> 30 #include <asm/hmi.h> 31 #include <asm/cpuidle.h> 32 #include <asm/atomic.h> 33 #include <asm/mce.h> 34 35 #include <asm-generic/mmiowb_types.h> 36 37 register struct paca_struct *local_paca asm("r13"); 38 39 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP) 40 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */ 41 /* 42 * Add standard checks that preemption cannot occur when using get_paca(): 43 * otherwise the paca_struct it points to may be the wrong one just after. 44 */ 45 #define get_paca() ((void) debug_smp_processor_id(), local_paca) 46 #else 47 #define get_paca() local_paca 48 #endif 49 50 #ifdef CONFIG_PPC_PSERIES 51 #define get_lppaca() (get_paca()->lppaca_ptr) 52 #endif 53 54 #define get_slb_shadow() (get_paca()->slb_shadow_ptr) 55 56 struct task_struct; 57 struct rtas_args; 58 59 /* 60 * Defines the layout of the paca. 61 * 62 * This structure is not directly accessed by firmware or the service 63 * processor. 64 */ 65 struct paca_struct { 66 #ifdef CONFIG_PPC_PSERIES 67 /* 68 * Because hw_cpu_id, unlike other paca fields, is accessed 69 * routinely from other CPUs (from the IRQ code), we stick to 70 * read-only (after boot) fields in the first cacheline to 71 * avoid cacheline bouncing. 72 */ 73 74 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ 75 #endif /* CONFIG_PPC_PSERIES */ 76 77 /* 78 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 79 * load lock_token and paca_index with a single lwz 80 * instruction. They must travel together and be properly 81 * aligned. 82 */ 83 #ifdef __BIG_ENDIAN__ 84 u16 lock_token; /* Constant 0x8000, used in locks */ 85 u16 paca_index; /* Logical processor number */ 86 #else 87 u16 paca_index; /* Logical processor number */ 88 u16 lock_token; /* Constant 0x8000, used in locks */ 89 #endif 90 91 #ifndef CONFIG_PPC_KERNEL_PCREL 92 u64 kernel_toc; /* Kernel TOC address */ 93 #endif 94 u64 kernelbase; /* Base address of kernel */ 95 u64 kernel_msr; /* MSR while running in kernel */ 96 void *emergency_sp; /* pointer to emergency stack */ 97 u64 data_offset; /* per cpu data offset */ 98 s16 hw_cpu_id; /* Physical processor number */ 99 u8 cpu_start; /* At startup, processor spins until */ 100 /* this becomes non-zero. */ 101 u8 kexec_state; /* set when kexec down has irqs off */ 102 #ifdef CONFIG_PPC_BOOK3S_64 103 #ifdef CONFIG_PPC_64S_HASH_MMU 104 struct slb_shadow *slb_shadow_ptr; 105 #endif 106 struct dtl_entry *dispatch_log; 107 struct dtl_entry *dispatch_log_end; 108 #endif 109 u64 dscr_default; /* per-CPU default DSCR */ 110 111 #ifdef CONFIG_PPC_BOOK3S_64 112 /* 113 * Now, starting in cacheline 2, the exception save areas 114 */ 115 /* used for most interrupts/exceptions */ 116 u64 exgen[EX_SIZE] __attribute__((aligned(0x80))); 117 118 #ifdef CONFIG_PPC_64S_HASH_MMU 119 /* SLB related definitions */ 120 u16 vmalloc_sllp; 121 u8 slb_cache_ptr; 122 u8 stab_rr; /* stab/slb round-robin counter */ 123 #ifdef CONFIG_DEBUG_VM 124 u8 in_kernel_slb_handler; 125 #endif 126 u32 slb_used_bitmap; /* Bitmaps for first 32 SLB entries. */ 127 u32 slb_kern_bitmap; 128 u32 slb_cache[SLB_CACHE_ENTRIES]; 129 #endif 130 #endif /* CONFIG_PPC_BOOK3S_64 */ 131 132 #ifdef CONFIG_PPC_BOOK3E_64 133 u64 exgen[8] __aligned(0x40); 134 /* Keep pgd in the same cacheline as the start of extlb */ 135 pgd_t *pgd __aligned(0x40); /* Current PGD */ 136 pgd_t *kernel_pgd; /* Kernel PGD */ 137 138 /* Shared by all threads of a core -- points to tcd of first thread */ 139 struct tlb_core_data *tcd_ptr; 140 141 /* 142 * We can have up to 3 levels of reentrancy in the TLB miss handler, 143 * in each of four exception levels (normal, crit, mcheck, debug). 144 */ 145 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)]; 146 u64 exmc[8]; /* used for machine checks */ 147 u64 excrit[8]; /* used for crit interrupts */ 148 u64 exdbg[8]; /* used for debug interrupts */ 149 150 /* Kernel stack pointers for use by special exceptions */ 151 void *mc_kstack; 152 void *crit_kstack; 153 void *dbg_kstack; 154 155 struct tlb_core_data tcd; 156 #endif /* CONFIG_PPC_BOOK3E_64 */ 157 158 #ifdef CONFIG_PPC_64S_HASH_MMU 159 unsigned char mm_ctx_low_slices_psize[BITS_PER_LONG / BITS_PER_BYTE]; 160 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE]; 161 #endif 162 163 /* 164 * then miscellaneous read-write fields 165 */ 166 struct task_struct *__current; /* Pointer to current */ 167 u64 kstack; /* Saved Kernel stack addr */ 168 u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */ 169 u64 saved_msr; /* MSR saved here by enter_rtas */ 170 #ifdef CONFIG_PPC64 171 u64 exit_save_r1; /* Syscall/interrupt R1 save */ 172 #endif 173 #ifdef CONFIG_PPC_BOOK3E_64 174 u16 trap_save; /* Used when bad stack is encountered */ 175 #endif 176 #ifdef CONFIG_PPC_BOOK3S_64 177 u8 hsrr_valid; /* HSRRs set for HRFID */ 178 u8 srr_valid; /* SRRs set for RFID */ 179 #endif 180 u8 irq_soft_mask; /* mask for irq soft masking */ 181 u8 irq_happened; /* irq happened while soft-disabled */ 182 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 183 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 184 u8 pmcregs_in_use; /* pseries puts this in lppaca */ 185 #endif 186 u64 sprg_vdso; /* Saved user-visible sprg */ 187 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 188 u64 tm_scratch; /* TM scratch area for reclaim */ 189 #endif 190 191 #ifdef CONFIG_PPC_POWERNV 192 /* PowerNV idle fields */ 193 /* PNV_CORE_IDLE_* bits, all siblings work on thread 0 paca */ 194 unsigned long idle_state; 195 union { 196 /* P7/P8 specific fields */ 197 struct { 198 /* PNV_THREAD_RUNNING/NAP/SLEEP */ 199 u8 thread_idle_state; 200 /* Mask to denote subcore sibling threads */ 201 u8 subcore_sibling_mask; 202 }; 203 204 /* P9 specific fields */ 205 struct { 206 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 207 /* The PSSCR value that the kernel requested before going to stop */ 208 u64 requested_psscr; 209 /* Flag to request this thread not to stop */ 210 atomic_t dont_stop; 211 #endif 212 }; 213 }; 214 #endif 215 216 #ifdef CONFIG_PPC_BOOK3S_64 217 /* Non-maskable exceptions that are not performance critical */ 218 u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */ 219 u64 exmc[EX_SIZE]; /* used for machine checks */ 220 #endif 221 #ifdef CONFIG_PPC_BOOK3S_64 222 /* Exclusive stacks for system reset and machine check exception. */ 223 void *nmi_emergency_sp; 224 void *mc_emergency_sp; 225 226 u16 in_nmi; /* In nmi handler */ 227 228 /* 229 * Flag to check whether we are in machine check early handler 230 * and already using emergency stack. 231 */ 232 u16 in_mce; 233 u8 hmi_event_available; /* HMI event is available */ 234 u8 hmi_p9_special_emu; /* HMI P9 special emulation */ 235 u32 hmi_irqs; /* HMI irq stat */ 236 #endif 237 u8 ftrace_enabled; /* Hard disable ftrace */ 238 239 /* Stuff for accurate time accounting */ 240 struct cpu_accounting_data accounting; 241 u64 dtl_ridx; /* read index in dispatch log */ 242 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */ 243 244 #ifdef CONFIG_KVM_BOOK3S_HANDLER 245 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 246 /* We use this to store guest state in */ 247 struct kvmppc_book3s_shadow_vcpu shadow_vcpu; 248 #endif 249 struct kvmppc_host_state kvm_hstate; 250 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 251 /* 252 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for 253 * more details 254 */ 255 struct sibling_subcore_state *sibling_subcore_state; 256 #endif 257 #endif 258 #ifdef CONFIG_PPC_BOOK3S_64 259 /* 260 * rfi fallback flush must be in its own cacheline to prevent 261 * other paca data leaking into the L1d 262 */ 263 u64 exrfi[EX_SIZE] __aligned(0x80); 264 void *rfi_flush_fallback_area; 265 u64 l1d_flush_size; 266 #endif 267 #ifdef CONFIG_PPC_PSERIES 268 u8 *mce_data_buf; /* buffer to hold per cpu rtas errlog */ 269 #endif /* CONFIG_PPC_PSERIES */ 270 271 #ifdef CONFIG_PPC_BOOK3S_64 272 #ifdef CONFIG_PPC_64S_HASH_MMU 273 /* Capture SLB related old contents in MCE handler. */ 274 struct slb_entry *mce_faulty_slbs; 275 u16 slb_save_cache_ptr; 276 #endif 277 #endif /* CONFIG_PPC_BOOK3S_64 */ 278 #ifdef CONFIG_STACKPROTECTOR 279 unsigned long canary; 280 #endif 281 #ifdef CONFIG_MMIOWB 282 struct mmiowb_state mmiowb_state; 283 #endif 284 #ifdef CONFIG_PPC_BOOK3S_64 285 struct mce_info *mce_info; 286 u8 mce_pending_irq_work; 287 #endif /* CONFIG_PPC_BOOK3S_64 */ 288 } ____cacheline_aligned; 289 290 extern void copy_mm_to_paca(struct mm_struct *mm); 291 extern struct paca_struct **paca_ptrs; 292 extern void initialise_paca(struct paca_struct *new_paca, int cpu); 293 extern void setup_paca(struct paca_struct *new_paca); 294 extern void allocate_paca_ptrs(void); 295 extern void allocate_paca(int cpu); 296 extern void free_unused_pacas(void); 297 298 #else /* CONFIG_PPC64 */ 299 300 static inline void allocate_paca(int cpu) { } 301 static inline void free_unused_pacas(void) { } 302 303 #endif /* CONFIG_PPC64 */ 304 305 #endif /* __KERNEL__ */ 306 #endif /* _ASM_POWERPC_PACA_H */ 307