1 /* 2 * This control block defines the PACA which defines the processor 3 * specific data for each logical processor on the system. 4 * There are some pointers defined that are utilized by PLIC. 5 * 6 * C 2001 PPC 64 Team, IBM Corp 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 #ifndef _ASM_POWERPC_PACA_H 14 #define _ASM_POWERPC_PACA_H 15 #ifdef __KERNEL__ 16 17 #ifdef CONFIG_PPC64 18 19 #include <linux/string.h> 20 #include <asm/types.h> 21 #include <asm/lppaca.h> 22 #include <asm/mmu.h> 23 #include <asm/page.h> 24 #ifdef CONFIG_PPC_BOOK3E 25 #include <asm/exception-64e.h> 26 #else 27 #include <asm/exception-64s.h> 28 #endif 29 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 30 #include <asm/kvm_book3s_asm.h> 31 #endif 32 #include <asm/accounting.h> 33 #include <asm/hmi.h> 34 35 register struct paca_struct *local_paca asm("r13"); 36 37 #if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP) 38 extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */ 39 /* 40 * Add standard checks that preemption cannot occur when using get_paca(): 41 * otherwise the paca_struct it points to may be the wrong one just after. 42 */ 43 #define get_paca() ((void) debug_smp_processor_id(), local_paca) 44 #else 45 #define get_paca() local_paca 46 #endif 47 48 #define get_lppaca() (get_paca()->lppaca_ptr) 49 #define get_slb_shadow() (get_paca()->slb_shadow_ptr) 50 51 struct task_struct; 52 53 /* 54 * Defines the layout of the paca. 55 * 56 * This structure is not directly accessed by firmware or the service 57 * processor. 58 */ 59 struct paca_struct { 60 #ifdef CONFIG_PPC_BOOK3S 61 /* 62 * Because hw_cpu_id, unlike other paca fields, is accessed 63 * routinely from other CPUs (from the IRQ code), we stick to 64 * read-only (after boot) fields in the first cacheline to 65 * avoid cacheline bouncing. 66 */ 67 68 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ 69 #endif /* CONFIG_PPC_BOOK3S */ 70 /* 71 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 72 * load lock_token and paca_index with a single lwz 73 * instruction. They must travel together and be properly 74 * aligned. 75 */ 76 #ifdef __BIG_ENDIAN__ 77 u16 lock_token; /* Constant 0x8000, used in locks */ 78 u16 paca_index; /* Logical processor number */ 79 #else 80 u16 paca_index; /* Logical processor number */ 81 u16 lock_token; /* Constant 0x8000, used in locks */ 82 #endif 83 84 u64 kernel_toc; /* Kernel TOC address */ 85 u64 kernelbase; /* Base address of kernel */ 86 u64 kernel_msr; /* MSR while running in kernel */ 87 void *emergency_sp; /* pointer to emergency stack */ 88 u64 data_offset; /* per cpu data offset */ 89 s16 hw_cpu_id; /* Physical processor number */ 90 u8 cpu_start; /* At startup, processor spins until */ 91 /* this becomes non-zero. */ 92 u8 kexec_state; /* set when kexec down has irqs off */ 93 #ifdef CONFIG_PPC_STD_MMU_64 94 struct slb_shadow *slb_shadow_ptr; 95 struct dtl_entry *dispatch_log; 96 struct dtl_entry *dispatch_log_end; 97 #endif /* CONFIG_PPC_STD_MMU_64 */ 98 u64 dscr_default; /* per-CPU default DSCR */ 99 100 #ifdef CONFIG_PPC_STD_MMU_64 101 /* 102 * Now, starting in cacheline 2, the exception save areas 103 */ 104 /* used for most interrupts/exceptions */ 105 u64 exgen[EX_SIZE] __attribute__((aligned(0x80))); 106 u64 exslb[EX_SIZE]; /* used for SLB/segment table misses 107 * on the linear mapping */ 108 /* SLB related definitions */ 109 u16 vmalloc_sllp; 110 u16 slb_cache_ptr; 111 u32 slb_cache[SLB_CACHE_ENTRIES]; 112 #endif /* CONFIG_PPC_STD_MMU_64 */ 113 114 #ifdef CONFIG_PPC_BOOK3E 115 u64 exgen[8] __aligned(0x40); 116 /* Keep pgd in the same cacheline as the start of extlb */ 117 pgd_t *pgd __aligned(0x40); /* Current PGD */ 118 pgd_t *kernel_pgd; /* Kernel PGD */ 119 120 /* Shared by all threads of a core -- points to tcd of first thread */ 121 struct tlb_core_data *tcd_ptr; 122 123 /* 124 * We can have up to 3 levels of reentrancy in the TLB miss handler, 125 * in each of four exception levels (normal, crit, mcheck, debug). 126 */ 127 u64 extlb[12][EX_TLB_SIZE / sizeof(u64)]; 128 u64 exmc[8]; /* used for machine checks */ 129 u64 excrit[8]; /* used for crit interrupts */ 130 u64 exdbg[8]; /* used for debug interrupts */ 131 132 /* Kernel stack pointers for use by special exceptions */ 133 void *mc_kstack; 134 void *crit_kstack; 135 void *dbg_kstack; 136 137 struct tlb_core_data tcd; 138 #endif /* CONFIG_PPC_BOOK3E */ 139 140 #ifdef CONFIG_PPC_BOOK3S 141 mm_context_id_t mm_ctx_id; 142 #ifdef CONFIG_PPC_MM_SLICES 143 u64 mm_ctx_low_slices_psize; 144 unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE]; 145 unsigned long addr_limit; 146 #else 147 u16 mm_ctx_user_psize; 148 u16 mm_ctx_sllp; 149 #endif 150 #endif 151 152 /* 153 * then miscellaneous read-write fields 154 */ 155 struct task_struct *__current; /* Pointer to current */ 156 u64 kstack; /* Saved Kernel stack addr */ 157 u64 stab_rr; /* stab/slb round-robin counter */ 158 u64 saved_r1; /* r1 save for RTAS calls or PM */ 159 u64 saved_msr; /* MSR saved here by enter_rtas */ 160 u16 trap_save; /* Used when bad stack is encountered */ 161 u8 soft_enabled; /* irq soft-enable flag */ 162 u8 irq_happened; /* irq happened while soft-disabled */ 163 u8 io_sync; /* writel() needs spin_unlock sync */ 164 u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */ 165 u8 nap_state_lost; /* NV GPR values lost in power7_idle */ 166 u64 sprg_vdso; /* Saved user-visible sprg */ 167 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 168 u64 tm_scratch; /* TM scratch area for reclaim */ 169 #endif 170 171 #ifdef CONFIG_PPC_POWERNV 172 /* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */ 173 u32 *core_idle_state_ptr; 174 u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */ 175 /* Mask to indicate thread id in core */ 176 u8 thread_mask; 177 /* Mask to denote subcore sibling threads */ 178 u8 subcore_sibling_mask; 179 /* 180 * Pointer to an array which contains pointer 181 * to the sibling threads' paca. 182 */ 183 struct paca_struct **thread_sibling_pacas; 184 /* The PSSCR value that the kernel requested before going to stop */ 185 u64 requested_psscr; 186 #endif 187 188 #ifdef CONFIG_PPC_STD_MMU_64 189 /* Non-maskable exceptions that are not performance critical */ 190 u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */ 191 u64 exmc[EX_SIZE]; /* used for machine checks */ 192 #endif 193 #ifdef CONFIG_PPC_BOOK3S_64 194 /* Exclusive stacks for system reset and machine check exception. */ 195 void *nmi_emergency_sp; 196 void *mc_emergency_sp; 197 198 u16 in_nmi; /* In nmi handler */ 199 200 /* 201 * Flag to check whether we are in machine check early handler 202 * and already using emergency stack. 203 */ 204 u16 in_mce; 205 u8 hmi_event_available; /* HMI event is available */ 206 #endif 207 208 /* Stuff for accurate time accounting */ 209 struct cpu_accounting_data accounting; 210 u64 dtl_ridx; /* read index in dispatch log */ 211 struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */ 212 213 #ifdef CONFIG_KVM_BOOK3S_HANDLER 214 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 215 /* We use this to store guest state in */ 216 struct kvmppc_book3s_shadow_vcpu shadow_vcpu; 217 #endif 218 struct kvmppc_host_state kvm_hstate; 219 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 220 /* 221 * Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for 222 * more details 223 */ 224 struct sibling_subcore_state *sibling_subcore_state; 225 #endif 226 #endif 227 }; 228 229 extern void copy_mm_to_paca(struct mm_struct *mm); 230 extern struct paca_struct *paca; 231 extern void initialise_paca(struct paca_struct *new_paca, int cpu); 232 extern void setup_paca(struct paca_struct *new_paca); 233 extern void allocate_pacas(void); 234 extern void free_unused_pacas(void); 235 236 #else /* CONFIG_PPC64 */ 237 238 static inline void allocate_pacas(void) { }; 239 static inline void free_unused_pacas(void) { }; 240 241 #endif /* CONFIG_PPC64 */ 242 243 #endif /* __KERNEL__ */ 244 #endif /* _ASM_POWERPC_PACA_H */ 245