1 /* 2 * PowerNV OPAL definitions. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef _ASM_POWERPC_OPAL_H 13 #define _ASM_POWERPC_OPAL_H 14 15 #include <asm/opal-api.h> 16 17 #ifndef __ASSEMBLY__ 18 19 #include <linux/notifier.h> 20 21 /* We calculate number of sg entries based on PAGE_SIZE */ 22 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 23 24 /* /sys/firmware/opal */ 25 extern struct kobject *opal_kobj; 26 27 /* /ibm,opal */ 28 extern struct device_node *opal_node; 29 30 /* API functions */ 31 int64_t opal_invalid_call(void); 32 int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf); 33 int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr, 34 uint64_t bdf); 35 int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid, 36 uint64_t lpcr); 37 int64_t opal_npu_spa_setup(uint64_t phb_id, uint32_t bdfn, 38 uint64_t addr, uint64_t PE_mask); 39 int64_t opal_npu_spa_clear_cache(uint64_t phb_id, uint32_t bdfn, 40 uint64_t PE_handle); 41 int64_t opal_npu_tl_set(uint64_t phb_id, uint32_t bdfn, long cap, 42 uint64_t rate_phys, uint32_t size); 43 int64_t opal_console_write(int64_t term_number, __be64 *length, 44 const uint8_t *buffer); 45 int64_t opal_console_read(int64_t term_number, __be64 *length, 46 uint8_t *buffer); 47 int64_t opal_console_write_buffer_space(int64_t term_number, 48 __be64 *length); 49 int64_t opal_console_flush(int64_t term_number); 50 int64_t opal_rtc_read(__be32 *year_month_day, 51 __be64 *hour_minute_second_millisecond); 52 int64_t opal_rtc_write(uint32_t year_month_day, 53 uint64_t hour_minute_second_millisecond); 54 int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min); 55 int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day, 56 uint32_t hour_min); 57 int64_t opal_cec_power_down(uint64_t request); 58 int64_t opal_cec_reboot(void); 59 int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag); 60 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 61 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 62 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); 63 int64_t opal_poll_events(__be64 *outstanding_event_mask); 64 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 65 uint64_t tce_mem_size); 66 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 67 uint64_t tce_mem_size); 68 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 69 uint64_t offset, uint8_t *data); 70 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 71 uint64_t offset, __be16 *data); 72 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 73 uint64_t offset, __be32 *data); 74 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 75 uint64_t offset, uint8_t data); 76 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 77 uint64_t offset, uint16_t data); 78 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 79 uint64_t offset, uint32_t data); 80 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 81 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); 82 int64_t opal_register_exception_handler(uint64_t opal_exception, 83 uint64_t handler_address, 84 uint64_t glue_cache_line); 85 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 86 uint8_t *freeze_state, 87 __be16 *pci_error_type, 88 __be64 *phb_status); 89 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 90 uint64_t eeh_action_token); 91 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, 92 uint64_t eeh_action_token); 93 int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type, 94 uint32_t func, uint64_t addr, uint64_t mask); 95 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 96 97 98 99 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 100 uint16_t window_num, uint16_t enable); 101 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 102 uint16_t window_num, 103 uint64_t starting_real_address, 104 uint64_t starting_pci_address, 105 uint64_t size); 106 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 107 uint16_t window_type, uint16_t window_num, 108 uint16_t segment_num); 109 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 110 uint64_t ivt_addr, uint64_t ivt_len, 111 uint64_t reject_array_addr, 112 uint64_t peltv_addr); 113 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 114 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 115 uint8_t pe_action); 116 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 117 uint8_t state); 118 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 119 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 120 uint32_t state); 121 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 122 uint8_t *p_bit, uint8_t *q_bit); 123 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 124 uint8_t p_bit, uint8_t q_bit); 125 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 126 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 127 uint32_t xive_num); 128 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 129 __be32 *interrupt_source_number); 130 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 131 uint8_t msi_range, __be32 *msi_address, 132 __be32 *message_data); 133 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 134 uint32_t xive_num, uint8_t msi_range, 135 __be64 *msi_address, __be32 *message_data); 136 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 137 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 138 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 139 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 140 uint16_t tce_levels, uint64_t tce_table_addr, 141 uint64_t tce_table_size, uint64_t tce_page_size); 142 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 143 uint16_t dma_window_number, uint64_t pci_start_addr, 144 uint64_t pci_mem_size); 145 int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state); 146 147 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 148 uint64_t diag_buffer_len); 149 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 150 uint64_t diag_buffer_len); 151 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 152 uint64_t diag_buffer_len); 153 int64_t opal_pci_fence_phb(uint64_t phb_id); 154 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); 155 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 156 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 157 int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes); 158 int64_t opal_get_dpo_status(__be64 *dpo_timeout); 159 int64_t opal_set_system_attention_led(uint8_t led_action); 160 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe, 161 __be16 *pci_error_type, __be16 *severity); 162 int64_t opal_pci_poll(uint64_t id); 163 int64_t opal_return_cpu(void); 164 int64_t opal_check_token(uint64_t token); 165 int64_t opal_reinit_cpus(uint64_t flags); 166 167 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); 168 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); 169 170 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 171 uint32_t addr, uint32_t data, uint32_t sz); 172 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 173 uint32_t addr, __be32 *data, uint32_t sz); 174 175 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); 176 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); 177 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); 178 int64_t opal_send_ack_elog(uint64_t log_id); 179 void opal_resend_pending_logs(void); 180 181 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 182 int64_t opal_manage_flash(uint8_t op); 183 int64_t opal_update_flash(uint64_t blk_list); 184 int64_t opal_dump_init(uint8_t dump_type); 185 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); 186 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); 187 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); 188 int64_t opal_dump_ack(uint32_t dump_id); 189 int64_t opal_dump_resend_notification(void); 190 191 int64_t opal_get_msg(uint64_t buffer, uint64_t size); 192 int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines, 193 uint64_t num_lines); 194 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); 195 int64_t opal_sync_host_reboot(void); 196 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, 197 uint64_t length); 198 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, 199 uint64_t length); 200 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); 201 int64_t opal_handle_hmi(void); 202 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); 203 int64_t opal_unregister_dump_region(uint32_t id); 204 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); 205 int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag); 206 int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number); 207 int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg, 208 uint64_t msg_len); 209 int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg, 210 uint64_t *msg_len); 211 int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id, 212 struct opal_i2c_request *oreq); 213 int64_t opal_prd_msg(struct opal_prd_msg *msg); 214 int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask, 215 __be64 *led_value, __be64 *max_led_type); 216 int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask, 217 const u64 led_value, __be64 *max_led_type); 218 219 int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf, 220 uint64_t size, uint64_t token); 221 int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf, 222 uint64_t size, uint64_t token); 223 int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size, 224 uint64_t token); 225 int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len); 226 int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data); 227 int64_t opal_pci_get_power_state(uint64_t id, uint64_t data); 228 int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id, 229 uint64_t data); 230 int64_t opal_pci_poll2(uint64_t id, uint64_t data); 231 232 int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll); 233 int64_t opal_int_set_cppr(uint8_t cppr); 234 int64_t opal_int_eoi(uint32_t xirr); 235 int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr); 236 int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type, 237 uint32_t pe_num, uint32_t tce_size, 238 uint64_t dma_addr, uint32_t npages); 239 int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr); 240 int64_t opal_xive_reset(uint64_t version); 241 int64_t opal_xive_get_irq_info(uint32_t girq, 242 __be64 *out_flags, 243 __be64 *out_eoi_page, 244 __be64 *out_trig_page, 245 __be32 *out_esb_shift, 246 __be32 *out_src_chip); 247 int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp, 248 uint8_t *out_prio, __be32 *out_lirq); 249 int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio, 250 uint32_t lirq); 251 int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio, 252 __be64 *out_qpage, 253 __be64 *out_qsize, 254 __be64 *out_qeoi_page, 255 __be32 *out_escalate_irq, 256 __be64 *out_qflags); 257 int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio, 258 uint64_t qpage, 259 uint64_t qsize, 260 uint64_t qflags); 261 int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr); 262 int64_t opal_xive_alloc_vp_block(uint32_t alloc_order); 263 int64_t opal_xive_free_vp_block(uint64_t vp); 264 int64_t opal_xive_get_vp_info(uint64_t vp, 265 __be64 *out_flags, 266 __be64 *out_cam_value, 267 __be64 *out_report_cl_pair, 268 __be32 *out_chip_id); 269 int64_t opal_xive_set_vp_info(uint64_t vp, 270 uint64_t flags, 271 uint64_t report_cl_pair); 272 int64_t opal_xive_allocate_irq(uint32_t chip_id); 273 int64_t opal_xive_free_irq(uint32_t girq); 274 int64_t opal_xive_sync(uint32_t type, uint32_t id); 275 int64_t opal_xive_dump(uint32_t type, uint32_t id); 276 int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target, 277 uint64_t desc, uint16_t pe_number); 278 279 int64_t opal_imc_counters_init(uint32_t type, uint64_t address, 280 uint64_t cpu_pir); 281 int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir); 282 int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir); 283 284 int opal_get_powercap(u32 handle, int token, u32 *pcap); 285 int opal_set_powercap(u32 handle, int token, u32 pcap); 286 int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr); 287 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr); 288 int opal_sensor_group_clear(u32 group_hndl, int token); 289 290 s64 opal_signal_system_reset(s32 cpu); 291 292 /* Internal functions */ 293 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 294 int depth, void *data); 295 extern int early_init_dt_scan_recoverable_ranges(unsigned long node, 296 const char *uname, int depth, void *data); 297 extern void opal_configure_cores(void); 298 299 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 300 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 301 302 extern void hvc_opal_init_early(void); 303 304 extern int opal_notifier_register(struct notifier_block *nb); 305 extern int opal_notifier_unregister(struct notifier_block *nb); 306 307 extern int opal_message_notifier_register(enum opal_msg_type msg_type, 308 struct notifier_block *nb); 309 extern int opal_message_notifier_unregister(enum opal_msg_type msg_type, 310 struct notifier_block *nb); 311 extern void opal_notifier_enable(void); 312 extern void opal_notifier_disable(void); 313 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 314 315 extern int opal_async_get_token_interruptible(void); 316 extern int opal_async_release_token(int token); 317 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); 318 extern int opal_async_wait_response_interruptible(uint64_t token, 319 struct opal_msg *msg); 320 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); 321 322 struct rtc_time; 323 extern unsigned long opal_get_boot_time(void); 324 extern void opal_nvram_init(void); 325 extern void opal_flash_update_init(void); 326 extern void opal_flash_term_callback(void); 327 extern int opal_elog_init(void); 328 extern void opal_platform_dump_init(void); 329 extern void opal_sys_param_init(void); 330 extern void opal_msglog_init(void); 331 extern void opal_msglog_sysfs_init(void); 332 extern int opal_async_comp_init(void); 333 extern int opal_sensor_init(void); 334 extern int opal_hmi_handler_init(void); 335 extern int opal_event_init(void); 336 337 extern int opal_machine_check(struct pt_regs *regs); 338 extern bool opal_mce_check_early_recovery(struct pt_regs *regs); 339 extern int opal_hmi_exception_early(struct pt_regs *regs); 340 extern int opal_handle_hmi_exception(struct pt_regs *regs); 341 342 extern void opal_shutdown(void); 343 extern int opal_resync_timebase(void); 344 345 extern void opal_lpc_init(void); 346 347 extern void opal_kmsg_init(void); 348 349 extern int opal_event_request(unsigned int opal_event_nr); 350 351 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 352 unsigned long vmalloc_size); 353 void opal_free_sg_list(struct opal_sg_list *sg); 354 355 extern int opal_error_code(int rc); 356 357 ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count); 358 359 static inline int opal_get_async_rc(struct opal_msg msg) 360 { 361 if (msg.msg_type != OPAL_MSG_ASYNC_COMP) 362 return OPAL_PARAMETER; 363 else 364 return be64_to_cpu(msg.params[1]); 365 } 366 367 void opal_wake_poller(void); 368 369 void opal_powercap_init(void); 370 void opal_psr_init(void); 371 void opal_sensor_groups_init(void); 372 373 #endif /* __ASSEMBLY__ */ 374 375 #endif /* _ASM_POWERPC_OPAL_H */ 376