1 /* 2 * PowerNV OPAL definitions. 3 * 4 * Copyright 2011 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_H 13 #define __OPAL_H 14 15 #ifndef __ASSEMBLY__ 16 /* 17 * SG entry 18 * 19 * WARNING: The current implementation requires each entry 20 * to represent a block that is 4k aligned *and* each block 21 * size except the last one in the list to be as well. 22 */ 23 struct opal_sg_entry { 24 __be64 data; 25 __be64 length; 26 }; 27 28 /* SG list */ 29 struct opal_sg_list { 30 __be64 length; 31 __be64 next; 32 struct opal_sg_entry entry[]; 33 }; 34 35 /* We calculate number of sg entries based on PAGE_SIZE */ 36 #define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry)) 37 38 #endif /* __ASSEMBLY__ */ 39 40 /****** OPAL APIs ******/ 41 42 /* Return codes */ 43 #define OPAL_SUCCESS 0 44 #define OPAL_PARAMETER -1 45 #define OPAL_BUSY -2 46 #define OPAL_PARTIAL -3 47 #define OPAL_CONSTRAINED -4 48 #define OPAL_CLOSED -5 49 #define OPAL_HARDWARE -6 50 #define OPAL_UNSUPPORTED -7 51 #define OPAL_PERMISSION -8 52 #define OPAL_NO_MEM -9 53 #define OPAL_RESOURCE -10 54 #define OPAL_INTERNAL_ERROR -11 55 #define OPAL_BUSY_EVENT -12 56 #define OPAL_HARDWARE_FROZEN -13 57 #define OPAL_WRONG_STATE -14 58 #define OPAL_ASYNC_COMPLETION -15 59 60 /* API Tokens (in r0) */ 61 #define OPAL_INVALID_CALL -1 62 #define OPAL_CONSOLE_WRITE 1 63 #define OPAL_CONSOLE_READ 2 64 #define OPAL_RTC_READ 3 65 #define OPAL_RTC_WRITE 4 66 #define OPAL_CEC_POWER_DOWN 5 67 #define OPAL_CEC_REBOOT 6 68 #define OPAL_READ_NVRAM 7 69 #define OPAL_WRITE_NVRAM 8 70 #define OPAL_HANDLE_INTERRUPT 9 71 #define OPAL_POLL_EVENTS 10 72 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 73 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 74 #define OPAL_PCI_CONFIG_READ_BYTE 13 75 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 76 #define OPAL_PCI_CONFIG_READ_WORD 15 77 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 78 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 79 #define OPAL_PCI_CONFIG_WRITE_WORD 18 80 #define OPAL_SET_XIVE 19 81 #define OPAL_GET_XIVE 20 82 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 83 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 84 #define OPAL_PCI_EEH_FREEZE_STATUS 23 85 #define OPAL_PCI_SHPC 24 86 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 87 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 88 #define OPAL_PCI_PHB_MMIO_ENABLE 27 89 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 90 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 91 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 92 #define OPAL_PCI_SET_PE 31 93 #define OPAL_PCI_SET_PELTV 32 94 #define OPAL_PCI_SET_MVE 33 95 #define OPAL_PCI_SET_MVE_ENABLE 34 96 #define OPAL_PCI_GET_XIVE_REISSUE 35 97 #define OPAL_PCI_SET_XIVE_REISSUE 36 98 #define OPAL_PCI_SET_XIVE_PE 37 99 #define OPAL_GET_XIVE_SOURCE 38 100 #define OPAL_GET_MSI_32 39 101 #define OPAL_GET_MSI_64 40 102 #define OPAL_START_CPU 41 103 #define OPAL_QUERY_CPU_STATUS 42 104 #define OPAL_WRITE_OPPANEL 43 105 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 106 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 107 #define OPAL_PCI_RESET 49 108 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 109 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 110 #define OPAL_PCI_FENCE_PHB 52 111 #define OPAL_PCI_REINIT 53 112 #define OPAL_PCI_MASK_PE_ERROR 54 113 #define OPAL_SET_SLOT_LED_STATUS 55 114 #define OPAL_GET_EPOW_STATUS 56 115 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 116 #define OPAL_RESERVED1 58 117 #define OPAL_RESERVED2 59 118 #define OPAL_PCI_NEXT_ERROR 60 119 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 120 #define OPAL_PCI_POLL 62 121 #define OPAL_PCI_MSI_EOI 63 122 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 123 #define OPAL_XSCOM_READ 65 124 #define OPAL_XSCOM_WRITE 66 125 #define OPAL_LPC_READ 67 126 #define OPAL_LPC_WRITE 68 127 #define OPAL_RETURN_CPU 69 128 #define OPAL_REINIT_CPUS 70 129 #define OPAL_ELOG_READ 71 130 #define OPAL_ELOG_WRITE 72 131 #define OPAL_ELOG_ACK 73 132 #define OPAL_ELOG_RESEND 74 133 #define OPAL_ELOG_SIZE 75 134 #define OPAL_FLASH_VALIDATE 76 135 #define OPAL_FLASH_MANAGE 77 136 #define OPAL_FLASH_UPDATE 78 137 #define OPAL_RESYNC_TIMEBASE 79 138 #define OPAL_DUMP_INIT 81 139 #define OPAL_DUMP_INFO 82 140 #define OPAL_DUMP_READ 83 141 #define OPAL_DUMP_ACK 84 142 #define OPAL_GET_MSG 85 143 #define OPAL_CHECK_ASYNC_COMPLETION 86 144 #define OPAL_SYNC_HOST_REBOOT 87 145 #define OPAL_SENSOR_READ 88 146 #define OPAL_GET_PARAM 89 147 #define OPAL_SET_PARAM 90 148 #define OPAL_DUMP_RESEND 91 149 #define OPAL_DUMP_INFO2 94 150 #define OPAL_PCI_EEH_FREEZE_SET 97 151 #define OPAL_HANDLE_HMI 98 152 #define OPAL_REGISTER_DUMP_REGION 101 153 #define OPAL_UNREGISTER_DUMP_REGION 102 154 155 #ifndef __ASSEMBLY__ 156 157 #include <linux/notifier.h> 158 159 /* Other enums */ 160 enum OpalVendorApiTokens { 161 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999 162 }; 163 164 enum OpalFreezeState { 165 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 166 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 167 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 168 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 169 OPAL_EEH_STOPPED_RESET = 4, 170 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 171 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 172 }; 173 174 enum OpalEehFreezeActionToken { 175 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 176 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 177 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 178 179 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 180 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 181 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 182 }; 183 184 enum OpalPciStatusToken { 185 OPAL_EEH_NO_ERROR = 0, 186 OPAL_EEH_IOC_ERROR = 1, 187 OPAL_EEH_PHB_ERROR = 2, 188 OPAL_EEH_PE_ERROR = 3, 189 OPAL_EEH_PE_MMIO_ERROR = 4, 190 OPAL_EEH_PE_DMA_ERROR = 5 191 }; 192 193 enum OpalPciErrorSeverity { 194 OPAL_EEH_SEV_NO_ERROR = 0, 195 OPAL_EEH_SEV_IOC_DEAD = 1, 196 OPAL_EEH_SEV_PHB_DEAD = 2, 197 OPAL_EEH_SEV_PHB_FENCED = 3, 198 OPAL_EEH_SEV_PE_ER = 4, 199 OPAL_EEH_SEV_INF = 5 200 }; 201 202 enum OpalShpcAction { 203 OPAL_SHPC_GET_LINK_STATE = 0, 204 OPAL_SHPC_GET_SLOT_STATE = 1 205 }; 206 207 enum OpalShpcLinkState { 208 OPAL_SHPC_LINK_DOWN = 0, 209 OPAL_SHPC_LINK_UP = 1 210 }; 211 212 enum OpalMmioWindowType { 213 OPAL_M32_WINDOW_TYPE = 1, 214 OPAL_M64_WINDOW_TYPE = 2, 215 OPAL_IO_WINDOW_TYPE = 3 216 }; 217 218 enum OpalShpcSlotState { 219 OPAL_SHPC_DEV_NOT_PRESENT = 0, 220 OPAL_SHPC_DEV_PRESENT = 1 221 }; 222 223 enum OpalExceptionHandler { 224 OPAL_MACHINE_CHECK_HANDLER = 1, 225 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 226 OPAL_SOFTPATCH_HANDLER = 3 227 }; 228 229 enum OpalPendingState { 230 OPAL_EVENT_OPAL_INTERNAL = 0x1, 231 OPAL_EVENT_NVRAM = 0x2, 232 OPAL_EVENT_RTC = 0x4, 233 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 234 OPAL_EVENT_CONSOLE_INPUT = 0x10, 235 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 236 OPAL_EVENT_ERROR_LOG = 0x40, 237 OPAL_EVENT_EPOW = 0x80, 238 OPAL_EVENT_LED_STATUS = 0x100, 239 OPAL_EVENT_PCI_ERROR = 0x200, 240 OPAL_EVENT_DUMP_AVAIL = 0x400, 241 OPAL_EVENT_MSG_PENDING = 0x800, 242 }; 243 244 enum OpalMessageType { 245 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 246 * additional params function-specific 247 */ 248 OPAL_MSG_MEM_ERR, 249 OPAL_MSG_EPOW, 250 OPAL_MSG_SHUTDOWN, 251 OPAL_MSG_HMI_EVT, 252 OPAL_MSG_TYPE_MAX, 253 }; 254 255 /* Machine check related definitions */ 256 enum OpalMCE_Version { 257 OpalMCE_V1 = 1, 258 }; 259 260 enum OpalMCE_Severity { 261 OpalMCE_SEV_NO_ERROR = 0, 262 OpalMCE_SEV_WARNING = 1, 263 OpalMCE_SEV_ERROR_SYNC = 2, 264 OpalMCE_SEV_FATAL = 3, 265 }; 266 267 enum OpalMCE_Disposition { 268 OpalMCE_DISPOSITION_RECOVERED = 0, 269 OpalMCE_DISPOSITION_NOT_RECOVERED = 1, 270 }; 271 272 enum OpalMCE_Initiator { 273 OpalMCE_INITIATOR_UNKNOWN = 0, 274 OpalMCE_INITIATOR_CPU = 1, 275 }; 276 277 enum OpalMCE_ErrorType { 278 OpalMCE_ERROR_TYPE_UNKNOWN = 0, 279 OpalMCE_ERROR_TYPE_UE = 1, 280 OpalMCE_ERROR_TYPE_SLB = 2, 281 OpalMCE_ERROR_TYPE_ERAT = 3, 282 OpalMCE_ERROR_TYPE_TLB = 4, 283 }; 284 285 enum OpalMCE_UeErrorType { 286 OpalMCE_UE_ERROR_INDETERMINATE = 0, 287 OpalMCE_UE_ERROR_IFETCH = 1, 288 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2, 289 OpalMCE_UE_ERROR_LOAD_STORE = 3, 290 OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4, 291 }; 292 293 enum OpalMCE_SlbErrorType { 294 OpalMCE_SLB_ERROR_INDETERMINATE = 0, 295 OpalMCE_SLB_ERROR_PARITY = 1, 296 OpalMCE_SLB_ERROR_MULTIHIT = 2, 297 }; 298 299 enum OpalMCE_EratErrorType { 300 OpalMCE_ERAT_ERROR_INDETERMINATE = 0, 301 OpalMCE_ERAT_ERROR_PARITY = 1, 302 OpalMCE_ERAT_ERROR_MULTIHIT = 2, 303 }; 304 305 enum OpalMCE_TlbErrorType { 306 OpalMCE_TLB_ERROR_INDETERMINATE = 0, 307 OpalMCE_TLB_ERROR_PARITY = 1, 308 OpalMCE_TLB_ERROR_MULTIHIT = 2, 309 }; 310 311 enum OpalThreadStatus { 312 OPAL_THREAD_INACTIVE = 0x0, 313 OPAL_THREAD_STARTED = 0x1, 314 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 315 }; 316 317 enum OpalPciBusCompare { 318 OpalPciBusAny = 0, /* Any bus number match */ 319 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 320 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 321 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 322 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 323 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 324 OpalPciBusAll = 7, /* Match bus number exactly */ 325 }; 326 327 enum OpalDeviceCompare { 328 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 329 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 330 }; 331 332 enum OpalFuncCompare { 333 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 334 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 335 }; 336 337 enum OpalPeAction { 338 OPAL_UNMAP_PE = 0, 339 OPAL_MAP_PE = 1 340 }; 341 342 enum OpalPeltvAction { 343 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 344 OPAL_ADD_PE_TO_DOMAIN = 1 345 }; 346 347 enum OpalMveEnableAction { 348 OPAL_DISABLE_MVE = 0, 349 OPAL_ENABLE_MVE = 1 350 }; 351 352 enum OpalM64EnableAction { 353 OPAL_DISABLE_M64 = 0, 354 OPAL_ENABLE_M64_SPLIT = 1, 355 OPAL_ENABLE_M64_NON_SPLIT = 2 356 }; 357 358 enum OpalPciResetScope { 359 OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3, 360 OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5, 361 OPAL_PCI_IODA_TABLE_RESET = 6, 362 }; 363 364 enum OpalPciReinitScope { 365 OPAL_REINIT_PCI_DEV = 1000 366 }; 367 368 enum OpalPciResetState { 369 OPAL_DEASSERT_RESET = 0, 370 OPAL_ASSERT_RESET = 1 371 }; 372 373 enum OpalPciMaskAction { 374 OPAL_UNMASK_ERROR_TYPE = 0, 375 OPAL_MASK_ERROR_TYPE = 1 376 }; 377 378 enum OpalSlotLedType { 379 OPAL_SLOT_LED_ID_TYPE = 0, 380 OPAL_SLOT_LED_FAULT_TYPE = 1 381 }; 382 383 enum OpalLedAction { 384 OPAL_TURN_OFF_LED = 0, 385 OPAL_TURN_ON_LED = 1, 386 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2 387 }; 388 389 enum OpalEpowStatus { 390 OPAL_EPOW_NONE = 0, 391 OPAL_EPOW_UPS = 1, 392 OPAL_EPOW_OVER_AMBIENT_TEMP = 2, 393 OPAL_EPOW_OVER_INTERNAL_TEMP = 3 394 }; 395 396 /* 397 * Address cycle types for LPC accesses. These also correspond 398 * to the content of the first cell of the "reg" property for 399 * device nodes on the LPC bus 400 */ 401 enum OpalLPCAddressType { 402 OPAL_LPC_MEM = 0, 403 OPAL_LPC_IO = 1, 404 OPAL_LPC_FW = 2, 405 }; 406 407 /* System parameter permission */ 408 enum OpalSysparamPerm { 409 OPAL_SYSPARAM_READ = 0x1, 410 OPAL_SYSPARAM_WRITE = 0x2, 411 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 412 }; 413 414 struct opal_msg { 415 __be32 msg_type; 416 __be32 reserved; 417 __be64 params[8]; 418 }; 419 420 struct opal_machine_check_event { 421 enum OpalMCE_Version version:8; /* 0x00 */ 422 uint8_t in_use; /* 0x01 */ 423 enum OpalMCE_Severity severity:8; /* 0x02 */ 424 enum OpalMCE_Initiator initiator:8; /* 0x03 */ 425 enum OpalMCE_ErrorType error_type:8; /* 0x04 */ 426 enum OpalMCE_Disposition disposition:8; /* 0x05 */ 427 uint8_t reserved_1[2]; /* 0x06 */ 428 uint64_t gpr3; /* 0x08 */ 429 uint64_t srr0; /* 0x10 */ 430 uint64_t srr1; /* 0x18 */ 431 union { /* 0x20 */ 432 struct { 433 enum OpalMCE_UeErrorType ue_error_type:8; 434 uint8_t effective_address_provided; 435 uint8_t physical_address_provided; 436 uint8_t reserved_1[5]; 437 uint64_t effective_address; 438 uint64_t physical_address; 439 uint8_t reserved_2[8]; 440 } ue_error; 441 442 struct { 443 enum OpalMCE_SlbErrorType slb_error_type:8; 444 uint8_t effective_address_provided; 445 uint8_t reserved_1[6]; 446 uint64_t effective_address; 447 uint8_t reserved_2[16]; 448 } slb_error; 449 450 struct { 451 enum OpalMCE_EratErrorType erat_error_type:8; 452 uint8_t effective_address_provided; 453 uint8_t reserved_1[6]; 454 uint64_t effective_address; 455 uint8_t reserved_2[16]; 456 } erat_error; 457 458 struct { 459 enum OpalMCE_TlbErrorType tlb_error_type:8; 460 uint8_t effective_address_provided; 461 uint8_t reserved_1[6]; 462 uint64_t effective_address; 463 uint8_t reserved_2[16]; 464 } tlb_error; 465 } u; 466 }; 467 468 /* FSP memory errors handling */ 469 enum OpalMemErr_Version { 470 OpalMemErr_V1 = 1, 471 }; 472 473 enum OpalMemErrType { 474 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 475 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 476 OPAL_MEM_ERR_TYPE_SCRUB, 477 }; 478 479 /* Memory Reilience error type */ 480 enum OpalMemErr_ResilErrType { 481 OPAL_MEM_RESILIENCE_CE = 0, 482 OPAL_MEM_RESILIENCE_UE, 483 OPAL_MEM_RESILIENCE_UE_SCRUB, 484 }; 485 486 /* Dynamic Memory Deallocation type */ 487 enum OpalMemErr_DynErrType { 488 OPAL_MEM_DYNAMIC_DEALLOC = 0, 489 }; 490 491 /* OpalMemoryErrorData->flags */ 492 #define OPAL_MEM_CORRECTED_ERROR 0x0001 493 #define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002 494 #define OPAL_MEM_ACK_REQUIRED 0x8000 495 496 struct OpalMemoryErrorData { 497 enum OpalMemErr_Version version:8; /* 0x00 */ 498 enum OpalMemErrType type:8; /* 0x01 */ 499 __be16 flags; /* 0x02 */ 500 uint8_t reserved_1[4]; /* 0x04 */ 501 502 union { 503 /* Memory Resilience corrected/uncorrected error info */ 504 struct { 505 enum OpalMemErr_ResilErrType resil_err_type:8; 506 uint8_t reserved_1[7]; 507 __be64 physical_address_start; 508 __be64 physical_address_end; 509 } resilience; 510 /* Dynamic memory deallocation error info */ 511 struct { 512 enum OpalMemErr_DynErrType dyn_err_type:8; 513 uint8_t reserved_1[7]; 514 __be64 physical_address_start; 515 __be64 physical_address_end; 516 } dyn_dealloc; 517 } u; 518 }; 519 520 /* HMI interrupt event */ 521 enum OpalHMI_Version { 522 OpalHMIEvt_V1 = 1, 523 }; 524 525 enum OpalHMI_Severity { 526 OpalHMI_SEV_NO_ERROR = 0, 527 OpalHMI_SEV_WARNING = 1, 528 OpalHMI_SEV_ERROR_SYNC = 2, 529 OpalHMI_SEV_FATAL = 3, 530 }; 531 532 enum OpalHMI_Disposition { 533 OpalHMI_DISPOSITION_RECOVERED = 0, 534 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 535 }; 536 537 enum OpalHMI_ErrType { 538 OpalHMI_ERROR_MALFUNC_ALERT = 0, 539 OpalHMI_ERROR_PROC_RECOV_DONE, 540 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 541 OpalHMI_ERROR_PROC_RECOV_MASKED, 542 OpalHMI_ERROR_TFAC, 543 OpalHMI_ERROR_TFMR_PARITY, 544 OpalHMI_ERROR_HA_OVERFLOW_WARN, 545 OpalHMI_ERROR_XSCOM_FAIL, 546 OpalHMI_ERROR_XSCOM_DONE, 547 OpalHMI_ERROR_SCOM_FIR, 548 OpalHMI_ERROR_DEBUG_TRIG_FIR, 549 OpalHMI_ERROR_HYP_RESOURCE, 550 }; 551 552 struct OpalHMIEvent { 553 uint8_t version; /* 0x00 */ 554 uint8_t severity; /* 0x01 */ 555 uint8_t type; /* 0x02 */ 556 uint8_t disposition; /* 0x03 */ 557 uint8_t reserved_1[4]; /* 0x04 */ 558 559 __be64 hmer; 560 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 561 __be64 tfmr; 562 }; 563 564 enum { 565 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 566 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 567 OPAL_P7IOC_DIAG_TYPE_BI = 2, 568 OPAL_P7IOC_DIAG_TYPE_CI = 3, 569 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 570 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 571 OPAL_P7IOC_DIAG_TYPE_LAST = 6 572 }; 573 574 struct OpalIoP7IOCErrorData { 575 __be16 type; 576 577 /* GEM */ 578 __be64 gemXfir; 579 __be64 gemRfir; 580 __be64 gemRirqfir; 581 __be64 gemMask; 582 __be64 gemRwof; 583 584 /* LEM */ 585 __be64 lemFir; 586 __be64 lemErrMask; 587 __be64 lemAction0; 588 __be64 lemAction1; 589 __be64 lemWof; 590 591 union { 592 struct OpalIoP7IOCRgcErrorData { 593 __be64 rgcStatus; /* 3E1C10 */ 594 __be64 rgcLdcp; /* 3E1C18 */ 595 }rgc; 596 struct OpalIoP7IOCBiErrorData { 597 __be64 biLdcp0; /* 3C0100, 3C0118 */ 598 __be64 biLdcp1; /* 3C0108, 3C0120 */ 599 __be64 biLdcp2; /* 3C0110, 3C0128 */ 600 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 601 602 u8 biDownbound; /* BI Downbound or Upbound */ 603 }bi; 604 struct OpalIoP7IOCCiErrorData { 605 __be64 ciPortStatus; /* 3Dn008 */ 606 __be64 ciPortLdcp; /* 3Dn010 */ 607 608 u8 ciPort; /* Index of CI port: 0/1 */ 609 }ci; 610 }; 611 }; 612 613 /** 614 * This structure defines the overlay which will be used to store PHB error 615 * data upon request. 616 */ 617 enum { 618 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 619 }; 620 621 enum { 622 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 623 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 624 }; 625 626 enum { 627 OPAL_P7IOC_NUM_PEST_REGS = 128, 628 OPAL_PHB3_NUM_PEST_REGS = 256 629 }; 630 631 struct OpalIoPhbErrorCommon { 632 __be32 version; 633 __be32 ioType; 634 __be32 len; 635 }; 636 637 struct OpalIoP7IOCPhbErrorData { 638 struct OpalIoPhbErrorCommon common; 639 640 __be32 brdgCtl; 641 642 // P7IOC utl regs 643 __be32 portStatusReg; 644 __be32 rootCmplxStatus; 645 __be32 busAgentStatus; 646 647 // P7IOC cfg regs 648 __be32 deviceStatus; 649 __be32 slotStatus; 650 __be32 linkStatus; 651 __be32 devCmdStatus; 652 __be32 devSecStatus; 653 654 // cfg AER regs 655 __be32 rootErrorStatus; 656 __be32 uncorrErrorStatus; 657 __be32 corrErrorStatus; 658 __be32 tlpHdr1; 659 __be32 tlpHdr2; 660 __be32 tlpHdr3; 661 __be32 tlpHdr4; 662 __be32 sourceId; 663 664 __be32 rsv3; 665 666 // Record data about the call to allocate a buffer. 667 __be64 errorClass; 668 __be64 correlator; 669 670 //P7IOC MMIO Error Regs 671 __be64 p7iocPlssr; // n120 672 __be64 p7iocCsr; // n110 673 __be64 lemFir; // nC00 674 __be64 lemErrorMask; // nC18 675 __be64 lemWOF; // nC40 676 __be64 phbErrorStatus; // nC80 677 __be64 phbFirstErrorStatus; // nC88 678 __be64 phbErrorLog0; // nCC0 679 __be64 phbErrorLog1; // nCC8 680 __be64 mmioErrorStatus; // nD00 681 __be64 mmioFirstErrorStatus; // nD08 682 __be64 mmioErrorLog0; // nD40 683 __be64 mmioErrorLog1; // nD48 684 __be64 dma0ErrorStatus; // nD80 685 __be64 dma0FirstErrorStatus; // nD88 686 __be64 dma0ErrorLog0; // nDC0 687 __be64 dma0ErrorLog1; // nDC8 688 __be64 dma1ErrorStatus; // nE00 689 __be64 dma1FirstErrorStatus; // nE08 690 __be64 dma1ErrorLog0; // nE40 691 __be64 dma1ErrorLog1; // nE48 692 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 693 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 694 }; 695 696 struct OpalIoPhb3ErrorData { 697 struct OpalIoPhbErrorCommon common; 698 699 __be32 brdgCtl; 700 701 /* PHB3 UTL regs */ 702 __be32 portStatusReg; 703 __be32 rootCmplxStatus; 704 __be32 busAgentStatus; 705 706 /* PHB3 cfg regs */ 707 __be32 deviceStatus; 708 __be32 slotStatus; 709 __be32 linkStatus; 710 __be32 devCmdStatus; 711 __be32 devSecStatus; 712 713 /* cfg AER regs */ 714 __be32 rootErrorStatus; 715 __be32 uncorrErrorStatus; 716 __be32 corrErrorStatus; 717 __be32 tlpHdr1; 718 __be32 tlpHdr2; 719 __be32 tlpHdr3; 720 __be32 tlpHdr4; 721 __be32 sourceId; 722 723 __be32 rsv3; 724 725 /* Record data about the call to allocate a buffer */ 726 __be64 errorClass; 727 __be64 correlator; 728 729 __be64 nFir; /* 000 */ 730 __be64 nFirMask; /* 003 */ 731 __be64 nFirWOF; /* 008 */ 732 733 /* PHB3 MMIO Error Regs */ 734 __be64 phbPlssr; /* 120 */ 735 __be64 phbCsr; /* 110 */ 736 __be64 lemFir; /* C00 */ 737 __be64 lemErrorMask; /* C18 */ 738 __be64 lemWOF; /* C40 */ 739 __be64 phbErrorStatus; /* C80 */ 740 __be64 phbFirstErrorStatus; /* C88 */ 741 __be64 phbErrorLog0; /* CC0 */ 742 __be64 phbErrorLog1; /* CC8 */ 743 __be64 mmioErrorStatus; /* D00 */ 744 __be64 mmioFirstErrorStatus; /* D08 */ 745 __be64 mmioErrorLog0; /* D40 */ 746 __be64 mmioErrorLog1; /* D48 */ 747 __be64 dma0ErrorStatus; /* D80 */ 748 __be64 dma0FirstErrorStatus; /* D88 */ 749 __be64 dma0ErrorLog0; /* DC0 */ 750 __be64 dma0ErrorLog1; /* DC8 */ 751 __be64 dma1ErrorStatus; /* E00 */ 752 __be64 dma1FirstErrorStatus; /* E08 */ 753 __be64 dma1ErrorLog0; /* E40 */ 754 __be64 dma1ErrorLog1; /* E48 */ 755 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 756 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 757 }; 758 759 enum { 760 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 761 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 762 }; 763 764 typedef struct oppanel_line { 765 const char * line; 766 uint64_t line_len; 767 } oppanel_line_t; 768 769 /* /sys/firmware/opal */ 770 extern struct kobject *opal_kobj; 771 772 /* /ibm,opal */ 773 extern struct device_node *opal_node; 774 775 /* API functions */ 776 int64_t opal_invalid_call(void); 777 int64_t opal_console_write(int64_t term_number, __be64 *length, 778 const uint8_t *buffer); 779 int64_t opal_console_read(int64_t term_number, __be64 *length, 780 uint8_t *buffer); 781 int64_t opal_console_write_buffer_space(int64_t term_number, 782 __be64 *length); 783 int64_t opal_rtc_read(__be32 *year_month_day, 784 __be64 *hour_minute_second_millisecond); 785 int64_t opal_rtc_write(uint32_t year_month_day, 786 uint64_t hour_minute_second_millisecond); 787 int64_t opal_cec_power_down(uint64_t request); 788 int64_t opal_cec_reboot(void); 789 int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 790 int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset); 791 int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask); 792 int64_t opal_poll_events(__be64 *outstanding_event_mask); 793 int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr, 794 uint64_t tce_mem_size); 795 int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr, 796 uint64_t tce_mem_size); 797 int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func, 798 uint64_t offset, uint8_t *data); 799 int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func, 800 uint64_t offset, __be16 *data); 801 int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func, 802 uint64_t offset, __be32 *data); 803 int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func, 804 uint64_t offset, uint8_t data); 805 int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func, 806 uint64_t offset, uint16_t data); 807 int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func, 808 uint64_t offset, uint32_t data); 809 int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority); 810 int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority); 811 int64_t opal_register_exception_handler(uint64_t opal_exception, 812 uint64_t handler_address, 813 uint64_t glue_cache_line); 814 int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number, 815 uint8_t *freeze_state, 816 __be16 *pci_error_type, 817 __be64 *phb_status); 818 int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number, 819 uint64_t eeh_action_token); 820 int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number, 821 uint64_t eeh_action_token); 822 int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state); 823 824 825 826 int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type, 827 uint16_t window_num, uint16_t enable); 828 int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type, 829 uint16_t window_num, 830 uint64_t starting_real_address, 831 uint64_t starting_pci_address, 832 uint64_t size); 833 int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number, 834 uint16_t window_type, uint16_t window_num, 835 uint16_t segment_num); 836 int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr, 837 uint64_t ivt_addr, uint64_t ivt_len, 838 uint64_t reject_array_addr, 839 uint64_t peltv_addr); 840 int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func, 841 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare, 842 uint8_t pe_action); 843 int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe, 844 uint8_t state); 845 int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number); 846 int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number, 847 uint32_t state); 848 int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number, 849 uint8_t *p_bit, uint8_t *q_bit); 850 int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number, 851 uint8_t p_bit, uint8_t q_bit); 852 int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq); 853 int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number, 854 uint32_t xive_num); 855 int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num, 856 __be32 *interrupt_source_number); 857 int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num, 858 uint8_t msi_range, __be32 *msi_address, 859 __be32 *message_data); 860 int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number, 861 uint32_t xive_num, uint8_t msi_range, 862 __be64 *msi_address, __be32 *message_data); 863 int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address); 864 int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status); 865 int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines); 866 int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id, 867 uint16_t tce_levels, uint64_t tce_table_addr, 868 uint64_t tce_table_size, uint64_t tce_page_size); 869 int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number, 870 uint16_t dma_window_number, uint64_t pci_start_addr, 871 uint64_t pci_mem_size); 872 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state); 873 874 int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, 875 uint64_t diag_buffer_len); 876 int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, 877 uint64_t diag_buffer_len); 878 int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer, 879 uint64_t diag_buffer_len); 880 int64_t opal_pci_fence_phb(uint64_t phb_id); 881 int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data); 882 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action); 883 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action); 884 int64_t opal_get_epow_status(__be64 *status); 885 int64_t opal_set_system_attention_led(uint8_t led_action); 886 int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe, 887 __be16 *pci_error_type, __be16 *severity); 888 int64_t opal_pci_poll(uint64_t phb_id); 889 int64_t opal_return_cpu(void); 890 int64_t opal_reinit_cpus(uint64_t flags); 891 892 int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val); 893 int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val); 894 895 int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type, 896 uint32_t addr, uint32_t data, uint32_t sz); 897 int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type, 898 uint32_t addr, __be32 *data, uint32_t sz); 899 900 int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id); 901 int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type); 902 int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset); 903 int64_t opal_send_ack_elog(uint64_t log_id); 904 void opal_resend_pending_logs(void); 905 906 int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result); 907 int64_t opal_manage_flash(uint8_t op); 908 int64_t opal_update_flash(uint64_t blk_list); 909 int64_t opal_dump_init(uint8_t dump_type); 910 int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size); 911 int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type); 912 int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer); 913 int64_t opal_dump_ack(uint32_t dump_id); 914 int64_t opal_dump_resend_notification(void); 915 916 int64_t opal_get_msg(uint64_t buffer, uint64_t size); 917 int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token); 918 int64_t opal_sync_host_reboot(void); 919 int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer, 920 uint64_t length); 921 int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer, 922 uint64_t length); 923 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data); 924 int64_t opal_handle_hmi(void); 925 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end); 926 int64_t opal_unregister_dump_region(uint32_t id); 927 928 /* Internal functions */ 929 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 930 int depth, void *data); 931 extern int early_init_dt_scan_recoverable_ranges(unsigned long node, 932 const char *uname, int depth, void *data); 933 934 extern int opal_get_chars(uint32_t vtermno, char *buf, int count); 935 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len); 936 937 extern void hvc_opal_init_early(void); 938 939 extern int opal_notifier_register(struct notifier_block *nb); 940 extern int opal_notifier_unregister(struct notifier_block *nb); 941 942 extern int opal_message_notifier_register(enum OpalMessageType msg_type, 943 struct notifier_block *nb); 944 extern void opal_notifier_enable(void); 945 extern void opal_notifier_disable(void); 946 extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 947 948 extern int __opal_async_get_token(void); 949 extern int opal_async_get_token_interruptible(void); 950 extern int __opal_async_release_token(int token); 951 extern int opal_async_release_token(int token); 952 extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg); 953 extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data); 954 955 struct rtc_time; 956 extern int opal_set_rtc_time(struct rtc_time *tm); 957 extern void opal_get_rtc_time(struct rtc_time *tm); 958 extern unsigned long opal_get_boot_time(void); 959 extern void opal_nvram_init(void); 960 extern void opal_flash_init(void); 961 extern void opal_flash_term_callback(void); 962 extern int opal_elog_init(void); 963 extern void opal_platform_dump_init(void); 964 extern void opal_sys_param_init(void); 965 extern void opal_msglog_init(void); 966 967 extern int opal_machine_check(struct pt_regs *regs); 968 extern bool opal_mce_check_early_recovery(struct pt_regs *regs); 969 extern int opal_hmi_exception_early(struct pt_regs *regs); 970 extern int opal_handle_hmi_exception(struct pt_regs *regs); 971 972 extern void opal_shutdown(void); 973 extern int opal_resync_timebase(void); 974 975 extern void opal_lpc_init(void); 976 977 struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr, 978 unsigned long vmalloc_size); 979 void opal_free_sg_list(struct opal_sg_list *sg); 980 981 /* 982 * Dump region ID range usable by the OS 983 */ 984 #define OPAL_DUMP_REGION_HOST_START 0x80 985 #define OPAL_DUMP_REGION_LOG_BUF 0x80 986 #define OPAL_DUMP_REGION_HOST_END 0xFF 987 988 #endif /* __ASSEMBLY__ */ 989 990 #endif /* __OPAL_H */ 991