1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * OPAL API definitions. 4 * 5 * Copyright 2011-2015 IBM Corp. 6 */ 7 8 #ifndef __OPAL_API_H 9 #define __OPAL_API_H 10 11 /****** OPAL APIs ******/ 12 13 /* Return codes */ 14 #define OPAL_SUCCESS 0 15 #define OPAL_PARAMETER -1 16 #define OPAL_BUSY -2 17 #define OPAL_PARTIAL -3 18 #define OPAL_CONSTRAINED -4 19 #define OPAL_CLOSED -5 20 #define OPAL_HARDWARE -6 21 #define OPAL_UNSUPPORTED -7 22 #define OPAL_PERMISSION -8 23 #define OPAL_NO_MEM -9 24 #define OPAL_RESOURCE -10 25 #define OPAL_INTERNAL_ERROR -11 26 #define OPAL_BUSY_EVENT -12 27 #define OPAL_HARDWARE_FROZEN -13 28 #define OPAL_WRONG_STATE -14 29 #define OPAL_ASYNC_COMPLETION -15 30 #define OPAL_EMPTY -16 31 #define OPAL_I2C_TIMEOUT -17 32 #define OPAL_I2C_INVALID_CMD -18 33 #define OPAL_I2C_LBUS_PARITY -19 34 #define OPAL_I2C_BKEND_OVERRUN -20 35 #define OPAL_I2C_BKEND_ACCESS -21 36 #define OPAL_I2C_ARBT_LOST -22 37 #define OPAL_I2C_NACK_RCVD -23 38 #define OPAL_I2C_STOP_ERR -24 39 #define OPAL_XIVE_PROVISIONING -31 40 #define OPAL_XIVE_FREE_ACTIVE -32 41 #define OPAL_TIMEOUT -33 42 43 /* API Tokens (in r0) */ 44 #define OPAL_INVALID_CALL -1 45 #define OPAL_TEST 0 46 #define OPAL_CONSOLE_WRITE 1 47 #define OPAL_CONSOLE_READ 2 48 #define OPAL_RTC_READ 3 49 #define OPAL_RTC_WRITE 4 50 #define OPAL_CEC_POWER_DOWN 5 51 #define OPAL_CEC_REBOOT 6 52 #define OPAL_READ_NVRAM 7 53 #define OPAL_WRITE_NVRAM 8 54 #define OPAL_HANDLE_INTERRUPT 9 55 #define OPAL_POLL_EVENTS 10 56 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 57 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 58 #define OPAL_PCI_CONFIG_READ_BYTE 13 59 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 60 #define OPAL_PCI_CONFIG_READ_WORD 15 61 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 62 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 63 #define OPAL_PCI_CONFIG_WRITE_WORD 18 64 #define OPAL_SET_XIVE 19 65 #define OPAL_GET_XIVE 20 66 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 67 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 68 #define OPAL_PCI_EEH_FREEZE_STATUS 23 69 #define OPAL_PCI_SHPC 24 70 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 71 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 72 #define OPAL_PCI_PHB_MMIO_ENABLE 27 73 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 74 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 75 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 76 #define OPAL_PCI_SET_PE 31 77 #define OPAL_PCI_SET_PELTV 32 78 #define OPAL_PCI_SET_MVE 33 79 #define OPAL_PCI_SET_MVE_ENABLE 34 80 #define OPAL_PCI_GET_XIVE_REISSUE 35 81 #define OPAL_PCI_SET_XIVE_REISSUE 36 82 #define OPAL_PCI_SET_XIVE_PE 37 83 #define OPAL_GET_XIVE_SOURCE 38 84 #define OPAL_GET_MSI_32 39 85 #define OPAL_GET_MSI_64 40 86 #define OPAL_START_CPU 41 87 #define OPAL_QUERY_CPU_STATUS 42 88 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ 89 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 90 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 91 #define OPAL_PCI_RESET 49 92 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 93 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 94 #define OPAL_PCI_FENCE_PHB 52 95 #define OPAL_PCI_REINIT 53 96 #define OPAL_PCI_MASK_PE_ERROR 54 97 #define OPAL_SET_SLOT_LED_STATUS 55 98 #define OPAL_GET_EPOW_STATUS 56 99 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 100 #define OPAL_RESERVED1 58 101 #define OPAL_RESERVED2 59 102 #define OPAL_PCI_NEXT_ERROR 60 103 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 104 #define OPAL_PCI_POLL 62 105 #define OPAL_PCI_MSI_EOI 63 106 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 107 #define OPAL_XSCOM_READ 65 108 #define OPAL_XSCOM_WRITE 66 109 #define OPAL_LPC_READ 67 110 #define OPAL_LPC_WRITE 68 111 #define OPAL_RETURN_CPU 69 112 #define OPAL_REINIT_CPUS 70 113 #define OPAL_ELOG_READ 71 114 #define OPAL_ELOG_WRITE 72 115 #define OPAL_ELOG_ACK 73 116 #define OPAL_ELOG_RESEND 74 117 #define OPAL_ELOG_SIZE 75 118 #define OPAL_FLASH_VALIDATE 76 119 #define OPAL_FLASH_MANAGE 77 120 #define OPAL_FLASH_UPDATE 78 121 #define OPAL_RESYNC_TIMEBASE 79 122 #define OPAL_CHECK_TOKEN 80 123 #define OPAL_DUMP_INIT 81 124 #define OPAL_DUMP_INFO 82 125 #define OPAL_DUMP_READ 83 126 #define OPAL_DUMP_ACK 84 127 #define OPAL_GET_MSG 85 128 #define OPAL_CHECK_ASYNC_COMPLETION 86 129 #define OPAL_SYNC_HOST_REBOOT 87 130 #define OPAL_SENSOR_READ 88 131 #define OPAL_GET_PARAM 89 132 #define OPAL_SET_PARAM 90 133 #define OPAL_DUMP_RESEND 91 134 #define OPAL_ELOG_SEND 92 /* Deprecated */ 135 #define OPAL_PCI_SET_PHB_CAPI_MODE 93 136 #define OPAL_DUMP_INFO2 94 137 #define OPAL_WRITE_OPPANEL_ASYNC 95 138 #define OPAL_PCI_ERR_INJECT 96 139 #define OPAL_PCI_EEH_FREEZE_SET 97 140 #define OPAL_HANDLE_HMI 98 141 #define OPAL_CONFIG_CPU_IDLE_STATE 99 142 #define OPAL_SLW_SET_REG 100 143 #define OPAL_REGISTER_DUMP_REGION 101 144 #define OPAL_UNREGISTER_DUMP_REGION 102 145 #define OPAL_WRITE_TPO 103 146 #define OPAL_READ_TPO 104 147 #define OPAL_GET_DPO_STATUS 105 148 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ 149 #define OPAL_IPMI_SEND 107 150 #define OPAL_IPMI_RECV 108 151 #define OPAL_I2C_REQUEST 109 152 #define OPAL_FLASH_READ 110 153 #define OPAL_FLASH_WRITE 111 154 #define OPAL_FLASH_ERASE 112 155 #define OPAL_PRD_MSG 113 156 #define OPAL_LEDS_GET_INDICATOR 114 157 #define OPAL_LEDS_SET_INDICATOR 115 158 #define OPAL_CEC_REBOOT2 116 159 #define OPAL_CONSOLE_FLUSH 117 160 #define OPAL_GET_DEVICE_TREE 118 161 #define OPAL_PCI_GET_PRESENCE_STATE 119 162 #define OPAL_PCI_GET_POWER_STATE 120 163 #define OPAL_PCI_SET_POWER_STATE 121 164 #define OPAL_INT_GET_XIRR 122 165 #define OPAL_INT_SET_CPPR 123 166 #define OPAL_INT_EOI 124 167 #define OPAL_INT_SET_MFRR 125 168 #define OPAL_PCI_TCE_KILL 126 169 #define OPAL_NMMU_SET_PTCR 127 170 #define OPAL_XIVE_RESET 128 171 #define OPAL_XIVE_GET_IRQ_INFO 129 172 #define OPAL_XIVE_GET_IRQ_CONFIG 130 173 #define OPAL_XIVE_SET_IRQ_CONFIG 131 174 #define OPAL_XIVE_GET_QUEUE_INFO 132 175 #define OPAL_XIVE_SET_QUEUE_INFO 133 176 #define OPAL_XIVE_DONATE_PAGE 134 177 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135 178 #define OPAL_XIVE_FREE_VP_BLOCK 136 179 #define OPAL_XIVE_GET_VP_INFO 137 180 #define OPAL_XIVE_SET_VP_INFO 138 181 #define OPAL_XIVE_ALLOCATE_IRQ 139 182 #define OPAL_XIVE_FREE_IRQ 140 183 #define OPAL_XIVE_SYNC 141 184 #define OPAL_XIVE_DUMP 142 185 #define OPAL_XIVE_GET_QUEUE_STATE 143 186 #define OPAL_XIVE_SET_QUEUE_STATE 144 187 #define OPAL_SIGNAL_SYSTEM_RESET 145 188 #define OPAL_NPU_INIT_CONTEXT 146 189 #define OPAL_NPU_DESTROY_CONTEXT 147 190 #define OPAL_NPU_MAP_LPAR 148 191 #define OPAL_IMC_COUNTERS_INIT 149 192 #define OPAL_IMC_COUNTERS_START 150 193 #define OPAL_IMC_COUNTERS_STOP 151 194 #define OPAL_GET_POWERCAP 152 195 #define OPAL_SET_POWERCAP 153 196 #define OPAL_GET_POWER_SHIFT_RATIO 154 197 #define OPAL_SET_POWER_SHIFT_RATIO 155 198 #define OPAL_SENSOR_GROUP_CLEAR 156 199 #define OPAL_PCI_SET_P2P 157 200 #define OPAL_QUIESCE 158 201 #define OPAL_NPU_SPA_SETUP 159 202 #define OPAL_NPU_SPA_CLEAR_CACHE 160 203 #define OPAL_NPU_TL_SET 161 204 #define OPAL_SENSOR_READ_U64 162 205 #define OPAL_SENSOR_GROUP_ENABLE 163 206 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164 207 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165 208 #define OPAL_HANDLE_HMI2 166 209 #define OPAL_NX_COPROC_INIT 167 210 #define OPAL_XIVE_GET_VP_STATE 170 211 #define OPAL_LAST 170 212 213 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ 214 #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ 215 #define QUIESCE_LOCK_BREAK 3 /* Set to ignore locks. */ 216 #define QUIESCE_RESUME 4 /* Un-quiesce */ 217 #define QUIESCE_RESUME_FAST_REBOOT 5 /* Un-quiesce, fast reboot */ 218 219 /* Device tree flags */ 220 221 /* 222 * Flags set in power-mgmt nodes in device tree describing 223 * idle states that are supported in the platform. 224 */ 225 226 #define OPAL_PM_TIMEBASE_STOP 0x00000002 227 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000 228 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000 229 #define OPAL_PM_NAP_ENABLED 0x00010000 230 #define OPAL_PM_SLEEP_ENABLED 0x00020000 231 #define OPAL_PM_WINKLE_ENABLED 0x00040000 232 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ 233 #define OPAL_PM_STOP_INST_FAST 0x00100000 234 #define OPAL_PM_STOP_INST_DEEP 0x00200000 235 236 /* 237 * OPAL_CONFIG_CPU_IDLE_STATE parameters 238 */ 239 #define OPAL_CONFIG_IDLE_FASTSLEEP 1 240 #define OPAL_CONFIG_IDLE_UNDO 0 241 #define OPAL_CONFIG_IDLE_APPLY 1 242 243 #ifndef __ASSEMBLY__ 244 245 /* Other enums */ 246 enum OpalFreezeState { 247 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 248 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 249 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 250 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 251 OPAL_EEH_STOPPED_RESET = 4, 252 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 253 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 254 }; 255 256 enum OpalEehFreezeActionToken { 257 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 258 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 259 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 260 261 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 262 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 263 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 264 }; 265 266 enum OpalPciStatusToken { 267 OPAL_EEH_NO_ERROR = 0, 268 OPAL_EEH_IOC_ERROR = 1, 269 OPAL_EEH_PHB_ERROR = 2, 270 OPAL_EEH_PE_ERROR = 3, 271 OPAL_EEH_PE_MMIO_ERROR = 4, 272 OPAL_EEH_PE_DMA_ERROR = 5 273 }; 274 275 enum OpalPciErrorSeverity { 276 OPAL_EEH_SEV_NO_ERROR = 0, 277 OPAL_EEH_SEV_IOC_DEAD = 1, 278 OPAL_EEH_SEV_PHB_DEAD = 2, 279 OPAL_EEH_SEV_PHB_FENCED = 3, 280 OPAL_EEH_SEV_PE_ER = 4, 281 OPAL_EEH_SEV_INF = 5 282 }; 283 284 enum OpalErrinjectType { 285 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, 286 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, 287 }; 288 289 enum OpalErrinjectFunc { 290 /* IOA bus specific errors */ 291 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, 292 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, 293 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, 294 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, 295 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, 296 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, 297 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, 298 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, 299 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, 300 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, 301 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, 302 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, 303 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, 304 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, 305 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, 306 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, 307 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, 308 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, 309 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, 310 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, 311 }; 312 313 enum OpalMmioWindowType { 314 OPAL_M32_WINDOW_TYPE = 1, 315 OPAL_M64_WINDOW_TYPE = 2, 316 OPAL_IO_WINDOW_TYPE = 3 317 }; 318 319 enum OpalExceptionHandler { 320 OPAL_MACHINE_CHECK_HANDLER = 1, 321 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 322 OPAL_SOFTPATCH_HANDLER = 3 323 }; 324 325 enum OpalPendingState { 326 OPAL_EVENT_OPAL_INTERNAL = 0x1, 327 OPAL_EVENT_NVRAM = 0x2, 328 OPAL_EVENT_RTC = 0x4, 329 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 330 OPAL_EVENT_CONSOLE_INPUT = 0x10, 331 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 332 OPAL_EVENT_ERROR_LOG = 0x40, 333 OPAL_EVENT_EPOW = 0x80, 334 OPAL_EVENT_LED_STATUS = 0x100, 335 OPAL_EVENT_PCI_ERROR = 0x200, 336 OPAL_EVENT_DUMP_AVAIL = 0x400, 337 OPAL_EVENT_MSG_PENDING = 0x800, 338 }; 339 340 enum OpalThreadStatus { 341 OPAL_THREAD_INACTIVE = 0x0, 342 OPAL_THREAD_STARTED = 0x1, 343 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 344 }; 345 346 enum OpalPciBusCompare { 347 OpalPciBusAny = 0, /* Any bus number match */ 348 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 349 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 350 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 351 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 352 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 353 OpalPciBusAll = 7, /* Match bus number exactly */ 354 }; 355 356 enum OpalDeviceCompare { 357 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 358 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 359 }; 360 361 enum OpalFuncCompare { 362 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 363 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 364 }; 365 366 enum OpalPeAction { 367 OPAL_UNMAP_PE = 0, 368 OPAL_MAP_PE = 1 369 }; 370 371 enum OpalPeltvAction { 372 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 373 OPAL_ADD_PE_TO_DOMAIN = 1 374 }; 375 376 enum OpalMveEnableAction { 377 OPAL_DISABLE_MVE = 0, 378 OPAL_ENABLE_MVE = 1 379 }; 380 381 enum OpalM64Action { 382 OPAL_DISABLE_M64 = 0, 383 OPAL_ENABLE_M64_SPLIT = 1, 384 OPAL_ENABLE_M64_NON_SPLIT = 2 385 }; 386 387 enum OpalPciResetScope { 388 OPAL_RESET_PHB_COMPLETE = 1, 389 OPAL_RESET_PCI_LINK = 2, 390 OPAL_RESET_PHB_ERROR = 3, 391 OPAL_RESET_PCI_HOT = 4, 392 OPAL_RESET_PCI_FUNDAMENTAL = 5, 393 OPAL_RESET_PCI_IODA_TABLE = 6 394 }; 395 396 enum OpalPciReinitScope { 397 /* 398 * Note: we chose values that do not overlap 399 * OpalPciResetScope as OPAL v2 used the same 400 * enum for both 401 */ 402 OPAL_REINIT_PCI_DEV = 1000 403 }; 404 405 enum OpalPciResetState { 406 OPAL_DEASSERT_RESET = 0, 407 OPAL_ASSERT_RESET = 1 408 }; 409 410 enum OpalPciSlotPresence { 411 OPAL_PCI_SLOT_EMPTY = 0, 412 OPAL_PCI_SLOT_PRESENT = 1 413 }; 414 415 enum OpalPciSlotPower { 416 OPAL_PCI_SLOT_POWER_OFF = 0, 417 OPAL_PCI_SLOT_POWER_ON = 1, 418 OPAL_PCI_SLOT_OFFLINE = 2, 419 OPAL_PCI_SLOT_ONLINE = 3 420 }; 421 422 enum OpalSlotLedType { 423 OPAL_SLOT_LED_TYPE_ID = 0, /* IDENTIFY LED */ 424 OPAL_SLOT_LED_TYPE_FAULT = 1, /* FAULT LED */ 425 OPAL_SLOT_LED_TYPE_ATTN = 2, /* System Attention LED */ 426 OPAL_SLOT_LED_TYPE_MAX = 3 427 }; 428 429 enum OpalSlotLedState { 430 OPAL_SLOT_LED_STATE_OFF = 0, /* LED is OFF */ 431 OPAL_SLOT_LED_STATE_ON = 1 /* LED is ON */ 432 }; 433 434 /* 435 * Address cycle types for LPC accesses. These also correspond 436 * to the content of the first cell of the "reg" property for 437 * device nodes on the LPC bus 438 */ 439 enum OpalLPCAddressType { 440 OPAL_LPC_MEM = 0, 441 OPAL_LPC_IO = 1, 442 OPAL_LPC_FW = 2, 443 }; 444 445 enum opal_msg_type { 446 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 447 * additional params function-specific 448 */ 449 OPAL_MSG_MEM_ERR = 1, 450 OPAL_MSG_EPOW = 2, 451 OPAL_MSG_SHUTDOWN = 3, /* params[0] = 1 reboot, 0 shutdown */ 452 OPAL_MSG_HMI_EVT = 4, 453 OPAL_MSG_DPO = 5, 454 OPAL_MSG_PRD = 6, 455 OPAL_MSG_OCC = 7, 456 OPAL_MSG_TYPE_MAX, 457 }; 458 459 struct opal_msg { 460 __be32 msg_type; 461 __be32 reserved; 462 __be64 params[8]; 463 }; 464 465 /* System parameter permission */ 466 enum OpalSysparamPerm { 467 OPAL_SYSPARAM_READ = 0x1, 468 OPAL_SYSPARAM_WRITE = 0x2, 469 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 470 }; 471 472 enum { 473 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, 474 }; 475 476 struct opal_ipmi_msg { 477 uint8_t version; 478 uint8_t netfn; 479 uint8_t cmd; 480 uint8_t data[]; 481 }; 482 483 /* FSP memory errors handling */ 484 enum OpalMemErr_Version { 485 OpalMemErr_V1 = 1, 486 }; 487 488 enum OpalMemErrType { 489 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 490 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 491 }; 492 493 /* Memory Reilience error type */ 494 enum OpalMemErr_ResilErrType { 495 OPAL_MEM_RESILIENCE_CE = 0, 496 OPAL_MEM_RESILIENCE_UE, 497 OPAL_MEM_RESILIENCE_UE_SCRUB, 498 }; 499 500 /* Dynamic Memory Deallocation type */ 501 enum OpalMemErr_DynErrType { 502 OPAL_MEM_DYNAMIC_DEALLOC = 0, 503 }; 504 505 struct OpalMemoryErrorData { 506 enum OpalMemErr_Version version:8; /* 0x00 */ 507 enum OpalMemErrType type:8; /* 0x01 */ 508 __be16 flags; /* 0x02 */ 509 uint8_t reserved_1[4]; /* 0x04 */ 510 511 union { 512 /* Memory Resilience corrected/uncorrected error info */ 513 struct { 514 enum OpalMemErr_ResilErrType resil_err_type:8; 515 uint8_t reserved_1[7]; 516 __be64 physical_address_start; 517 __be64 physical_address_end; 518 } resilience; 519 /* Dynamic memory deallocation error info */ 520 struct { 521 enum OpalMemErr_DynErrType dyn_err_type:8; 522 uint8_t reserved_1[7]; 523 __be64 physical_address_start; 524 __be64 physical_address_end; 525 } dyn_dealloc; 526 } u; 527 }; 528 529 /* HMI interrupt event */ 530 enum OpalHMI_Version { 531 OpalHMIEvt_V1 = 1, 532 OpalHMIEvt_V2 = 2, 533 }; 534 535 enum OpalHMI_Severity { 536 OpalHMI_SEV_NO_ERROR = 0, 537 OpalHMI_SEV_WARNING = 1, 538 OpalHMI_SEV_ERROR_SYNC = 2, 539 OpalHMI_SEV_FATAL = 3, 540 }; 541 542 enum OpalHMI_Disposition { 543 OpalHMI_DISPOSITION_RECOVERED = 0, 544 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 545 }; 546 547 enum OpalHMI_ErrType { 548 OpalHMI_ERROR_MALFUNC_ALERT = 0, 549 OpalHMI_ERROR_PROC_RECOV_DONE, 550 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 551 OpalHMI_ERROR_PROC_RECOV_MASKED, 552 OpalHMI_ERROR_TFAC, 553 OpalHMI_ERROR_TFMR_PARITY, 554 OpalHMI_ERROR_HA_OVERFLOW_WARN, 555 OpalHMI_ERROR_XSCOM_FAIL, 556 OpalHMI_ERROR_XSCOM_DONE, 557 OpalHMI_ERROR_SCOM_FIR, 558 OpalHMI_ERROR_DEBUG_TRIG_FIR, 559 OpalHMI_ERROR_HYP_RESOURCE, 560 OpalHMI_ERROR_CAPP_RECOVERY, 561 }; 562 563 enum OpalHMI_XstopType { 564 CHECKSTOP_TYPE_UNKNOWN = 0, 565 CHECKSTOP_TYPE_CORE = 1, 566 CHECKSTOP_TYPE_NX = 2, 567 CHECKSTOP_TYPE_NPU = 3 568 }; 569 570 enum OpalHMI_CoreXstopReason { 571 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001, 572 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002, 573 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004, 574 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008, 575 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010, 576 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020, 577 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040, 578 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080, 579 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100, 580 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200, 581 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400, 582 CORE_CHECKSTOP_PC_LOGIC = 0x00000800, 583 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000, 584 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000, 585 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000, 586 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000, 587 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000, 588 }; 589 590 enum OpalHMI_NestAccelXstopReason { 591 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001, 592 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002, 593 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004, 594 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008, 595 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010, 596 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020, 597 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040, 598 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080, 599 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100, 600 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200, 601 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400, 602 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800, 603 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000, 604 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000, 605 }; 606 607 struct OpalHMIEvent { 608 uint8_t version; /* 0x00 */ 609 uint8_t severity; /* 0x01 */ 610 uint8_t type; /* 0x02 */ 611 uint8_t disposition; /* 0x03 */ 612 uint8_t reserved_1[4]; /* 0x04 */ 613 614 __be64 hmer; 615 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 616 __be64 tfmr; 617 618 /* version 2 and later */ 619 union { 620 /* 621 * checkstop info (Core/NX). 622 * Valid for OpalHMI_ERROR_MALFUNC_ALERT. 623 */ 624 struct { 625 uint8_t xstop_type; /* enum OpalHMI_XstopType */ 626 uint8_t reserved_1[3]; 627 __be32 xstop_reason; 628 union { 629 __be32 pir; /* for CHECKSTOP_TYPE_CORE */ 630 __be32 chip_id; /* for CHECKSTOP_TYPE_NX */ 631 } u; 632 } xstop_error; 633 } u; 634 }; 635 636 /* OPAL_HANDLE_HMI2 out_flags */ 637 enum { 638 OPAL_HMI_FLAGS_TB_RESYNC = (1ull << 0), /* Timebase has been resynced */ 639 OPAL_HMI_FLAGS_DEC_LOST = (1ull << 1), /* DEC lost, needs to be reprogrammed */ 640 OPAL_HMI_FLAGS_HDEC_LOST = (1ull << 2), /* HDEC lost, needs to be reprogrammed */ 641 OPAL_HMI_FLAGS_TOD_TB_FAIL = (1ull << 3), /* TOD/TB recovery failed. */ 642 OPAL_HMI_FLAGS_NEW_EVENT = (1ull << 63), /* An event has been created */ 643 }; 644 645 enum { 646 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 647 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 648 OPAL_P7IOC_DIAG_TYPE_BI = 2, 649 OPAL_P7IOC_DIAG_TYPE_CI = 3, 650 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 651 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 652 OPAL_P7IOC_DIAG_TYPE_LAST = 6 653 }; 654 655 struct OpalIoP7IOCErrorData { 656 __be16 type; 657 658 /* GEM */ 659 __be64 gemXfir; 660 __be64 gemRfir; 661 __be64 gemRirqfir; 662 __be64 gemMask; 663 __be64 gemRwof; 664 665 /* LEM */ 666 __be64 lemFir; 667 __be64 lemErrMask; 668 __be64 lemAction0; 669 __be64 lemAction1; 670 __be64 lemWof; 671 672 union { 673 struct OpalIoP7IOCRgcErrorData { 674 __be64 rgcStatus; /* 3E1C10 */ 675 __be64 rgcLdcp; /* 3E1C18 */ 676 }rgc; 677 struct OpalIoP7IOCBiErrorData { 678 __be64 biLdcp0; /* 3C0100, 3C0118 */ 679 __be64 biLdcp1; /* 3C0108, 3C0120 */ 680 __be64 biLdcp2; /* 3C0110, 3C0128 */ 681 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 682 683 uint8_t biDownbound; /* BI Downbound or Upbound */ 684 }bi; 685 struct OpalIoP7IOCCiErrorData { 686 __be64 ciPortStatus; /* 3Dn008 */ 687 __be64 ciPortLdcp; /* 3Dn010 */ 688 689 uint8_t ciPort; /* Index of CI port: 0/1 */ 690 }ci; 691 }; 692 }; 693 694 /** 695 * This structure defines the overlay which will be used to store PHB error 696 * data upon request. 697 */ 698 enum { 699 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 700 }; 701 702 enum { 703 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 704 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2, 705 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3 706 }; 707 708 enum { 709 OPAL_P7IOC_NUM_PEST_REGS = 128, 710 OPAL_PHB3_NUM_PEST_REGS = 256, 711 OPAL_PHB4_NUM_PEST_REGS = 512 712 }; 713 714 struct OpalIoPhbErrorCommon { 715 __be32 version; 716 __be32 ioType; 717 __be32 len; 718 }; 719 720 struct OpalIoP7IOCPhbErrorData { 721 struct OpalIoPhbErrorCommon common; 722 723 __be32 brdgCtl; 724 725 // P7IOC utl regs 726 __be32 portStatusReg; 727 __be32 rootCmplxStatus; 728 __be32 busAgentStatus; 729 730 // P7IOC cfg regs 731 __be32 deviceStatus; 732 __be32 slotStatus; 733 __be32 linkStatus; 734 __be32 devCmdStatus; 735 __be32 devSecStatus; 736 737 // cfg AER regs 738 __be32 rootErrorStatus; 739 __be32 uncorrErrorStatus; 740 __be32 corrErrorStatus; 741 __be32 tlpHdr1; 742 __be32 tlpHdr2; 743 __be32 tlpHdr3; 744 __be32 tlpHdr4; 745 __be32 sourceId; 746 747 __be32 rsv3; 748 749 // Record data about the call to allocate a buffer. 750 __be64 errorClass; 751 __be64 correlator; 752 753 //P7IOC MMIO Error Regs 754 __be64 p7iocPlssr; // n120 755 __be64 p7iocCsr; // n110 756 __be64 lemFir; // nC00 757 __be64 lemErrorMask; // nC18 758 __be64 lemWOF; // nC40 759 __be64 phbErrorStatus; // nC80 760 __be64 phbFirstErrorStatus; // nC88 761 __be64 phbErrorLog0; // nCC0 762 __be64 phbErrorLog1; // nCC8 763 __be64 mmioErrorStatus; // nD00 764 __be64 mmioFirstErrorStatus; // nD08 765 __be64 mmioErrorLog0; // nD40 766 __be64 mmioErrorLog1; // nD48 767 __be64 dma0ErrorStatus; // nD80 768 __be64 dma0FirstErrorStatus; // nD88 769 __be64 dma0ErrorLog0; // nDC0 770 __be64 dma0ErrorLog1; // nDC8 771 __be64 dma1ErrorStatus; // nE00 772 __be64 dma1FirstErrorStatus; // nE08 773 __be64 dma1ErrorLog0; // nE40 774 __be64 dma1ErrorLog1; // nE48 775 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 776 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 777 }; 778 779 struct OpalIoPhb3ErrorData { 780 struct OpalIoPhbErrorCommon common; 781 782 __be32 brdgCtl; 783 784 /* PHB3 UTL regs */ 785 __be32 portStatusReg; 786 __be32 rootCmplxStatus; 787 __be32 busAgentStatus; 788 789 /* PHB3 cfg regs */ 790 __be32 deviceStatus; 791 __be32 slotStatus; 792 __be32 linkStatus; 793 __be32 devCmdStatus; 794 __be32 devSecStatus; 795 796 /* cfg AER regs */ 797 __be32 rootErrorStatus; 798 __be32 uncorrErrorStatus; 799 __be32 corrErrorStatus; 800 __be32 tlpHdr1; 801 __be32 tlpHdr2; 802 __be32 tlpHdr3; 803 __be32 tlpHdr4; 804 __be32 sourceId; 805 806 __be32 rsv3; 807 808 /* Record data about the call to allocate a buffer */ 809 __be64 errorClass; 810 __be64 correlator; 811 812 /* PHB3 MMIO Error Regs */ 813 __be64 nFir; /* 000 */ 814 __be64 nFirMask; /* 003 */ 815 __be64 nFirWOF; /* 008 */ 816 __be64 phbPlssr; /* 120 */ 817 __be64 phbCsr; /* 110 */ 818 __be64 lemFir; /* C00 */ 819 __be64 lemErrorMask; /* C18 */ 820 __be64 lemWOF; /* C40 */ 821 __be64 phbErrorStatus; /* C80 */ 822 __be64 phbFirstErrorStatus; /* C88 */ 823 __be64 phbErrorLog0; /* CC0 */ 824 __be64 phbErrorLog1; /* CC8 */ 825 __be64 mmioErrorStatus; /* D00 */ 826 __be64 mmioFirstErrorStatus; /* D08 */ 827 __be64 mmioErrorLog0; /* D40 */ 828 __be64 mmioErrorLog1; /* D48 */ 829 __be64 dma0ErrorStatus; /* D80 */ 830 __be64 dma0FirstErrorStatus; /* D88 */ 831 __be64 dma0ErrorLog0; /* DC0 */ 832 __be64 dma0ErrorLog1; /* DC8 */ 833 __be64 dma1ErrorStatus; /* E00 */ 834 __be64 dma1FirstErrorStatus; /* E08 */ 835 __be64 dma1ErrorLog0; /* E40 */ 836 __be64 dma1ErrorLog1; /* E48 */ 837 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 838 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 839 }; 840 841 struct OpalIoPhb4ErrorData { 842 struct OpalIoPhbErrorCommon common; 843 844 __be32 brdgCtl; 845 846 /* PHB4 cfg regs */ 847 __be32 deviceStatus; 848 __be32 slotStatus; 849 __be32 linkStatus; 850 __be32 devCmdStatus; 851 __be32 devSecStatus; 852 853 /* cfg AER regs */ 854 __be32 rootErrorStatus; 855 __be32 uncorrErrorStatus; 856 __be32 corrErrorStatus; 857 __be32 tlpHdr1; 858 __be32 tlpHdr2; 859 __be32 tlpHdr3; 860 __be32 tlpHdr4; 861 __be32 sourceId; 862 863 /* PHB4 ETU Error Regs */ 864 __be64 nFir; /* 000 */ 865 __be64 nFirMask; /* 003 */ 866 __be64 nFirWOF; /* 008 */ 867 __be64 phbPlssr; /* 120 */ 868 __be64 phbCsr; /* 110 */ 869 __be64 lemFir; /* C00 */ 870 __be64 lemErrorMask; /* C18 */ 871 __be64 lemWOF; /* C40 */ 872 __be64 phbErrorStatus; /* C80 */ 873 __be64 phbFirstErrorStatus; /* C88 */ 874 __be64 phbErrorLog0; /* CC0 */ 875 __be64 phbErrorLog1; /* CC8 */ 876 __be64 phbTxeErrorStatus; /* D00 */ 877 __be64 phbTxeFirstErrorStatus; /* D08 */ 878 __be64 phbTxeErrorLog0; /* D40 */ 879 __be64 phbTxeErrorLog1; /* D48 */ 880 __be64 phbRxeArbErrorStatus; /* D80 */ 881 __be64 phbRxeArbFirstErrorStatus; /* D88 */ 882 __be64 phbRxeArbErrorLog0; /* DC0 */ 883 __be64 phbRxeArbErrorLog1; /* DC8 */ 884 __be64 phbRxeMrgErrorStatus; /* E00 */ 885 __be64 phbRxeMrgFirstErrorStatus; /* E08 */ 886 __be64 phbRxeMrgErrorLog0; /* E40 */ 887 __be64 phbRxeMrgErrorLog1; /* E48 */ 888 __be64 phbRxeTceErrorStatus; /* E80 */ 889 __be64 phbRxeTceFirstErrorStatus; /* E88 */ 890 __be64 phbRxeTceErrorLog0; /* EC0 */ 891 __be64 phbRxeTceErrorLog1; /* EC8 */ 892 893 /* PHB4 REGB Error Regs */ 894 __be64 phbPblErrorStatus; /* 1900 */ 895 __be64 phbPblFirstErrorStatus; /* 1908 */ 896 __be64 phbPblErrorLog0; /* 1940 */ 897 __be64 phbPblErrorLog1; /* 1948 */ 898 __be64 phbPcieDlpErrorLog1; /* 1AA0 */ 899 __be64 phbPcieDlpErrorLog2; /* 1AA8 */ 900 __be64 phbPcieDlpErrorStatus; /* 1AB0 */ 901 __be64 phbRegbErrorStatus; /* 1C00 */ 902 __be64 phbRegbFirstErrorStatus; /* 1C08 */ 903 __be64 phbRegbErrorLog0; /* 1C40 */ 904 __be64 phbRegbErrorLog1; /* 1C48 */ 905 906 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS]; 907 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS]; 908 }; 909 910 enum { 911 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 912 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 913 914 /* These two define the base MMU mode of the host on P9 915 * 916 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still 917 * create hash guests in "radix" mode with care (full core 918 * switch only). 919 */ 920 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2), 921 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3), 922 923 OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4), 924 }; 925 926 typedef struct oppanel_line { 927 __be64 line; 928 __be64 line_len; 929 } oppanel_line_t; 930 931 enum opal_prd_msg_type { 932 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */ 933 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */ 934 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */ 935 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */ 936 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */ 937 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */ 938 }; 939 940 struct opal_prd_msg_header { 941 uint8_t type; 942 uint8_t pad[1]; 943 __be16 size; 944 }; 945 946 struct opal_prd_msg; 947 948 #define OCC_RESET 0 949 #define OCC_LOAD 1 950 #define OCC_THROTTLE 2 951 #define OCC_MAX_THROTTLE_STATUS 5 952 953 struct opal_occ_msg { 954 __be64 type; 955 __be64 chip; 956 __be64 throttle_status; 957 }; 958 959 /* 960 * SG entries 961 * 962 * WARNING: The current implementation requires each entry 963 * to represent a block that is 4k aligned *and* each block 964 * size except the last one in the list to be as well. 965 */ 966 struct opal_sg_entry { 967 __be64 data; 968 __be64 length; 969 }; 970 971 /* 972 * Candidate image SG list. 973 * 974 * length = VER | length 975 */ 976 struct opal_sg_list { 977 __be64 length; 978 __be64 next; 979 struct opal_sg_entry entry[]; 980 }; 981 982 /* 983 * Dump region ID range usable by the OS 984 */ 985 #define OPAL_DUMP_REGION_HOST_START 0x80 986 #define OPAL_DUMP_REGION_LOG_BUF 0x80 987 #define OPAL_DUMP_REGION_HOST_END 0xFF 988 989 /* CAPI modes for PHB */ 990 enum { 991 OPAL_PHB_CAPI_MODE_PCIE = 0, 992 OPAL_PHB_CAPI_MODE_CAPI = 1, 993 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, 994 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, 995 OPAL_PHB_CAPI_MODE_DMA = 4, 996 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5, 997 }; 998 999 /* OPAL I2C request */ 1000 struct opal_i2c_request { 1001 uint8_t type; 1002 #define OPAL_I2C_RAW_READ 0 1003 #define OPAL_I2C_RAW_WRITE 1 1004 #define OPAL_I2C_SM_READ 2 1005 #define OPAL_I2C_SM_WRITE 3 1006 uint8_t flags; 1007 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ 1008 uint8_t subaddr_sz; /* Max 4 */ 1009 uint8_t reserved; 1010 __be16 addr; /* 7 or 10 bit address */ 1011 __be16 reserved2; 1012 __be32 subaddr; /* Sub-address if any */ 1013 __be32 size; /* Data size */ 1014 __be64 buffer_ra; /* Buffer real address */ 1015 }; 1016 1017 /* 1018 * EPOW status sharing (OPAL and the host) 1019 * 1020 * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX 1021 * with individual elements being 16 bits wide to fetch the system 1022 * wide EPOW status. Each element in the buffer will contain the 1023 * EPOW status in it's bit representation for a particular EPOW sub 1024 * class as defined here. So multiple detailed EPOW status bits 1025 * specific for any sub class can be represented in a single buffer 1026 * element as it's bit representation. 1027 */ 1028 1029 /* System EPOW type */ 1030 enum OpalSysEpow { 1031 OPAL_SYSEPOW_POWER = 0, /* Power EPOW */ 1032 OPAL_SYSEPOW_TEMP = 1, /* Temperature EPOW */ 1033 OPAL_SYSEPOW_COOLING = 2, /* Cooling EPOW */ 1034 OPAL_SYSEPOW_MAX = 3, /* Max EPOW categories */ 1035 }; 1036 1037 /* Power EPOW */ 1038 enum OpalSysPower { 1039 OPAL_SYSPOWER_UPS = 0x0001, /* System on UPS power */ 1040 OPAL_SYSPOWER_CHNG = 0x0002, /* System power config change */ 1041 OPAL_SYSPOWER_FAIL = 0x0004, /* System impending power failure */ 1042 OPAL_SYSPOWER_INCL = 0x0008, /* System incomplete power */ 1043 }; 1044 1045 /* Temperature EPOW */ 1046 enum OpalSysTemp { 1047 OPAL_SYSTEMP_AMB = 0x0001, /* System over ambient temperature */ 1048 OPAL_SYSTEMP_INT = 0x0002, /* System over internal temperature */ 1049 OPAL_SYSTEMP_HMD = 0x0004, /* System over ambient humidity */ 1050 }; 1051 1052 /* Cooling EPOW */ 1053 enum OpalSysCooling { 1054 OPAL_SYSCOOL_INSF = 0x0001, /* System insufficient cooling */ 1055 }; 1056 1057 /* Argument to OPAL_CEC_REBOOT2() */ 1058 enum { 1059 OPAL_REBOOT_NORMAL = 0, 1060 OPAL_REBOOT_PLATFORM_ERROR = 1, 1061 OPAL_REBOOT_FULL_IPL = 2, 1062 }; 1063 1064 /* Argument to OPAL_PCI_TCE_KILL */ 1065 enum { 1066 OPAL_PCI_TCE_KILL_PAGES, 1067 OPAL_PCI_TCE_KILL_PE, 1068 OPAL_PCI_TCE_KILL_ALL, 1069 }; 1070 1071 /* The xive operation mode indicates the active "API" and 1072 * corresponds to the "mode" parameter of the opal_xive_reset() 1073 * call 1074 */ 1075 enum { 1076 OPAL_XIVE_MODE_EMU = 0, 1077 OPAL_XIVE_MODE_EXPL = 1, 1078 }; 1079 1080 /* Flags for OPAL_XIVE_GET_IRQ_INFO */ 1081 enum { 1082 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001, 1083 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002, 1084 OPAL_XIVE_IRQ_LSI = 0x00000004, 1085 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, 1086 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, 1087 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, 1088 }; 1089 1090 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */ 1091 enum { 1092 OPAL_XIVE_EQ_ENABLED = 0x00000001, 1093 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002, 1094 OPAL_XIVE_EQ_ESCALATE = 0x00000004, 1095 }; 1096 1097 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */ 1098 enum { 1099 OPAL_XIVE_VP_ENABLED = 0x00000001, 1100 OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002, 1101 }; 1102 1103 /* "Any chip" replacement for chip ID for allocation functions */ 1104 enum { 1105 OPAL_XIVE_ANY_CHIP = 0xffffffff, 1106 }; 1107 1108 /* Xive sync options */ 1109 enum { 1110 /* This bits are cumulative, arg is a girq */ 1111 XIVE_SYNC_EAS = 0x00000001, /* Sync irq source */ 1112 XIVE_SYNC_QUEUE = 0x00000002, /* Sync irq target */ 1113 }; 1114 1115 /* Dump options */ 1116 enum { 1117 XIVE_DUMP_TM_HYP = 0, 1118 XIVE_DUMP_TM_POOL = 1, 1119 XIVE_DUMP_TM_OS = 2, 1120 XIVE_DUMP_TM_USER = 3, 1121 XIVE_DUMP_VP = 4, 1122 XIVE_DUMP_EMU_STATE = 5, 1123 }; 1124 1125 /* "type" argument options for OPAL_IMC_COUNTERS_* calls */ 1126 enum { 1127 OPAL_IMC_COUNTERS_NEST = 1, 1128 OPAL_IMC_COUNTERS_CORE = 2, 1129 OPAL_IMC_COUNTERS_TRACE = 3, 1130 }; 1131 1132 1133 /* PCI p2p descriptor */ 1134 #define OPAL_PCI_P2P_ENABLE 0x1 1135 #define OPAL_PCI_P2P_LOAD 0x2 1136 #define OPAL_PCI_P2P_STORE 0x4 1137 1138 #endif /* __ASSEMBLY__ */ 1139 1140 #endif /* __OPAL_API_H */ 1141