1 /* 2 * OPAL API definitions. 3 * 4 * Copyright 2011-2015 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #ifndef __OPAL_API_H 13 #define __OPAL_API_H 14 15 /****** OPAL APIs ******/ 16 17 /* Return codes */ 18 #define OPAL_SUCCESS 0 19 #define OPAL_PARAMETER -1 20 #define OPAL_BUSY -2 21 #define OPAL_PARTIAL -3 22 #define OPAL_CONSTRAINED -4 23 #define OPAL_CLOSED -5 24 #define OPAL_HARDWARE -6 25 #define OPAL_UNSUPPORTED -7 26 #define OPAL_PERMISSION -8 27 #define OPAL_NO_MEM -9 28 #define OPAL_RESOURCE -10 29 #define OPAL_INTERNAL_ERROR -11 30 #define OPAL_BUSY_EVENT -12 31 #define OPAL_HARDWARE_FROZEN -13 32 #define OPAL_WRONG_STATE -14 33 #define OPAL_ASYNC_COMPLETION -15 34 #define OPAL_EMPTY -16 35 #define OPAL_I2C_TIMEOUT -17 36 #define OPAL_I2C_INVALID_CMD -18 37 #define OPAL_I2C_LBUS_PARITY -19 38 #define OPAL_I2C_BKEND_OVERRUN -20 39 #define OPAL_I2C_BKEND_ACCESS -21 40 #define OPAL_I2C_ARBT_LOST -22 41 #define OPAL_I2C_NACK_RCVD -23 42 #define OPAL_I2C_STOP_ERR -24 43 44 /* API Tokens (in r0) */ 45 #define OPAL_INVALID_CALL -1 46 #define OPAL_TEST 0 47 #define OPAL_CONSOLE_WRITE 1 48 #define OPAL_CONSOLE_READ 2 49 #define OPAL_RTC_READ 3 50 #define OPAL_RTC_WRITE 4 51 #define OPAL_CEC_POWER_DOWN 5 52 #define OPAL_CEC_REBOOT 6 53 #define OPAL_READ_NVRAM 7 54 #define OPAL_WRITE_NVRAM 8 55 #define OPAL_HANDLE_INTERRUPT 9 56 #define OPAL_POLL_EVENTS 10 57 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11 58 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12 59 #define OPAL_PCI_CONFIG_READ_BYTE 13 60 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14 61 #define OPAL_PCI_CONFIG_READ_WORD 15 62 #define OPAL_PCI_CONFIG_WRITE_BYTE 16 63 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17 64 #define OPAL_PCI_CONFIG_WRITE_WORD 18 65 #define OPAL_SET_XIVE 19 66 #define OPAL_GET_XIVE 20 67 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */ 68 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22 69 #define OPAL_PCI_EEH_FREEZE_STATUS 23 70 #define OPAL_PCI_SHPC 24 71 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25 72 #define OPAL_PCI_EEH_FREEZE_CLEAR 26 73 #define OPAL_PCI_PHB_MMIO_ENABLE 27 74 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 75 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29 76 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30 77 #define OPAL_PCI_SET_PE 31 78 #define OPAL_PCI_SET_PELTV 32 79 #define OPAL_PCI_SET_MVE 33 80 #define OPAL_PCI_SET_MVE_ENABLE 34 81 #define OPAL_PCI_GET_XIVE_REISSUE 35 82 #define OPAL_PCI_SET_XIVE_REISSUE 36 83 #define OPAL_PCI_SET_XIVE_PE 37 84 #define OPAL_GET_XIVE_SOURCE 38 85 #define OPAL_GET_MSI_32 39 86 #define OPAL_GET_MSI_64 40 87 #define OPAL_START_CPU 41 88 #define OPAL_QUERY_CPU_STATUS 42 89 #define OPAL_WRITE_OPPANEL 43 /* unimplemented */ 90 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44 91 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45 92 #define OPAL_PCI_RESET 49 93 #define OPAL_PCI_GET_HUB_DIAG_DATA 50 94 #define OPAL_PCI_GET_PHB_DIAG_DATA 51 95 #define OPAL_PCI_FENCE_PHB 52 96 #define OPAL_PCI_REINIT 53 97 #define OPAL_PCI_MASK_PE_ERROR 54 98 #define OPAL_SET_SLOT_LED_STATUS 55 99 #define OPAL_GET_EPOW_STATUS 56 100 #define OPAL_SET_SYSTEM_ATTENTION_LED 57 101 #define OPAL_RESERVED1 58 102 #define OPAL_RESERVED2 59 103 #define OPAL_PCI_NEXT_ERROR 60 104 #define OPAL_PCI_EEH_FREEZE_STATUS2 61 105 #define OPAL_PCI_POLL 62 106 #define OPAL_PCI_MSI_EOI 63 107 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64 108 #define OPAL_XSCOM_READ 65 109 #define OPAL_XSCOM_WRITE 66 110 #define OPAL_LPC_READ 67 111 #define OPAL_LPC_WRITE 68 112 #define OPAL_RETURN_CPU 69 113 #define OPAL_REINIT_CPUS 70 114 #define OPAL_ELOG_READ 71 115 #define OPAL_ELOG_WRITE 72 116 #define OPAL_ELOG_ACK 73 117 #define OPAL_ELOG_RESEND 74 118 #define OPAL_ELOG_SIZE 75 119 #define OPAL_FLASH_VALIDATE 76 120 #define OPAL_FLASH_MANAGE 77 121 #define OPAL_FLASH_UPDATE 78 122 #define OPAL_RESYNC_TIMEBASE 79 123 #define OPAL_CHECK_TOKEN 80 124 #define OPAL_DUMP_INIT 81 125 #define OPAL_DUMP_INFO 82 126 #define OPAL_DUMP_READ 83 127 #define OPAL_DUMP_ACK 84 128 #define OPAL_GET_MSG 85 129 #define OPAL_CHECK_ASYNC_COMPLETION 86 130 #define OPAL_SYNC_HOST_REBOOT 87 131 #define OPAL_SENSOR_READ 88 132 #define OPAL_GET_PARAM 89 133 #define OPAL_SET_PARAM 90 134 #define OPAL_DUMP_RESEND 91 135 #define OPAL_ELOG_SEND 92 /* Deprecated */ 136 #define OPAL_PCI_SET_PHB_CAPI_MODE 93 137 #define OPAL_DUMP_INFO2 94 138 #define OPAL_WRITE_OPPANEL_ASYNC 95 139 #define OPAL_PCI_ERR_INJECT 96 140 #define OPAL_PCI_EEH_FREEZE_SET 97 141 #define OPAL_HANDLE_HMI 98 142 #define OPAL_CONFIG_CPU_IDLE_STATE 99 143 #define OPAL_SLW_SET_REG 100 144 #define OPAL_REGISTER_DUMP_REGION 101 145 #define OPAL_UNREGISTER_DUMP_REGION 102 146 #define OPAL_WRITE_TPO 103 147 #define OPAL_READ_TPO 104 148 #define OPAL_GET_DPO_STATUS 105 149 #define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */ 150 #define OPAL_IPMI_SEND 107 151 #define OPAL_IPMI_RECV 108 152 #define OPAL_I2C_REQUEST 109 153 #define OPAL_FLASH_READ 110 154 #define OPAL_FLASH_WRITE 111 155 #define OPAL_FLASH_ERASE 112 156 #define OPAL_PRD_MSG 113 157 #define OPAL_LAST 113 158 159 /* Device tree flags */ 160 161 /* Flags set in power-mgmt nodes in device tree if 162 * respective idle states are supported in the platform. 163 */ 164 #define OPAL_PM_NAP_ENABLED 0x00010000 165 #define OPAL_PM_SLEEP_ENABLED 0x00020000 166 #define OPAL_PM_WINKLE_ENABLED 0x00040000 167 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */ 168 169 /* 170 * OPAL_CONFIG_CPU_IDLE_STATE parameters 171 */ 172 #define OPAL_CONFIG_IDLE_FASTSLEEP 1 173 #define OPAL_CONFIG_IDLE_UNDO 0 174 #define OPAL_CONFIG_IDLE_APPLY 1 175 176 #ifndef __ASSEMBLY__ 177 178 /* Other enums */ 179 enum OpalFreezeState { 180 OPAL_EEH_STOPPED_NOT_FROZEN = 0, 181 OPAL_EEH_STOPPED_MMIO_FREEZE = 1, 182 OPAL_EEH_STOPPED_DMA_FREEZE = 2, 183 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3, 184 OPAL_EEH_STOPPED_RESET = 4, 185 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5, 186 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6 187 }; 188 189 enum OpalEehFreezeActionToken { 190 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1, 191 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2, 192 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3, 193 194 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1, 195 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2, 196 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3 197 }; 198 199 enum OpalPciStatusToken { 200 OPAL_EEH_NO_ERROR = 0, 201 OPAL_EEH_IOC_ERROR = 1, 202 OPAL_EEH_PHB_ERROR = 2, 203 OPAL_EEH_PE_ERROR = 3, 204 OPAL_EEH_PE_MMIO_ERROR = 4, 205 OPAL_EEH_PE_DMA_ERROR = 5 206 }; 207 208 enum OpalPciErrorSeverity { 209 OPAL_EEH_SEV_NO_ERROR = 0, 210 OPAL_EEH_SEV_IOC_DEAD = 1, 211 OPAL_EEH_SEV_PHB_DEAD = 2, 212 OPAL_EEH_SEV_PHB_FENCED = 3, 213 OPAL_EEH_SEV_PE_ER = 4, 214 OPAL_EEH_SEV_INF = 5 215 }; 216 217 enum OpalErrinjectType { 218 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0, 219 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1, 220 }; 221 222 enum OpalErrinjectFunc { 223 /* IOA bus specific errors */ 224 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0, 225 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1, 226 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2, 227 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3, 228 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4, 229 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5, 230 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6, 231 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7, 232 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8, 233 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9, 234 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10, 235 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11, 236 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12, 237 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13, 238 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14, 239 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15, 240 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16, 241 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17, 242 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18, 243 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19, 244 }; 245 246 enum OpalMmioWindowType { 247 OPAL_M32_WINDOW_TYPE = 1, 248 OPAL_M64_WINDOW_TYPE = 2, 249 OPAL_IO_WINDOW_TYPE = 3 250 }; 251 252 enum OpalExceptionHandler { 253 OPAL_MACHINE_CHECK_HANDLER = 1, 254 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2, 255 OPAL_SOFTPATCH_HANDLER = 3 256 }; 257 258 enum OpalPendingState { 259 OPAL_EVENT_OPAL_INTERNAL = 0x1, 260 OPAL_EVENT_NVRAM = 0x2, 261 OPAL_EVENT_RTC = 0x4, 262 OPAL_EVENT_CONSOLE_OUTPUT = 0x8, 263 OPAL_EVENT_CONSOLE_INPUT = 0x10, 264 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20, 265 OPAL_EVENT_ERROR_LOG = 0x40, 266 OPAL_EVENT_EPOW = 0x80, 267 OPAL_EVENT_LED_STATUS = 0x100, 268 OPAL_EVENT_PCI_ERROR = 0x200, 269 OPAL_EVENT_DUMP_AVAIL = 0x400, 270 OPAL_EVENT_MSG_PENDING = 0x800, 271 }; 272 273 enum OpalThreadStatus { 274 OPAL_THREAD_INACTIVE = 0x0, 275 OPAL_THREAD_STARTED = 0x1, 276 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */ 277 }; 278 279 enum OpalPciBusCompare { 280 OpalPciBusAny = 0, /* Any bus number match */ 281 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */ 282 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */ 283 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */ 284 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */ 285 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */ 286 OpalPciBusAll = 7, /* Match bus number exactly */ 287 }; 288 289 enum OpalDeviceCompare { 290 OPAL_IGNORE_RID_DEVICE_NUMBER = 0, 291 OPAL_COMPARE_RID_DEVICE_NUMBER = 1 292 }; 293 294 enum OpalFuncCompare { 295 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0, 296 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1 297 }; 298 299 enum OpalPeAction { 300 OPAL_UNMAP_PE = 0, 301 OPAL_MAP_PE = 1 302 }; 303 304 enum OpalPeltvAction { 305 OPAL_REMOVE_PE_FROM_DOMAIN = 0, 306 OPAL_ADD_PE_TO_DOMAIN = 1 307 }; 308 309 enum OpalMveEnableAction { 310 OPAL_DISABLE_MVE = 0, 311 OPAL_ENABLE_MVE = 1 312 }; 313 314 enum OpalM64Action { 315 OPAL_DISABLE_M64 = 0, 316 OPAL_ENABLE_M64_SPLIT = 1, 317 OPAL_ENABLE_M64_NON_SPLIT = 2 318 }; 319 320 enum OpalPciResetScope { 321 OPAL_RESET_PHB_COMPLETE = 1, 322 OPAL_RESET_PCI_LINK = 2, 323 OPAL_RESET_PHB_ERROR = 3, 324 OPAL_RESET_PCI_HOT = 4, 325 OPAL_RESET_PCI_FUNDAMENTAL = 5, 326 OPAL_RESET_PCI_IODA_TABLE = 6 327 }; 328 329 enum OpalPciReinitScope { 330 /* 331 * Note: we chose values that do not overlap 332 * OpalPciResetScope as OPAL v2 used the same 333 * enum for both 334 */ 335 OPAL_REINIT_PCI_DEV = 1000 336 }; 337 338 enum OpalPciResetState { 339 OPAL_DEASSERT_RESET = 0, 340 OPAL_ASSERT_RESET = 1 341 }; 342 343 /* 344 * Address cycle types for LPC accesses. These also correspond 345 * to the content of the first cell of the "reg" property for 346 * device nodes on the LPC bus 347 */ 348 enum OpalLPCAddressType { 349 OPAL_LPC_MEM = 0, 350 OPAL_LPC_IO = 1, 351 OPAL_LPC_FW = 2, 352 }; 353 354 enum opal_msg_type { 355 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc, 356 * additional params function-specific 357 */ 358 OPAL_MSG_MEM_ERR, 359 OPAL_MSG_EPOW, 360 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */ 361 OPAL_MSG_HMI_EVT, 362 OPAL_MSG_DPO, 363 OPAL_MSG_PRD, 364 OPAL_MSG_TYPE_MAX, 365 }; 366 367 struct opal_msg { 368 __be32 msg_type; 369 __be32 reserved; 370 __be64 params[8]; 371 }; 372 373 /* System parameter permission */ 374 enum OpalSysparamPerm { 375 OPAL_SYSPARAM_READ = 0x1, 376 OPAL_SYSPARAM_WRITE = 0x2, 377 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE), 378 }; 379 380 enum { 381 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1, 382 }; 383 384 struct opal_ipmi_msg { 385 uint8_t version; 386 uint8_t netfn; 387 uint8_t cmd; 388 uint8_t data[]; 389 }; 390 391 /* FSP memory errors handling */ 392 enum OpalMemErr_Version { 393 OpalMemErr_V1 = 1, 394 }; 395 396 enum OpalMemErrType { 397 OPAL_MEM_ERR_TYPE_RESILIENCE = 0, 398 OPAL_MEM_ERR_TYPE_DYN_DALLOC, 399 }; 400 401 /* Memory Reilience error type */ 402 enum OpalMemErr_ResilErrType { 403 OPAL_MEM_RESILIENCE_CE = 0, 404 OPAL_MEM_RESILIENCE_UE, 405 OPAL_MEM_RESILIENCE_UE_SCRUB, 406 }; 407 408 /* Dynamic Memory Deallocation type */ 409 enum OpalMemErr_DynErrType { 410 OPAL_MEM_DYNAMIC_DEALLOC = 0, 411 }; 412 413 struct OpalMemoryErrorData { 414 enum OpalMemErr_Version version:8; /* 0x00 */ 415 enum OpalMemErrType type:8; /* 0x01 */ 416 __be16 flags; /* 0x02 */ 417 uint8_t reserved_1[4]; /* 0x04 */ 418 419 union { 420 /* Memory Resilience corrected/uncorrected error info */ 421 struct { 422 enum OpalMemErr_ResilErrType resil_err_type:8; 423 uint8_t reserved_1[7]; 424 __be64 physical_address_start; 425 __be64 physical_address_end; 426 } resilience; 427 /* Dynamic memory deallocation error info */ 428 struct { 429 enum OpalMemErr_DynErrType dyn_err_type:8; 430 uint8_t reserved_1[7]; 431 __be64 physical_address_start; 432 __be64 physical_address_end; 433 } dyn_dealloc; 434 } u; 435 }; 436 437 /* HMI interrupt event */ 438 enum OpalHMI_Version { 439 OpalHMIEvt_V1 = 1, 440 }; 441 442 enum OpalHMI_Severity { 443 OpalHMI_SEV_NO_ERROR = 0, 444 OpalHMI_SEV_WARNING = 1, 445 OpalHMI_SEV_ERROR_SYNC = 2, 446 OpalHMI_SEV_FATAL = 3, 447 }; 448 449 enum OpalHMI_Disposition { 450 OpalHMI_DISPOSITION_RECOVERED = 0, 451 OpalHMI_DISPOSITION_NOT_RECOVERED = 1, 452 }; 453 454 enum OpalHMI_ErrType { 455 OpalHMI_ERROR_MALFUNC_ALERT = 0, 456 OpalHMI_ERROR_PROC_RECOV_DONE, 457 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN, 458 OpalHMI_ERROR_PROC_RECOV_MASKED, 459 OpalHMI_ERROR_TFAC, 460 OpalHMI_ERROR_TFMR_PARITY, 461 OpalHMI_ERROR_HA_OVERFLOW_WARN, 462 OpalHMI_ERROR_XSCOM_FAIL, 463 OpalHMI_ERROR_XSCOM_DONE, 464 OpalHMI_ERROR_SCOM_FIR, 465 OpalHMI_ERROR_DEBUG_TRIG_FIR, 466 OpalHMI_ERROR_HYP_RESOURCE, 467 OpalHMI_ERROR_CAPP_RECOVERY, 468 }; 469 470 struct OpalHMIEvent { 471 uint8_t version; /* 0x00 */ 472 uint8_t severity; /* 0x01 */ 473 uint8_t type; /* 0x02 */ 474 uint8_t disposition; /* 0x03 */ 475 uint8_t reserved_1[4]; /* 0x04 */ 476 477 __be64 hmer; 478 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */ 479 __be64 tfmr; 480 }; 481 482 enum { 483 OPAL_P7IOC_DIAG_TYPE_NONE = 0, 484 OPAL_P7IOC_DIAG_TYPE_RGC = 1, 485 OPAL_P7IOC_DIAG_TYPE_BI = 2, 486 OPAL_P7IOC_DIAG_TYPE_CI = 3, 487 OPAL_P7IOC_DIAG_TYPE_MISC = 4, 488 OPAL_P7IOC_DIAG_TYPE_I2C = 5, 489 OPAL_P7IOC_DIAG_TYPE_LAST = 6 490 }; 491 492 struct OpalIoP7IOCErrorData { 493 __be16 type; 494 495 /* GEM */ 496 __be64 gemXfir; 497 __be64 gemRfir; 498 __be64 gemRirqfir; 499 __be64 gemMask; 500 __be64 gemRwof; 501 502 /* LEM */ 503 __be64 lemFir; 504 __be64 lemErrMask; 505 __be64 lemAction0; 506 __be64 lemAction1; 507 __be64 lemWof; 508 509 union { 510 struct OpalIoP7IOCRgcErrorData { 511 __be64 rgcStatus; /* 3E1C10 */ 512 __be64 rgcLdcp; /* 3E1C18 */ 513 }rgc; 514 struct OpalIoP7IOCBiErrorData { 515 __be64 biLdcp0; /* 3C0100, 3C0118 */ 516 __be64 biLdcp1; /* 3C0108, 3C0120 */ 517 __be64 biLdcp2; /* 3C0110, 3C0128 */ 518 __be64 biFenceStatus; /* 3C0130, 3C0130 */ 519 520 uint8_t biDownbound; /* BI Downbound or Upbound */ 521 }bi; 522 struct OpalIoP7IOCCiErrorData { 523 __be64 ciPortStatus; /* 3Dn008 */ 524 __be64 ciPortLdcp; /* 3Dn010 */ 525 526 uint8_t ciPort; /* Index of CI port: 0/1 */ 527 }ci; 528 }; 529 }; 530 531 /** 532 * This structure defines the overlay which will be used to store PHB error 533 * data upon request. 534 */ 535 enum { 536 OPAL_PHB_ERROR_DATA_VERSION_1 = 1, 537 }; 538 539 enum { 540 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1, 541 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2 542 }; 543 544 enum { 545 OPAL_P7IOC_NUM_PEST_REGS = 128, 546 OPAL_PHB3_NUM_PEST_REGS = 256 547 }; 548 549 struct OpalIoPhbErrorCommon { 550 __be32 version; 551 __be32 ioType; 552 __be32 len; 553 }; 554 555 struct OpalIoP7IOCPhbErrorData { 556 struct OpalIoPhbErrorCommon common; 557 558 __be32 brdgCtl; 559 560 // P7IOC utl regs 561 __be32 portStatusReg; 562 __be32 rootCmplxStatus; 563 __be32 busAgentStatus; 564 565 // P7IOC cfg regs 566 __be32 deviceStatus; 567 __be32 slotStatus; 568 __be32 linkStatus; 569 __be32 devCmdStatus; 570 __be32 devSecStatus; 571 572 // cfg AER regs 573 __be32 rootErrorStatus; 574 __be32 uncorrErrorStatus; 575 __be32 corrErrorStatus; 576 __be32 tlpHdr1; 577 __be32 tlpHdr2; 578 __be32 tlpHdr3; 579 __be32 tlpHdr4; 580 __be32 sourceId; 581 582 __be32 rsv3; 583 584 // Record data about the call to allocate a buffer. 585 __be64 errorClass; 586 __be64 correlator; 587 588 //P7IOC MMIO Error Regs 589 __be64 p7iocPlssr; // n120 590 __be64 p7iocCsr; // n110 591 __be64 lemFir; // nC00 592 __be64 lemErrorMask; // nC18 593 __be64 lemWOF; // nC40 594 __be64 phbErrorStatus; // nC80 595 __be64 phbFirstErrorStatus; // nC88 596 __be64 phbErrorLog0; // nCC0 597 __be64 phbErrorLog1; // nCC8 598 __be64 mmioErrorStatus; // nD00 599 __be64 mmioFirstErrorStatus; // nD08 600 __be64 mmioErrorLog0; // nD40 601 __be64 mmioErrorLog1; // nD48 602 __be64 dma0ErrorStatus; // nD80 603 __be64 dma0FirstErrorStatus; // nD88 604 __be64 dma0ErrorLog0; // nDC0 605 __be64 dma0ErrorLog1; // nDC8 606 __be64 dma1ErrorStatus; // nE00 607 __be64 dma1FirstErrorStatus; // nE08 608 __be64 dma1ErrorLog0; // nE40 609 __be64 dma1ErrorLog1; // nE48 610 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS]; 611 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS]; 612 }; 613 614 struct OpalIoPhb3ErrorData { 615 struct OpalIoPhbErrorCommon common; 616 617 __be32 brdgCtl; 618 619 /* PHB3 UTL regs */ 620 __be32 portStatusReg; 621 __be32 rootCmplxStatus; 622 __be32 busAgentStatus; 623 624 /* PHB3 cfg regs */ 625 __be32 deviceStatus; 626 __be32 slotStatus; 627 __be32 linkStatus; 628 __be32 devCmdStatus; 629 __be32 devSecStatus; 630 631 /* cfg AER regs */ 632 __be32 rootErrorStatus; 633 __be32 uncorrErrorStatus; 634 __be32 corrErrorStatus; 635 __be32 tlpHdr1; 636 __be32 tlpHdr2; 637 __be32 tlpHdr3; 638 __be32 tlpHdr4; 639 __be32 sourceId; 640 641 __be32 rsv3; 642 643 /* Record data about the call to allocate a buffer */ 644 __be64 errorClass; 645 __be64 correlator; 646 647 /* PHB3 MMIO Error Regs */ 648 __be64 nFir; /* 000 */ 649 __be64 nFirMask; /* 003 */ 650 __be64 nFirWOF; /* 008 */ 651 __be64 phbPlssr; /* 120 */ 652 __be64 phbCsr; /* 110 */ 653 __be64 lemFir; /* C00 */ 654 __be64 lemErrorMask; /* C18 */ 655 __be64 lemWOF; /* C40 */ 656 __be64 phbErrorStatus; /* C80 */ 657 __be64 phbFirstErrorStatus; /* C88 */ 658 __be64 phbErrorLog0; /* CC0 */ 659 __be64 phbErrorLog1; /* CC8 */ 660 __be64 mmioErrorStatus; /* D00 */ 661 __be64 mmioFirstErrorStatus; /* D08 */ 662 __be64 mmioErrorLog0; /* D40 */ 663 __be64 mmioErrorLog1; /* D48 */ 664 __be64 dma0ErrorStatus; /* D80 */ 665 __be64 dma0FirstErrorStatus; /* D88 */ 666 __be64 dma0ErrorLog0; /* DC0 */ 667 __be64 dma0ErrorLog1; /* DC8 */ 668 __be64 dma1ErrorStatus; /* E00 */ 669 __be64 dma1FirstErrorStatus; /* E08 */ 670 __be64 dma1ErrorLog0; /* E40 */ 671 __be64 dma1ErrorLog1; /* E48 */ 672 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS]; 673 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS]; 674 }; 675 676 enum { 677 OPAL_REINIT_CPUS_HILE_BE = (1 << 0), 678 OPAL_REINIT_CPUS_HILE_LE = (1 << 1), 679 }; 680 681 typedef struct oppanel_line { 682 __be64 line; 683 __be64 line_len; 684 } oppanel_line_t; 685 686 enum opal_prd_msg_type { 687 OPAL_PRD_MSG_TYPE_INIT = 0, /* HBRT --> OPAL */ 688 OPAL_PRD_MSG_TYPE_FINI, /* HBRT/kernel --> OPAL */ 689 OPAL_PRD_MSG_TYPE_ATTN, /* HBRT <-- OPAL */ 690 OPAL_PRD_MSG_TYPE_ATTN_ACK, /* HBRT --> OPAL */ 691 OPAL_PRD_MSG_TYPE_OCC_ERROR, /* HBRT <-- OPAL */ 692 OPAL_PRD_MSG_TYPE_OCC_RESET, /* HBRT <-- OPAL */ 693 }; 694 695 struct opal_prd_msg_header { 696 uint8_t type; 697 uint8_t pad[1]; 698 __be16 size; 699 }; 700 701 struct opal_prd_msg; 702 703 /* 704 * SG entries 705 * 706 * WARNING: The current implementation requires each entry 707 * to represent a block that is 4k aligned *and* each block 708 * size except the last one in the list to be as well. 709 */ 710 struct opal_sg_entry { 711 __be64 data; 712 __be64 length; 713 }; 714 715 /* 716 * Candiate image SG list. 717 * 718 * length = VER | length 719 */ 720 struct opal_sg_list { 721 __be64 length; 722 __be64 next; 723 struct opal_sg_entry entry[]; 724 }; 725 726 /* 727 * Dump region ID range usable by the OS 728 */ 729 #define OPAL_DUMP_REGION_HOST_START 0x80 730 #define OPAL_DUMP_REGION_LOG_BUF 0x80 731 #define OPAL_DUMP_REGION_HOST_END 0xFF 732 733 /* CAPI modes for PHB */ 734 enum { 735 OPAL_PHB_CAPI_MODE_PCIE = 0, 736 OPAL_PHB_CAPI_MODE_CAPI = 1, 737 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2, 738 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3, 739 }; 740 741 /* OPAL I2C request */ 742 struct opal_i2c_request { 743 uint8_t type; 744 #define OPAL_I2C_RAW_READ 0 745 #define OPAL_I2C_RAW_WRITE 1 746 #define OPAL_I2C_SM_READ 2 747 #define OPAL_I2C_SM_WRITE 3 748 uint8_t flags; 749 #define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */ 750 uint8_t subaddr_sz; /* Max 4 */ 751 uint8_t reserved; 752 __be16 addr; /* 7 or 10 bit address */ 753 __be16 reserved2; 754 __be32 subaddr; /* Sub-address if any */ 755 __be32 size; /* Data size */ 756 __be64 buffer_ra; /* Buffer real address */ 757 }; 758 759 #endif /* __ASSEMBLY__ */ 760 761 #endif /* __OPAL_API_H */ 762