1 /*
2  * OPAL API definitions.
3  *
4  * Copyright 2011-2015 IBM Corp.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 
12 #ifndef __OPAL_API_H
13 #define __OPAL_API_H
14 
15 /****** OPAL APIs ******/
16 
17 /* Return codes */
18 #define OPAL_SUCCESS		0
19 #define OPAL_PARAMETER		-1
20 #define OPAL_BUSY		-2
21 #define OPAL_PARTIAL		-3
22 #define OPAL_CONSTRAINED	-4
23 #define OPAL_CLOSED		-5
24 #define OPAL_HARDWARE		-6
25 #define OPAL_UNSUPPORTED	-7
26 #define OPAL_PERMISSION		-8
27 #define OPAL_NO_MEM		-9
28 #define OPAL_RESOURCE		-10
29 #define OPAL_INTERNAL_ERROR	-11
30 #define OPAL_BUSY_EVENT		-12
31 #define OPAL_HARDWARE_FROZEN	-13
32 #define OPAL_WRONG_STATE	-14
33 #define OPAL_ASYNC_COMPLETION	-15
34 #define OPAL_EMPTY		-16
35 #define OPAL_I2C_TIMEOUT	-17
36 #define OPAL_I2C_INVALID_CMD	-18
37 #define OPAL_I2C_LBUS_PARITY	-19
38 #define OPAL_I2C_BKEND_OVERRUN	-20
39 #define OPAL_I2C_BKEND_ACCESS	-21
40 #define OPAL_I2C_ARBT_LOST	-22
41 #define OPAL_I2C_NACK_RCVD	-23
42 #define OPAL_I2C_STOP_ERR	-24
43 #define OPAL_XIVE_PROVISIONING	-31
44 #define OPAL_XIVE_FREE_ACTIVE	-32
45 
46 /* API Tokens (in r0) */
47 #define OPAL_INVALID_CALL		       -1
48 #define OPAL_TEST				0
49 #define OPAL_CONSOLE_WRITE			1
50 #define OPAL_CONSOLE_READ			2
51 #define OPAL_RTC_READ				3
52 #define OPAL_RTC_WRITE				4
53 #define OPAL_CEC_POWER_DOWN			5
54 #define OPAL_CEC_REBOOT				6
55 #define OPAL_READ_NVRAM				7
56 #define OPAL_WRITE_NVRAM			8
57 #define OPAL_HANDLE_INTERRUPT			9
58 #define OPAL_POLL_EVENTS			10
59 #define OPAL_PCI_SET_HUB_TCE_MEMORY		11
60 #define OPAL_PCI_SET_PHB_TCE_MEMORY		12
61 #define OPAL_PCI_CONFIG_READ_BYTE		13
62 #define OPAL_PCI_CONFIG_READ_HALF_WORD  	14
63 #define OPAL_PCI_CONFIG_READ_WORD		15
64 #define OPAL_PCI_CONFIG_WRITE_BYTE		16
65 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD		17
66 #define OPAL_PCI_CONFIG_WRITE_WORD		18
67 #define OPAL_SET_XIVE				19
68 #define OPAL_GET_XIVE				20
69 #define OPAL_GET_COMPLETION_TOKEN_STATUS	21 /* obsolete */
70 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER	22
71 #define OPAL_PCI_EEH_FREEZE_STATUS		23
72 #define OPAL_PCI_SHPC				24
73 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE		25
74 #define OPAL_PCI_EEH_FREEZE_CLEAR		26
75 #define OPAL_PCI_PHB_MMIO_ENABLE		27
76 #define OPAL_PCI_SET_PHB_MEM_WINDOW		28
77 #define OPAL_PCI_MAP_PE_MMIO_WINDOW		29
78 #define OPAL_PCI_SET_PHB_TABLE_MEMORY		30
79 #define OPAL_PCI_SET_PE				31
80 #define OPAL_PCI_SET_PELTV			32
81 #define OPAL_PCI_SET_MVE			33
82 #define OPAL_PCI_SET_MVE_ENABLE			34
83 #define OPAL_PCI_GET_XIVE_REISSUE		35
84 #define OPAL_PCI_SET_XIVE_REISSUE		36
85 #define OPAL_PCI_SET_XIVE_PE			37
86 #define OPAL_GET_XIVE_SOURCE			38
87 #define OPAL_GET_MSI_32				39
88 #define OPAL_GET_MSI_64				40
89 #define OPAL_START_CPU				41
90 #define OPAL_QUERY_CPU_STATUS			42
91 #define OPAL_WRITE_OPPANEL			43 /* unimplemented */
92 #define OPAL_PCI_MAP_PE_DMA_WINDOW		44
93 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL		45
94 #define OPAL_PCI_RESET				49
95 #define OPAL_PCI_GET_HUB_DIAG_DATA		50
96 #define OPAL_PCI_GET_PHB_DIAG_DATA		51
97 #define OPAL_PCI_FENCE_PHB			52
98 #define OPAL_PCI_REINIT				53
99 #define OPAL_PCI_MASK_PE_ERROR			54
100 #define OPAL_SET_SLOT_LED_STATUS		55
101 #define OPAL_GET_EPOW_STATUS			56
102 #define OPAL_SET_SYSTEM_ATTENTION_LED		57
103 #define OPAL_RESERVED1				58
104 #define OPAL_RESERVED2				59
105 #define OPAL_PCI_NEXT_ERROR			60
106 #define OPAL_PCI_EEH_FREEZE_STATUS2		61
107 #define OPAL_PCI_POLL				62
108 #define OPAL_PCI_MSI_EOI			63
109 #define OPAL_PCI_GET_PHB_DIAG_DATA2		64
110 #define OPAL_XSCOM_READ				65
111 #define OPAL_XSCOM_WRITE			66
112 #define OPAL_LPC_READ				67
113 #define OPAL_LPC_WRITE				68
114 #define OPAL_RETURN_CPU				69
115 #define OPAL_REINIT_CPUS			70
116 #define OPAL_ELOG_READ				71
117 #define OPAL_ELOG_WRITE				72
118 #define OPAL_ELOG_ACK				73
119 #define OPAL_ELOG_RESEND			74
120 #define OPAL_ELOG_SIZE				75
121 #define OPAL_FLASH_VALIDATE			76
122 #define OPAL_FLASH_MANAGE			77
123 #define OPAL_FLASH_UPDATE			78
124 #define OPAL_RESYNC_TIMEBASE			79
125 #define OPAL_CHECK_TOKEN			80
126 #define OPAL_DUMP_INIT				81
127 #define OPAL_DUMP_INFO				82
128 #define OPAL_DUMP_READ				83
129 #define OPAL_DUMP_ACK				84
130 #define OPAL_GET_MSG				85
131 #define OPAL_CHECK_ASYNC_COMPLETION		86
132 #define OPAL_SYNC_HOST_REBOOT			87
133 #define OPAL_SENSOR_READ			88
134 #define OPAL_GET_PARAM				89
135 #define OPAL_SET_PARAM				90
136 #define OPAL_DUMP_RESEND			91
137 #define OPAL_ELOG_SEND				92	/* Deprecated */
138 #define OPAL_PCI_SET_PHB_CAPI_MODE		93
139 #define OPAL_DUMP_INFO2				94
140 #define OPAL_WRITE_OPPANEL_ASYNC		95
141 #define OPAL_PCI_ERR_INJECT			96
142 #define OPAL_PCI_EEH_FREEZE_SET			97
143 #define OPAL_HANDLE_HMI				98
144 #define OPAL_CONFIG_CPU_IDLE_STATE		99
145 #define OPAL_SLW_SET_REG			100
146 #define OPAL_REGISTER_DUMP_REGION		101
147 #define OPAL_UNREGISTER_DUMP_REGION		102
148 #define OPAL_WRITE_TPO				103
149 #define OPAL_READ_TPO				104
150 #define OPAL_GET_DPO_STATUS			105
151 #define OPAL_OLD_I2C_REQUEST			106	/* Deprecated */
152 #define OPAL_IPMI_SEND				107
153 #define OPAL_IPMI_RECV				108
154 #define OPAL_I2C_REQUEST			109
155 #define OPAL_FLASH_READ				110
156 #define OPAL_FLASH_WRITE			111
157 #define OPAL_FLASH_ERASE			112
158 #define OPAL_PRD_MSG				113
159 #define OPAL_LEDS_GET_INDICATOR			114
160 #define OPAL_LEDS_SET_INDICATOR			115
161 #define OPAL_CEC_REBOOT2			116
162 #define OPAL_CONSOLE_FLUSH			117
163 #define OPAL_GET_DEVICE_TREE			118
164 #define OPAL_PCI_GET_PRESENCE_STATE		119
165 #define OPAL_PCI_GET_POWER_STATE		120
166 #define OPAL_PCI_SET_POWER_STATE		121
167 #define OPAL_INT_GET_XIRR			122
168 #define	OPAL_INT_SET_CPPR			123
169 #define OPAL_INT_EOI				124
170 #define OPAL_INT_SET_MFRR			125
171 #define OPAL_PCI_TCE_KILL			126
172 #define OPAL_NMMU_SET_PTCR			127
173 #define OPAL_XIVE_RESET				128
174 #define OPAL_XIVE_GET_IRQ_INFO			129
175 #define OPAL_XIVE_GET_IRQ_CONFIG		130
176 #define OPAL_XIVE_SET_IRQ_CONFIG		131
177 #define OPAL_XIVE_GET_QUEUE_INFO		132
178 #define OPAL_XIVE_SET_QUEUE_INFO		133
179 #define OPAL_XIVE_DONATE_PAGE			134
180 #define OPAL_XIVE_ALLOCATE_VP_BLOCK		135
181 #define OPAL_XIVE_FREE_VP_BLOCK			136
182 #define OPAL_XIVE_GET_VP_INFO			137
183 #define OPAL_XIVE_SET_VP_INFO			138
184 #define OPAL_XIVE_ALLOCATE_IRQ			139
185 #define OPAL_XIVE_FREE_IRQ			140
186 #define OPAL_XIVE_SYNC				141
187 #define OPAL_XIVE_DUMP				142
188 #define OPAL_XIVE_RESERVED3			143
189 #define OPAL_XIVE_RESERVED4			144
190 #define OPAL_NPU_INIT_CONTEXT			146
191 #define OPAL_NPU_DESTROY_CONTEXT		147
192 #define OPAL_NPU_MAP_LPAR			148
193 #define OPAL_LAST				148
194 
195 /* Device tree flags */
196 
197 /*
198  * Flags set in power-mgmt nodes in device tree describing
199  * idle states that are supported in the platform.
200  */
201 
202 #define OPAL_PM_TIMEBASE_STOP		0x00000002
203 #define OPAL_PM_LOSE_HYP_CONTEXT	0x00002000
204 #define OPAL_PM_LOSE_FULL_CONTEXT	0x00004000
205 #define OPAL_PM_NAP_ENABLED		0x00010000
206 #define OPAL_PM_SLEEP_ENABLED		0x00020000
207 #define OPAL_PM_WINKLE_ENABLED		0x00040000
208 #define OPAL_PM_SLEEP_ENABLED_ER1	0x00080000 /* with workaround */
209 #define OPAL_PM_STOP_INST_FAST		0x00100000
210 #define OPAL_PM_STOP_INST_DEEP		0x00200000
211 
212 /*
213  * OPAL_CONFIG_CPU_IDLE_STATE parameters
214  */
215 #define OPAL_CONFIG_IDLE_FASTSLEEP	1
216 #define OPAL_CONFIG_IDLE_UNDO		0
217 #define OPAL_CONFIG_IDLE_APPLY		1
218 
219 #ifndef __ASSEMBLY__
220 
221 /* Other enums */
222 enum OpalFreezeState {
223 	OPAL_EEH_STOPPED_NOT_FROZEN = 0,
224 	OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
225 	OPAL_EEH_STOPPED_DMA_FREEZE = 2,
226 	OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
227 	OPAL_EEH_STOPPED_RESET = 4,
228 	OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
229 	OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
230 };
231 
232 enum OpalEehFreezeActionToken {
233 	OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
234 	OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
235 	OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
236 
237 	OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
238 	OPAL_EEH_ACTION_SET_FREEZE_DMA  = 2,
239 	OPAL_EEH_ACTION_SET_FREEZE_ALL  = 3
240 };
241 
242 enum OpalPciStatusToken {
243 	OPAL_EEH_NO_ERROR	= 0,
244 	OPAL_EEH_IOC_ERROR	= 1,
245 	OPAL_EEH_PHB_ERROR	= 2,
246 	OPAL_EEH_PE_ERROR	= 3,
247 	OPAL_EEH_PE_MMIO_ERROR	= 4,
248 	OPAL_EEH_PE_DMA_ERROR	= 5
249 };
250 
251 enum OpalPciErrorSeverity {
252 	OPAL_EEH_SEV_NO_ERROR	= 0,
253 	OPAL_EEH_SEV_IOC_DEAD	= 1,
254 	OPAL_EEH_SEV_PHB_DEAD	= 2,
255 	OPAL_EEH_SEV_PHB_FENCED	= 3,
256 	OPAL_EEH_SEV_PE_ER	= 4,
257 	OPAL_EEH_SEV_INF	= 5
258 };
259 
260 enum OpalErrinjectType {
261 	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR	= 0,
262 	OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64	= 1,
263 };
264 
265 enum OpalErrinjectFunc {
266 	/* IOA bus specific errors */
267 	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR	= 0,
268 	OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA	= 1,
269 	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR	= 2,
270 	OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA	= 3,
271 	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR	= 4,
272 	OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA	= 5,
273 	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR	= 6,
274 	OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA	= 7,
275 	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR	= 8,
276 	OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA	= 9,
277 	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR	= 10,
278 	OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA	= 11,
279 	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR	= 12,
280 	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA	= 13,
281 	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER	= 14,
282 	OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET	= 15,
283 	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR	= 16,
284 	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA	= 17,
285 	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER	= 18,
286 	OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET	= 19,
287 };
288 
289 enum OpalMmioWindowType {
290 	OPAL_M32_WINDOW_TYPE = 1,
291 	OPAL_M64_WINDOW_TYPE = 2,
292 	OPAL_IO_WINDOW_TYPE  = 3
293 };
294 
295 enum OpalExceptionHandler {
296 	OPAL_MACHINE_CHECK_HANDLER	    = 1,
297 	OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
298 	OPAL_SOFTPATCH_HANDLER		    = 3
299 };
300 
301 enum OpalPendingState {
302 	OPAL_EVENT_OPAL_INTERNAL   = 0x1,
303 	OPAL_EVENT_NVRAM	   = 0x2,
304 	OPAL_EVENT_RTC		   = 0x4,
305 	OPAL_EVENT_CONSOLE_OUTPUT  = 0x8,
306 	OPAL_EVENT_CONSOLE_INPUT   = 0x10,
307 	OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
308 	OPAL_EVENT_ERROR_LOG	   = 0x40,
309 	OPAL_EVENT_EPOW		   = 0x80,
310 	OPAL_EVENT_LED_STATUS	   = 0x100,
311 	OPAL_EVENT_PCI_ERROR	   = 0x200,
312 	OPAL_EVENT_DUMP_AVAIL	   = 0x400,
313 	OPAL_EVENT_MSG_PENDING	   = 0x800,
314 };
315 
316 enum OpalThreadStatus {
317 	OPAL_THREAD_INACTIVE = 0x0,
318 	OPAL_THREAD_STARTED = 0x1,
319 	OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
320 };
321 
322 enum OpalPciBusCompare {
323 	OpalPciBusAny	= 0,	/* Any bus number match */
324 	OpalPciBus3Bits	= 2,	/* Match top 3 bits of bus number */
325 	OpalPciBus4Bits	= 3,	/* Match top 4 bits of bus number */
326 	OpalPciBus5Bits	= 4,	/* Match top 5 bits of bus number */
327 	OpalPciBus6Bits	= 5,	/* Match top 6 bits of bus number */
328 	OpalPciBus7Bits	= 6,	/* Match top 7 bits of bus number */
329 	OpalPciBusAll	= 7,	/* Match bus number exactly */
330 };
331 
332 enum OpalDeviceCompare {
333 	OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
334 	OPAL_COMPARE_RID_DEVICE_NUMBER = 1
335 };
336 
337 enum OpalFuncCompare {
338 	OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
339 	OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
340 };
341 
342 enum OpalPeAction {
343 	OPAL_UNMAP_PE = 0,
344 	OPAL_MAP_PE = 1
345 };
346 
347 enum OpalPeltvAction {
348 	OPAL_REMOVE_PE_FROM_DOMAIN = 0,
349 	OPAL_ADD_PE_TO_DOMAIN = 1
350 };
351 
352 enum OpalMveEnableAction {
353 	OPAL_DISABLE_MVE = 0,
354 	OPAL_ENABLE_MVE = 1
355 };
356 
357 enum OpalM64Action {
358 	OPAL_DISABLE_M64 = 0,
359 	OPAL_ENABLE_M64_SPLIT = 1,
360 	OPAL_ENABLE_M64_NON_SPLIT = 2
361 };
362 
363 enum OpalPciResetScope {
364 	OPAL_RESET_PHB_COMPLETE		= 1,
365 	OPAL_RESET_PCI_LINK		= 2,
366 	OPAL_RESET_PHB_ERROR		= 3,
367 	OPAL_RESET_PCI_HOT		= 4,
368 	OPAL_RESET_PCI_FUNDAMENTAL	= 5,
369 	OPAL_RESET_PCI_IODA_TABLE	= 6
370 };
371 
372 enum OpalPciReinitScope {
373 	/*
374 	 * Note: we chose values that do not overlap
375 	 * OpalPciResetScope as OPAL v2 used the same
376 	 * enum for both
377 	 */
378 	OPAL_REINIT_PCI_DEV = 1000
379 };
380 
381 enum OpalPciResetState {
382 	OPAL_DEASSERT_RESET = 0,
383 	OPAL_ASSERT_RESET   = 1
384 };
385 
386 enum OpalPciSlotPresence {
387 	OPAL_PCI_SLOT_EMPTY	= 0,
388 	OPAL_PCI_SLOT_PRESENT	= 1
389 };
390 
391 enum OpalPciSlotPower {
392 	OPAL_PCI_SLOT_POWER_OFF	= 0,
393 	OPAL_PCI_SLOT_POWER_ON	= 1,
394 	OPAL_PCI_SLOT_OFFLINE	= 2,
395 	OPAL_PCI_SLOT_ONLINE	= 3
396 };
397 
398 enum OpalSlotLedType {
399 	OPAL_SLOT_LED_TYPE_ID = 0,	/* IDENTIFY LED */
400 	OPAL_SLOT_LED_TYPE_FAULT = 1,	/* FAULT LED */
401 	OPAL_SLOT_LED_TYPE_ATTN = 2,	/* System Attention LED */
402 	OPAL_SLOT_LED_TYPE_MAX = 3
403 };
404 
405 enum OpalSlotLedState {
406 	OPAL_SLOT_LED_STATE_OFF = 0,	/* LED is OFF */
407 	OPAL_SLOT_LED_STATE_ON = 1	/* LED is ON */
408 };
409 
410 /*
411  * Address cycle types for LPC accesses. These also correspond
412  * to the content of the first cell of the "reg" property for
413  * device nodes on the LPC bus
414  */
415 enum OpalLPCAddressType {
416 	OPAL_LPC_MEM	= 0,
417 	OPAL_LPC_IO	= 1,
418 	OPAL_LPC_FW	= 2,
419 };
420 
421 enum opal_msg_type {
422 	OPAL_MSG_ASYNC_COMP	= 0,	/* params[0] = token, params[1] = rc,
423 					 * additional params function-specific
424 					 */
425 	OPAL_MSG_MEM_ERR	= 1,
426 	OPAL_MSG_EPOW		= 2,
427 	OPAL_MSG_SHUTDOWN	= 3,	/* params[0] = 1 reboot, 0 shutdown */
428 	OPAL_MSG_HMI_EVT	= 4,
429 	OPAL_MSG_DPO		= 5,
430 	OPAL_MSG_PRD		= 6,
431 	OPAL_MSG_OCC		= 7,
432 	OPAL_MSG_TYPE_MAX,
433 };
434 
435 struct opal_msg {
436 	__be32 msg_type;
437 	__be32 reserved;
438 	__be64 params[8];
439 };
440 
441 /* System parameter permission */
442 enum OpalSysparamPerm {
443 	OPAL_SYSPARAM_READ  = 0x1,
444 	OPAL_SYSPARAM_WRITE = 0x2,
445 	OPAL_SYSPARAM_RW    = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
446 };
447 
448 enum {
449 	OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
450 };
451 
452 struct opal_ipmi_msg {
453 	uint8_t version;
454 	uint8_t netfn;
455 	uint8_t cmd;
456 	uint8_t data[];
457 };
458 
459 /* FSP memory errors handling */
460 enum OpalMemErr_Version {
461 	OpalMemErr_V1 = 1,
462 };
463 
464 enum OpalMemErrType {
465 	OPAL_MEM_ERR_TYPE_RESILIENCE	= 0,
466 	OPAL_MEM_ERR_TYPE_DYN_DALLOC,
467 };
468 
469 /* Memory Reilience error type */
470 enum OpalMemErr_ResilErrType {
471 	OPAL_MEM_RESILIENCE_CE		= 0,
472 	OPAL_MEM_RESILIENCE_UE,
473 	OPAL_MEM_RESILIENCE_UE_SCRUB,
474 };
475 
476 /* Dynamic Memory Deallocation type */
477 enum OpalMemErr_DynErrType {
478 	OPAL_MEM_DYNAMIC_DEALLOC	= 0,
479 };
480 
481 struct OpalMemoryErrorData {
482 	enum OpalMemErr_Version	version:8;	/* 0x00 */
483 	enum OpalMemErrType	type:8;		/* 0x01 */
484 	__be16			flags;		/* 0x02 */
485 	uint8_t			reserved_1[4];	/* 0x04 */
486 
487 	union {
488 		/* Memory Resilience corrected/uncorrected error info */
489 		struct {
490 			enum OpalMemErr_ResilErrType	resil_err_type:8;
491 			uint8_t				reserved_1[7];
492 			__be64				physical_address_start;
493 			__be64				physical_address_end;
494 		} resilience;
495 		/* Dynamic memory deallocation error info */
496 		struct {
497 			enum OpalMemErr_DynErrType	dyn_err_type:8;
498 			uint8_t				reserved_1[7];
499 			__be64				physical_address_start;
500 			__be64				physical_address_end;
501 		} dyn_dealloc;
502 	} u;
503 };
504 
505 /* HMI interrupt event */
506 enum OpalHMI_Version {
507 	OpalHMIEvt_V1 = 1,
508 	OpalHMIEvt_V2 = 2,
509 };
510 
511 enum OpalHMI_Severity {
512 	OpalHMI_SEV_NO_ERROR = 0,
513 	OpalHMI_SEV_WARNING = 1,
514 	OpalHMI_SEV_ERROR_SYNC = 2,
515 	OpalHMI_SEV_FATAL = 3,
516 };
517 
518 enum OpalHMI_Disposition {
519 	OpalHMI_DISPOSITION_RECOVERED = 0,
520 	OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
521 };
522 
523 enum OpalHMI_ErrType {
524 	OpalHMI_ERROR_MALFUNC_ALERT	= 0,
525 	OpalHMI_ERROR_PROC_RECOV_DONE,
526 	OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
527 	OpalHMI_ERROR_PROC_RECOV_MASKED,
528 	OpalHMI_ERROR_TFAC,
529 	OpalHMI_ERROR_TFMR_PARITY,
530 	OpalHMI_ERROR_HA_OVERFLOW_WARN,
531 	OpalHMI_ERROR_XSCOM_FAIL,
532 	OpalHMI_ERROR_XSCOM_DONE,
533 	OpalHMI_ERROR_SCOM_FIR,
534 	OpalHMI_ERROR_DEBUG_TRIG_FIR,
535 	OpalHMI_ERROR_HYP_RESOURCE,
536 	OpalHMI_ERROR_CAPP_RECOVERY,
537 };
538 
539 enum OpalHMI_XstopType {
540 	CHECKSTOP_TYPE_UNKNOWN	=	0,
541 	CHECKSTOP_TYPE_CORE	=	1,
542 	CHECKSTOP_TYPE_NX	=	2,
543 };
544 
545 enum OpalHMI_CoreXstopReason {
546 	CORE_CHECKSTOP_IFU_REGFILE		= 0x00000001,
547 	CORE_CHECKSTOP_IFU_LOGIC		= 0x00000002,
548 	CORE_CHECKSTOP_PC_DURING_RECOV		= 0x00000004,
549 	CORE_CHECKSTOP_ISU_REGFILE		= 0x00000008,
550 	CORE_CHECKSTOP_ISU_LOGIC		= 0x00000010,
551 	CORE_CHECKSTOP_FXU_LOGIC		= 0x00000020,
552 	CORE_CHECKSTOP_VSU_LOGIC		= 0x00000040,
553 	CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE	= 0x00000080,
554 	CORE_CHECKSTOP_LSU_REGFILE		= 0x00000100,
555 	CORE_CHECKSTOP_PC_FWD_PROGRESS		= 0x00000200,
556 	CORE_CHECKSTOP_LSU_LOGIC		= 0x00000400,
557 	CORE_CHECKSTOP_PC_LOGIC			= 0x00000800,
558 	CORE_CHECKSTOP_PC_HYP_RESOURCE		= 0x00001000,
559 	CORE_CHECKSTOP_PC_HANG_RECOV_FAILED	= 0x00002000,
560 	CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED	= 0x00004000,
561 	CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ	= 0x00008000,
562 	CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ	= 0x00010000,
563 };
564 
565 enum OpalHMI_NestAccelXstopReason {
566 	NX_CHECKSTOP_SHM_INVAL_STATE_ERR	= 0x00000001,
567 	NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1	= 0x00000002,
568 	NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2	= 0x00000004,
569 	NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR	= 0x00000008,
570 	NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR	= 0x00000010,
571 	NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR	= 0x00000020,
572 	NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR	= 0x00000040,
573 	NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR	= 0x00000080,
574 	NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR	= 0x00000100,
575 	NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR	= 0x00000200,
576 	NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR	= 0x00000400,
577 	NX_CHECKSTOP_DMA_CRB_UE			= 0x00000800,
578 	NX_CHECKSTOP_DMA_CRB_SUE		= 0x00001000,
579 	NX_CHECKSTOP_PBI_ISN_UE			= 0x00002000,
580 };
581 
582 struct OpalHMIEvent {
583 	uint8_t		version;	/* 0x00 */
584 	uint8_t		severity;	/* 0x01 */
585 	uint8_t		type;		/* 0x02 */
586 	uint8_t		disposition;	/* 0x03 */
587 	uint8_t		reserved_1[4];	/* 0x04 */
588 
589 	__be64		hmer;
590 	/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
591 	__be64		tfmr;
592 
593 	/* version 2 and later */
594 	union {
595 		/*
596 		 * checkstop info (Core/NX).
597 		 * Valid for OpalHMI_ERROR_MALFUNC_ALERT.
598 		 */
599 		struct {
600 			uint8_t	xstop_type;	/* enum OpalHMI_XstopType */
601 			uint8_t reserved_1[3];
602 			__be32  xstop_reason;
603 			union {
604 				__be32 pir;	/* for CHECKSTOP_TYPE_CORE */
605 				__be32 chip_id;	/* for CHECKSTOP_TYPE_NX */
606 			} u;
607 		} xstop_error;
608 	} u;
609 };
610 
611 enum {
612 	OPAL_P7IOC_DIAG_TYPE_NONE	= 0,
613 	OPAL_P7IOC_DIAG_TYPE_RGC	= 1,
614 	OPAL_P7IOC_DIAG_TYPE_BI		= 2,
615 	OPAL_P7IOC_DIAG_TYPE_CI		= 3,
616 	OPAL_P7IOC_DIAG_TYPE_MISC	= 4,
617 	OPAL_P7IOC_DIAG_TYPE_I2C	= 5,
618 	OPAL_P7IOC_DIAG_TYPE_LAST	= 6
619 };
620 
621 struct OpalIoP7IOCErrorData {
622 	__be16 type;
623 
624 	/* GEM */
625 	__be64 gemXfir;
626 	__be64 gemRfir;
627 	__be64 gemRirqfir;
628 	__be64 gemMask;
629 	__be64 gemRwof;
630 
631 	/* LEM */
632 	__be64 lemFir;
633 	__be64 lemErrMask;
634 	__be64 lemAction0;
635 	__be64 lemAction1;
636 	__be64 lemWof;
637 
638 	union {
639 		struct OpalIoP7IOCRgcErrorData {
640 			__be64 rgcStatus;	/* 3E1C10 */
641 			__be64 rgcLdcp;		/* 3E1C18 */
642 		}rgc;
643 		struct OpalIoP7IOCBiErrorData {
644 			__be64 biLdcp0;		/* 3C0100, 3C0118 */
645 			__be64 biLdcp1;		/* 3C0108, 3C0120 */
646 			__be64 biLdcp2;		/* 3C0110, 3C0128 */
647 			__be64 biFenceStatus;	/* 3C0130, 3C0130 */
648 
649 			uint8_t biDownbound;	/* BI Downbound or Upbound */
650 		}bi;
651 		struct OpalIoP7IOCCiErrorData {
652 			__be64 ciPortStatus;	/* 3Dn008 */
653 			__be64 ciPortLdcp;	/* 3Dn010 */
654 
655 			uint8_t ciPort;		/* Index of CI port: 0/1 */
656 		}ci;
657 	};
658 };
659 
660 /**
661  * This structure defines the overlay which will be used to store PHB error
662  * data upon request.
663  */
664 enum {
665 	OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
666 };
667 
668 enum {
669 	OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
670 	OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
671 	OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
672 };
673 
674 enum {
675 	OPAL_P7IOC_NUM_PEST_REGS = 128,
676 	OPAL_PHB3_NUM_PEST_REGS = 256,
677 	OPAL_PHB4_NUM_PEST_REGS = 512
678 };
679 
680 struct OpalIoPhbErrorCommon {
681 	__be32 version;
682 	__be32 ioType;
683 	__be32 len;
684 };
685 
686 struct OpalIoP7IOCPhbErrorData {
687 	struct OpalIoPhbErrorCommon common;
688 
689 	__be32 brdgCtl;
690 
691 	// P7IOC utl regs
692 	__be32 portStatusReg;
693 	__be32 rootCmplxStatus;
694 	__be32 busAgentStatus;
695 
696 	// P7IOC cfg regs
697 	__be32 deviceStatus;
698 	__be32 slotStatus;
699 	__be32 linkStatus;
700 	__be32 devCmdStatus;
701 	__be32 devSecStatus;
702 
703 	// cfg AER regs
704 	__be32 rootErrorStatus;
705 	__be32 uncorrErrorStatus;
706 	__be32 corrErrorStatus;
707 	__be32 tlpHdr1;
708 	__be32 tlpHdr2;
709 	__be32 tlpHdr3;
710 	__be32 tlpHdr4;
711 	__be32 sourceId;
712 
713 	__be32 rsv3;
714 
715 	// Record data about the call to allocate a buffer.
716 	__be64 errorClass;
717 	__be64 correlator;
718 
719 	//P7IOC MMIO Error Regs
720 	__be64 p7iocPlssr;                // n120
721 	__be64 p7iocCsr;                  // n110
722 	__be64 lemFir;                    // nC00
723 	__be64 lemErrorMask;              // nC18
724 	__be64 lemWOF;                    // nC40
725 	__be64 phbErrorStatus;            // nC80
726 	__be64 phbFirstErrorStatus;       // nC88
727 	__be64 phbErrorLog0;              // nCC0
728 	__be64 phbErrorLog1;              // nCC8
729 	__be64 mmioErrorStatus;           // nD00
730 	__be64 mmioFirstErrorStatus;      // nD08
731 	__be64 mmioErrorLog0;             // nD40
732 	__be64 mmioErrorLog1;             // nD48
733 	__be64 dma0ErrorStatus;           // nD80
734 	__be64 dma0FirstErrorStatus;      // nD88
735 	__be64 dma0ErrorLog0;             // nDC0
736 	__be64 dma0ErrorLog1;             // nDC8
737 	__be64 dma1ErrorStatus;           // nE00
738 	__be64 dma1FirstErrorStatus;      // nE08
739 	__be64 dma1ErrorLog0;             // nE40
740 	__be64 dma1ErrorLog1;             // nE48
741 	__be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
742 	__be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
743 };
744 
745 struct OpalIoPhb3ErrorData {
746 	struct OpalIoPhbErrorCommon common;
747 
748 	__be32 brdgCtl;
749 
750 	/* PHB3 UTL regs */
751 	__be32 portStatusReg;
752 	__be32 rootCmplxStatus;
753 	__be32 busAgentStatus;
754 
755 	/* PHB3 cfg regs */
756 	__be32 deviceStatus;
757 	__be32 slotStatus;
758 	__be32 linkStatus;
759 	__be32 devCmdStatus;
760 	__be32 devSecStatus;
761 
762 	/* cfg AER regs */
763 	__be32 rootErrorStatus;
764 	__be32 uncorrErrorStatus;
765 	__be32 corrErrorStatus;
766 	__be32 tlpHdr1;
767 	__be32 tlpHdr2;
768 	__be32 tlpHdr3;
769 	__be32 tlpHdr4;
770 	__be32 sourceId;
771 
772 	__be32 rsv3;
773 
774 	/* Record data about the call to allocate a buffer */
775 	__be64 errorClass;
776 	__be64 correlator;
777 
778 	/* PHB3 MMIO Error Regs */
779 	__be64 nFir;			/* 000 */
780 	__be64 nFirMask;		/* 003 */
781 	__be64 nFirWOF;		/* 008 */
782 	__be64 phbPlssr;		/* 120 */
783 	__be64 phbCsr;		/* 110 */
784 	__be64 lemFir;		/* C00 */
785 	__be64 lemErrorMask;		/* C18 */
786 	__be64 lemWOF;		/* C40 */
787 	__be64 phbErrorStatus;	/* C80 */
788 	__be64 phbFirstErrorStatus;	/* C88 */
789 	__be64 phbErrorLog0;		/* CC0 */
790 	__be64 phbErrorLog1;		/* CC8 */
791 	__be64 mmioErrorStatus;	/* D00 */
792 	__be64 mmioFirstErrorStatus;	/* D08 */
793 	__be64 mmioErrorLog0;		/* D40 */
794 	__be64 mmioErrorLog1;		/* D48 */
795 	__be64 dma0ErrorStatus;	/* D80 */
796 	__be64 dma0FirstErrorStatus;	/* D88 */
797 	__be64 dma0ErrorLog0;		/* DC0 */
798 	__be64 dma0ErrorLog1;		/* DC8 */
799 	__be64 dma1ErrorStatus;	/* E00 */
800 	__be64 dma1FirstErrorStatus;	/* E08 */
801 	__be64 dma1ErrorLog0;		/* E40 */
802 	__be64 dma1ErrorLog1;		/* E48 */
803 	__be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
804 	__be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
805 };
806 
807 struct OpalIoPhb4ErrorData {
808 	struct OpalIoPhbErrorCommon common;
809 
810 	__be32 brdgCtl;
811 
812 	/* PHB4 cfg regs */
813 	__be32 deviceStatus;
814 	__be32 slotStatus;
815 	__be32 linkStatus;
816 	__be32 devCmdStatus;
817 	__be32 devSecStatus;
818 
819 	/* cfg AER regs */
820 	__be32 rootErrorStatus;
821 	__be32 uncorrErrorStatus;
822 	__be32 corrErrorStatus;
823 	__be32 tlpHdr1;
824 	__be32 tlpHdr2;
825 	__be32 tlpHdr3;
826 	__be32 tlpHdr4;
827 	__be32 sourceId;
828 
829 	/* PHB4 ETU Error Regs */
830 	__be64 nFir;				/* 000 */
831 	__be64 nFirMask;			/* 003 */
832 	__be64 nFirWOF;				/* 008 */
833 	__be64 phbPlssr;			/* 120 */
834 	__be64 phbCsr;				/* 110 */
835 	__be64 lemFir;				/* C00 */
836 	__be64 lemErrorMask;			/* C18 */
837 	__be64 lemWOF;				/* C40 */
838 	__be64 phbErrorStatus;			/* C80 */
839 	__be64 phbFirstErrorStatus;		/* C88 */
840 	__be64 phbErrorLog0;			/* CC0 */
841 	__be64 phbErrorLog1;			/* CC8 */
842 	__be64 phbTxeErrorStatus;		/* D00 */
843 	__be64 phbTxeFirstErrorStatus;		/* D08 */
844 	__be64 phbTxeErrorLog0;			/* D40 */
845 	__be64 phbTxeErrorLog1;			/* D48 */
846 	__be64 phbRxeArbErrorStatus;		/* D80 */
847 	__be64 phbRxeArbFirstErrorStatus;	/* D88 */
848 	__be64 phbRxeArbErrorLog0;		/* DC0 */
849 	__be64 phbRxeArbErrorLog1;		/* DC8 */
850 	__be64 phbRxeMrgErrorStatus;		/* E00 */
851 	__be64 phbRxeMrgFirstErrorStatus;	/* E08 */
852 	__be64 phbRxeMrgErrorLog0;		/* E40 */
853 	__be64 phbRxeMrgErrorLog1;		/* E48 */
854 	__be64 phbRxeTceErrorStatus;		/* E80 */
855 	__be64 phbRxeTceFirstErrorStatus;	/* E88 */
856 	__be64 phbRxeTceErrorLog0;		/* EC0 */
857 	__be64 phbRxeTceErrorLog1;		/* EC8 */
858 
859 	/* PHB4 REGB Error Regs */
860 	__be64 phbPblErrorStatus;		/* 1900 */
861 	__be64 phbPblFirstErrorStatus;		/* 1908 */
862 	__be64 phbPblErrorLog0;			/* 1940 */
863 	__be64 phbPblErrorLog1;			/* 1948 */
864 	__be64 phbPcieDlpErrorLog1;		/* 1AA0 */
865 	__be64 phbPcieDlpErrorLog2;		/* 1AA8 */
866 	__be64 phbPcieDlpErrorStatus;		/* 1AB0 */
867 	__be64 phbRegbErrorStatus;		/* 1C00 */
868 	__be64 phbRegbFirstErrorStatus;		/* 1C08 */
869 	__be64 phbRegbErrorLog0;		/* 1C40 */
870 	__be64 phbRegbErrorLog1;		/* 1C48 */
871 
872 	__be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
873 	__be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
874 };
875 
876 enum {
877 	OPAL_REINIT_CPUS_HILE_BE	= (1 << 0),
878 	OPAL_REINIT_CPUS_HILE_LE	= (1 << 1),
879 
880 	/* These two define the base MMU mode of the host on P9
881 	 *
882 	 * On P9 Nimbus DD2.0 and Cumlus (and later), KVM can still
883 	 * create hash guests in "radix" mode with care (full core
884 	 * switch only).
885 	 */
886 	OPAL_REINIT_CPUS_MMU_HASH	= (1 << 2),
887 	OPAL_REINIT_CPUS_MMU_RADIX	= (1 << 3),
888 };
889 
890 typedef struct oppanel_line {
891 	__be64 line;
892 	__be64 line_len;
893 } oppanel_line_t;
894 
895 enum opal_prd_msg_type {
896 	OPAL_PRD_MSG_TYPE_INIT = 0,	/* HBRT --> OPAL */
897 	OPAL_PRD_MSG_TYPE_FINI,		/* HBRT/kernel --> OPAL */
898 	OPAL_PRD_MSG_TYPE_ATTN,		/* HBRT <-- OPAL */
899 	OPAL_PRD_MSG_TYPE_ATTN_ACK,	/* HBRT --> OPAL */
900 	OPAL_PRD_MSG_TYPE_OCC_ERROR,	/* HBRT <-- OPAL */
901 	OPAL_PRD_MSG_TYPE_OCC_RESET,	/* HBRT <-- OPAL */
902 };
903 
904 struct opal_prd_msg_header {
905 	uint8_t		type;
906 	uint8_t		pad[1];
907 	__be16		size;
908 };
909 
910 struct opal_prd_msg;
911 
912 #define OCC_RESET                       0
913 #define OCC_LOAD                        1
914 #define OCC_THROTTLE                    2
915 #define OCC_MAX_THROTTLE_STATUS         5
916 
917 struct opal_occ_msg {
918 	__be64 type;
919 	__be64 chip;
920 	__be64 throttle_status;
921 };
922 
923 /*
924  * SG entries
925  *
926  * WARNING: The current implementation requires each entry
927  * to represent a block that is 4k aligned *and* each block
928  * size except the last one in the list to be as well.
929  */
930 struct opal_sg_entry {
931 	__be64 data;
932 	__be64 length;
933 };
934 
935 /*
936  * Candidate image SG list.
937  *
938  * length = VER | length
939  */
940 struct opal_sg_list {
941 	__be64 length;
942 	__be64 next;
943 	struct opal_sg_entry entry[];
944 };
945 
946 /*
947  * Dump region ID range usable by the OS
948  */
949 #define OPAL_DUMP_REGION_HOST_START		0x80
950 #define OPAL_DUMP_REGION_LOG_BUF		0x80
951 #define OPAL_DUMP_REGION_HOST_END		0xFF
952 
953 /* CAPI modes for PHB */
954 enum {
955 	OPAL_PHB_CAPI_MODE_PCIE		= 0,
956 	OPAL_PHB_CAPI_MODE_CAPI		= 1,
957 	OPAL_PHB_CAPI_MODE_SNOOP_OFF    = 2,
958 	OPAL_PHB_CAPI_MODE_SNOOP_ON	= 3,
959 	OPAL_PHB_CAPI_MODE_DMA		= 4,
960 	OPAL_PHB_CAPI_MODE_DMA_TVT1	= 5,
961 };
962 
963 /* OPAL I2C request */
964 struct opal_i2c_request {
965 	uint8_t	type;
966 #define OPAL_I2C_RAW_READ	0
967 #define OPAL_I2C_RAW_WRITE	1
968 #define OPAL_I2C_SM_READ	2
969 #define OPAL_I2C_SM_WRITE	3
970 	uint8_t flags;
971 #define OPAL_I2C_ADDR_10	0x01	/* Not supported yet */
972 	uint8_t	subaddr_sz;		/* Max 4 */
973 	uint8_t reserved;
974 	__be16 addr;			/* 7 or 10 bit address */
975 	__be16 reserved2;
976 	__be32 subaddr;		/* Sub-address if any */
977 	__be32 size;			/* Data size */
978 	__be64 buffer_ra;		/* Buffer real address */
979 };
980 
981 /*
982  * EPOW status sharing (OPAL and the host)
983  *
984  * The host will pass on OPAL, a buffer of length OPAL_SYSEPOW_MAX
985  * with individual elements being 16 bits wide to fetch the system
986  * wide EPOW status. Each element in the buffer will contain the
987  * EPOW status in it's bit representation for a particular EPOW sub
988  * class as defined here. So multiple detailed EPOW status bits
989  * specific for any sub class can be represented in a single buffer
990  * element as it's bit representation.
991  */
992 
993 /* System EPOW type */
994 enum OpalSysEpow {
995 	OPAL_SYSEPOW_POWER	= 0,	/* Power EPOW */
996 	OPAL_SYSEPOW_TEMP	= 1,	/* Temperature EPOW */
997 	OPAL_SYSEPOW_COOLING	= 2,	/* Cooling EPOW */
998 	OPAL_SYSEPOW_MAX	= 3,	/* Max EPOW categories */
999 };
1000 
1001 /* Power EPOW */
1002 enum OpalSysPower {
1003 	OPAL_SYSPOWER_UPS	= 0x0001, /* System on UPS power */
1004 	OPAL_SYSPOWER_CHNG	= 0x0002, /* System power config change */
1005 	OPAL_SYSPOWER_FAIL	= 0x0004, /* System impending power failure */
1006 	OPAL_SYSPOWER_INCL	= 0x0008, /* System incomplete power */
1007 };
1008 
1009 /* Temperature EPOW */
1010 enum OpalSysTemp {
1011 	OPAL_SYSTEMP_AMB	= 0x0001, /* System over ambient temperature */
1012 	OPAL_SYSTEMP_INT	= 0x0002, /* System over internal temperature */
1013 	OPAL_SYSTEMP_HMD	= 0x0004, /* System over ambient humidity */
1014 };
1015 
1016 /* Cooling EPOW */
1017 enum OpalSysCooling {
1018 	OPAL_SYSCOOL_INSF	= 0x0001, /* System insufficient cooling */
1019 };
1020 
1021 /* Argument to OPAL_CEC_REBOOT2() */
1022 enum {
1023 	OPAL_REBOOT_NORMAL		= 0,
1024 	OPAL_REBOOT_PLATFORM_ERROR	= 1,
1025 };
1026 
1027 /* Argument to OPAL_PCI_TCE_KILL */
1028 enum {
1029 	OPAL_PCI_TCE_KILL_PAGES,
1030 	OPAL_PCI_TCE_KILL_PE,
1031 	OPAL_PCI_TCE_KILL_ALL,
1032 };
1033 
1034 /* The xive operation mode indicates the active "API" and
1035  * corresponds to the "mode" parameter of the opal_xive_reset()
1036  * call
1037  */
1038 enum {
1039 	OPAL_XIVE_MODE_EMU	= 0,
1040 	OPAL_XIVE_MODE_EXPL	= 1,
1041 };
1042 
1043 /* Flags for OPAL_XIVE_GET_IRQ_INFO */
1044 enum {
1045 	OPAL_XIVE_IRQ_TRIGGER_PAGE	= 0x00000001,
1046 	OPAL_XIVE_IRQ_STORE_EOI		= 0x00000002,
1047 	OPAL_XIVE_IRQ_LSI		= 0x00000004,
1048 	OPAL_XIVE_IRQ_SHIFT_BUG		= 0x00000008,
1049 	OPAL_XIVE_IRQ_MASK_VIA_FW	= 0x00000010,
1050 	OPAL_XIVE_IRQ_EOI_VIA_FW	= 0x00000020,
1051 };
1052 
1053 /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
1054 enum {
1055 	OPAL_XIVE_EQ_ENABLED		= 0x00000001,
1056 	OPAL_XIVE_EQ_ALWAYS_NOTIFY	= 0x00000002,
1057 	OPAL_XIVE_EQ_ESCALATE		= 0x00000004,
1058 };
1059 
1060 /* Flags for OPAL_XIVE_GET/SET_VP_INFO */
1061 enum {
1062 	OPAL_XIVE_VP_ENABLED		= 0x00000001,
1063 };
1064 
1065 /* "Any chip" replacement for chip ID for allocation functions */
1066 enum {
1067 	OPAL_XIVE_ANY_CHIP		= 0xffffffff,
1068 };
1069 
1070 /* Xive sync options */
1071 enum {
1072 	/* This bits are cumulative, arg is a girq */
1073 	XIVE_SYNC_EAS			= 0x00000001, /* Sync irq source */
1074 	XIVE_SYNC_QUEUE			= 0x00000002, /* Sync irq target */
1075 };
1076 
1077 /* Dump options */
1078 enum {
1079 	XIVE_DUMP_TM_HYP	= 0,
1080 	XIVE_DUMP_TM_POOL	= 1,
1081 	XIVE_DUMP_TM_OS		= 2,
1082 	XIVE_DUMP_TM_USER	= 3,
1083 	XIVE_DUMP_VP		= 4,
1084 	XIVE_DUMP_EMU_STATE	= 5,
1085 };
1086 
1087 #endif /* __ASSEMBLY__ */
1088 
1089 #endif /* __OPAL_API_H */
1090