1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H 3 #define _ASM_POWERPC_NOHASH_PGTABLE_H 4 5 #if defined(CONFIG_PPC64) 6 #include <asm/nohash/64/pgtable.h> 7 #else 8 #include <asm/nohash/32/pgtable.h> 9 #endif 10 11 /* Permission masks used for kernel mappings */ 12 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW) 13 #define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE) 14 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE | _PAGE_GUARDED) 15 #define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX) 16 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO) 17 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX) 18 19 #ifndef __ASSEMBLY__ 20 21 /* Generic accessors to PTE bits */ 22 #ifndef pte_write 23 static inline int pte_write(pte_t pte) 24 { 25 return pte_val(pte) & _PAGE_RW; 26 } 27 #endif 28 static inline int pte_read(pte_t pte) { return 1; } 29 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 30 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 31 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 32 static inline bool pte_hashpte(pte_t pte) { return false; } 33 static inline bool pte_ci(pte_t pte) { return pte_val(pte) & _PAGE_NO_CACHE; } 34 static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 35 36 #ifdef CONFIG_NUMA_BALANCING 37 /* 38 * These work without NUMA balancing but the kernel does not care. See the 39 * comment in include/linux/pgtable.h . On powerpc, this will only 40 * work for user pages and always return true for kernel pages. 41 */ 42 static inline int pte_protnone(pte_t pte) 43 { 44 return pte_present(pte) && !pte_user(pte); 45 } 46 47 static inline int pmd_protnone(pmd_t pmd) 48 { 49 return pte_protnone(pmd_pte(pmd)); 50 } 51 #endif /* CONFIG_NUMA_BALANCING */ 52 53 static inline int pte_present(pte_t pte) 54 { 55 return pte_val(pte) & _PAGE_PRESENT; 56 } 57 58 static inline bool pte_hw_valid(pte_t pte) 59 { 60 return pte_val(pte) & _PAGE_PRESENT; 61 } 62 63 /* 64 * Don't just check for any non zero bits in __PAGE_USER, since for book3e 65 * and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in 66 * _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too. 67 */ 68 #ifndef pte_user 69 static inline bool pte_user(pte_t pte) 70 { 71 return (pte_val(pte) & _PAGE_USER) == _PAGE_USER; 72 } 73 #endif 74 75 /* 76 * We only find page table entry in the last level 77 * Hence no need for other accessors 78 */ 79 #define pte_access_permitted pte_access_permitted 80 static inline bool pte_access_permitted(pte_t pte, bool write) 81 { 82 /* 83 * A read-only access is controlled by _PAGE_USER bit. 84 * We have _PAGE_READ set for WRITE and EXECUTE 85 */ 86 if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 87 return false; 88 89 if (write && !pte_write(pte)) 90 return false; 91 92 return true; 93 } 94 95 /* Conversion functions: convert a page and protection to a page entry, 96 * and a page entry and page directory to the page they refer to. 97 * 98 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 99 * long for now. 100 */ 101 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) { 102 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 103 pgprot_val(pgprot)); } 104 105 /* Generic modifiers for PTE bits */ 106 static inline pte_t pte_exprotect(pte_t pte) 107 { 108 return __pte(pte_val(pte) & ~_PAGE_EXEC); 109 } 110 111 static inline pte_t pte_mkclean(pte_t pte) 112 { 113 return __pte(pte_val(pte) & ~_PAGE_DIRTY); 114 } 115 116 static inline pte_t pte_mkold(pte_t pte) 117 { 118 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 119 } 120 121 static inline pte_t pte_mkspecial(pte_t pte) 122 { 123 return __pte(pte_val(pte) | _PAGE_SPECIAL); 124 } 125 126 #ifndef pte_mkhuge 127 static inline pte_t pte_mkhuge(pte_t pte) 128 { 129 return __pte(pte_val(pte)); 130 } 131 #endif 132 133 #ifndef pte_mkprivileged 134 static inline pte_t pte_mkprivileged(pte_t pte) 135 { 136 return __pte(pte_val(pte) & ~_PAGE_USER); 137 } 138 #endif 139 140 #ifndef pte_mkuser 141 static inline pte_t pte_mkuser(pte_t pte) 142 { 143 return __pte(pte_val(pte) | _PAGE_USER); 144 } 145 #endif 146 147 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 148 { 149 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 150 } 151 152 static inline int pte_swp_exclusive(pte_t pte) 153 { 154 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE; 155 } 156 157 static inline pte_t pte_swp_mkexclusive(pte_t pte) 158 { 159 return __pte(pte_val(pte) | _PAGE_SWP_EXCLUSIVE); 160 } 161 162 static inline pte_t pte_swp_clear_exclusive(pte_t pte) 163 { 164 return __pte(pte_val(pte) & ~_PAGE_SWP_EXCLUSIVE); 165 } 166 167 /* This low level function performs the actual PTE insertion 168 * Setting the PTE depends on the MMU type and other factors. It's 169 * an horrible mess that I'm not going to try to clean up now but 170 * I'm keeping it in one place rather than spread around 171 */ 172 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 173 pte_t *ptep, pte_t pte, int percpu) 174 { 175 /* Second case is 32-bit with 64-bit PTE. In this case, we 176 * can just store as long as we do the two halves in the right order 177 * with a barrier in between. 178 * In the percpu case, we also fallback to the simple update 179 */ 180 if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) { 181 __asm__ __volatile__("\ 182 stw%X0 %2,%0\n\ 183 mbar\n\ 184 stw%X1 %L2,%1" 185 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 186 : "r" (pte) : "memory"); 187 return; 188 } 189 /* Anything else just stores the PTE normally. That covers all 64-bit 190 * cases, and 32-bit non-hash with 32-bit PTEs. 191 */ 192 #if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES) 193 ptep->pte3 = ptep->pte2 = ptep->pte1 = ptep->pte = pte_val(pte); 194 #else 195 *ptep = pte; 196 #endif 197 198 /* 199 * With hardware tablewalk, a sync is needed to ensure that 200 * subsequent accesses see the PTE we just wrote. Unlike userspace 201 * mappings, we can't tolerate spurious faults, so make sure 202 * the new PTE will be seen the first time. 203 */ 204 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr)) 205 mb(); 206 } 207 208 209 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 210 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 211 pte_t *ptep, pte_t entry, int dirty); 212 213 /* 214 * Macro to mark a page protection value as "uncacheable". 215 */ 216 217 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 218 _PAGE_WRITETHRU) 219 220 #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 221 _PAGE_NO_CACHE | _PAGE_GUARDED)) 222 223 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 224 _PAGE_NO_CACHE)) 225 226 #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 227 _PAGE_COHERENT)) 228 229 #if _PAGE_WRITETHRU != 0 230 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 231 _PAGE_COHERENT | _PAGE_WRITETHRU)) 232 #else 233 #define pgprot_cached_wthru(prot) pgprot_noncached(prot) 234 #endif 235 236 #define pgprot_cached_noncoherent(prot) \ 237 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL)) 238 239 #define pgprot_writecombine pgprot_noncached_wc 240 241 struct file; 242 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 243 unsigned long size, pgprot_t vma_prot); 244 #define __HAVE_PHYS_MEM_ACCESS_PROT 245 246 #ifdef CONFIG_HUGETLB_PAGE 247 static inline int hugepd_ok(hugepd_t hpd) 248 { 249 #ifdef CONFIG_PPC_8xx 250 return ((hpd_val(hpd) & _PMD_PAGE_MASK) == _PMD_PAGE_8M); 251 #else 252 /* We clear the top bit to indicate hugepd */ 253 return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0); 254 #endif 255 } 256 257 static inline int pmd_huge(pmd_t pmd) 258 { 259 return 0; 260 } 261 262 static inline int pud_huge(pud_t pud) 263 { 264 return 0; 265 } 266 267 #define is_hugepd(hpd) (hugepd_ok(hpd)) 268 #endif 269 270 /* 271 * This gets called at the end of handling a page fault, when 272 * the kernel has put a new PTE into the page table for the process. 273 * We use it to ensure coherency between the i-cache and d-cache 274 * for the page which has just been mapped in. 275 */ 276 #if defined(CONFIG_PPC_E500) && defined(CONFIG_HUGETLB_PAGE) 277 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma, 278 unsigned long address, pte_t *ptep, unsigned int nr); 279 #else 280 static inline void update_mmu_cache_range(struct vm_fault *vmf, 281 struct vm_area_struct *vma, unsigned long address, 282 pte_t *ptep, unsigned int nr) {} 283 #endif 284 285 #endif /* __ASSEMBLY__ */ 286 #endif 287