1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
3 #define _ASM_POWERPC_NOHASH_PGTABLE_H
4 
5 #if defined(CONFIG_PPC64)
6 #include <asm/nohash/64/pgtable.h>
7 #else
8 #include <asm/nohash/32/pgtable.h>
9 #endif
10 
11 #ifndef __ASSEMBLY__
12 
13 /* Generic accessors to PTE bits */
14 static inline int pte_write(pte_t pte)
15 {
16 	return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO;
17 }
18 static inline int pte_read(pte_t pte)		{ return 1; }
19 static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }
20 static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }
21 static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }
22 static inline int pte_none(pte_t pte)		{ return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
23 static inline pgprot_t pte_pgprot(pte_t pte)	{ return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
24 
25 #ifdef CONFIG_NUMA_BALANCING
26 /*
27  * These work without NUMA balancing but the kernel does not care. See the
28  * comment in include/asm-generic/pgtable.h . On powerpc, this will only
29  * work for user pages and always return true for kernel pages.
30  */
31 static inline int pte_protnone(pte_t pte)
32 {
33 	return (pte_val(pte) &
34 		(_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
35 }
36 
37 static inline int pmd_protnone(pmd_t pmd)
38 {
39 	return pte_protnone(pmd_pte(pmd));
40 }
41 #endif /* CONFIG_NUMA_BALANCING */
42 
43 static inline int pte_present(pte_t pte)
44 {
45 	return pte_val(pte) & _PAGE_PRESENT;
46 }
47 
48 /* Conversion functions: convert a page and protection to a page entry,
49  * and a page entry and page directory to the page they refer to.
50  *
51  * Even if PTEs can be unsigned long long, a PFN is always an unsigned
52  * long for now.
53  */
54 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
55 	return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
56 		     pgprot_val(pgprot)); }
57 static inline unsigned long pte_pfn(pte_t pte)	{
58 	return pte_val(pte) >> PTE_RPN_SHIFT; }
59 
60 /* Generic modifiers for PTE bits */
61 static inline pte_t pte_wrprotect(pte_t pte)
62 {
63 	pte_basic_t ptev;
64 
65 	ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE);
66 	ptev |= _PAGE_RO;
67 	return __pte(ptev);
68 }
69 
70 static inline pte_t pte_mkclean(pte_t pte)
71 {
72 	return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
73 }
74 
75 static inline pte_t pte_mkold(pte_t pte)
76 {
77 	return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
78 }
79 
80 static inline pte_t pte_mkwrite(pte_t pte)
81 {
82 	pte_basic_t ptev;
83 
84 	ptev = pte_val(pte) & ~_PAGE_RO;
85 	ptev |= _PAGE_RW;
86 	return __pte(ptev);
87 }
88 
89 static inline pte_t pte_mkdirty(pte_t pte)
90 {
91 	return __pte(pte_val(pte) | _PAGE_DIRTY);
92 }
93 
94 static inline pte_t pte_mkyoung(pte_t pte)
95 {
96 	return __pte(pte_val(pte) | _PAGE_ACCESSED);
97 }
98 
99 static inline pte_t pte_mkspecial(pte_t pte)
100 {
101 	return __pte(pte_val(pte) | _PAGE_SPECIAL);
102 }
103 
104 static inline pte_t pte_mkhuge(pte_t pte)
105 {
106 	return pte;
107 }
108 
109 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
110 {
111 	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
112 }
113 
114 /* Insert a PTE, top-level function is out of line. It uses an inline
115  * low level function in the respective pgtable-* files
116  */
117 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
118 		       pte_t pte);
119 
120 /* This low level function performs the actual PTE insertion
121  * Setting the PTE depends on the MMU type and other factors. It's
122  * an horrible mess that I'm not going to try to clean up now but
123  * I'm keeping it in one place rather than spread around
124  */
125 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
126 				pte_t *ptep, pte_t pte, int percpu)
127 {
128 #if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
129 	/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
130 	 * helper pte_update() which does an atomic update. We need to do that
131 	 * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
132 	 * per-CPU PTE such as a kmap_atomic, we do a simple update preserving
133 	 * the hash bits instead (ie, same as the non-SMP case)
134 	 */
135 	if (percpu)
136 		*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
137 			      | (pte_val(pte) & ~_PAGE_HASHPTE));
138 	else
139 		pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
140 
141 #elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
142 	/* Second case is 32-bit with 64-bit PTE.  In this case, we
143 	 * can just store as long as we do the two halves in the right order
144 	 * with a barrier in between. This is possible because we take care,
145 	 * in the hash code, to pre-invalidate if the PTE was already hashed,
146 	 * which synchronizes us with any concurrent invalidation.
147 	 * In the percpu case, we also fallback to the simple update preserving
148 	 * the hash bits
149 	 */
150 	if (percpu) {
151 		*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
152 			      | (pte_val(pte) & ~_PAGE_HASHPTE));
153 		return;
154 	}
155 #if _PAGE_HASHPTE != 0
156 	if (pte_val(*ptep) & _PAGE_HASHPTE)
157 		flush_hash_entry(mm, ptep, addr);
158 #endif
159 	__asm__ __volatile__("\
160 		stw%U0%X0 %2,%0\n\
161 		eieio\n\
162 		stw%U0%X0 %L2,%1"
163 	: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
164 	: "r" (pte) : "memory");
165 
166 #elif defined(CONFIG_PPC_STD_MMU_32)
167 	/* Third case is 32-bit hash table in UP mode, we need to preserve
168 	 * the _PAGE_HASHPTE bit since we may not have invalidated the previous
169 	 * translation in the hash yet (done in a subsequent flush_tlb_xxx())
170 	 * and see we need to keep track that this PTE needs invalidating
171 	 */
172 	*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
173 		      | (pte_val(pte) & ~_PAGE_HASHPTE));
174 
175 #else
176 	/* Anything else just stores the PTE normally. That covers all 64-bit
177 	 * cases, and 32-bit non-hash with 32-bit PTEs.
178 	 */
179 	*ptep = pte;
180 
181 #ifdef CONFIG_PPC_BOOK3E_64
182 	/*
183 	 * With hardware tablewalk, a sync is needed to ensure that
184 	 * subsequent accesses see the PTE we just wrote.  Unlike userspace
185 	 * mappings, we can't tolerate spurious faults, so make sure
186 	 * the new PTE will be seen the first time.
187 	 */
188 	if (is_kernel_addr(addr))
189 		mb();
190 #endif
191 #endif
192 }
193 
194 
195 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
196 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
197 				 pte_t *ptep, pte_t entry, int dirty);
198 
199 /*
200  * Macro to mark a page protection value as "uncacheable".
201  */
202 
203 #define _PAGE_CACHE_CTL	(_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
204 			 _PAGE_WRITETHRU)
205 
206 #define pgprot_noncached(prot)	  (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
207 				            _PAGE_NO_CACHE | _PAGE_GUARDED))
208 
209 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
210 				            _PAGE_NO_CACHE))
211 
212 #define pgprot_cached(prot)       (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
213 				            _PAGE_COHERENT))
214 
215 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
216 				            _PAGE_COHERENT | _PAGE_WRITETHRU))
217 
218 #define pgprot_cached_noncoherent(prot) \
219 		(__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
220 
221 #define pgprot_writecombine pgprot_noncached_wc
222 
223 struct file;
224 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
225 				     unsigned long size, pgprot_t vma_prot);
226 #define __HAVE_PHYS_MEM_ACCESS_PROT
227 
228 #ifdef CONFIG_HUGETLB_PAGE
229 static inline int hugepd_ok(hugepd_t hpd)
230 {
231 #ifdef CONFIG_PPC_8xx
232 	return ((hpd_val(hpd) & 0x4) != 0);
233 #else
234 	/* We clear the top bit to indicate hugepd */
235 	return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0);
236 #endif
237 }
238 
239 static inline int pmd_huge(pmd_t pmd)
240 {
241 	return 0;
242 }
243 
244 static inline int pud_huge(pud_t pud)
245 {
246 	return 0;
247 }
248 
249 static inline int pgd_huge(pgd_t pgd)
250 {
251 	return 0;
252 }
253 #define pgd_huge		pgd_huge
254 
255 #define is_hugepd(hpd)		(hugepd_ok(hpd))
256 #endif
257 
258 #endif /* __ASSEMBLY__ */
259 #endif
260