1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H 3 #define _ASM_POWERPC_NOHASH_PGTABLE_H 4 5 #if defined(CONFIG_PPC64) 6 #include <asm/nohash/64/pgtable.h> 7 #else 8 #include <asm/nohash/32/pgtable.h> 9 #endif 10 11 #ifndef __ASSEMBLY__ 12 13 /* Generic accessors to PTE bits */ 14 static inline int pte_write(pte_t pte) 15 { 16 return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; 17 } 18 static inline int pte_read(pte_t pte) { return 1; } 19 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 20 static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 21 static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 22 static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 23 24 #ifdef CONFIG_NUMA_BALANCING 25 /* 26 * These work without NUMA balancing but the kernel does not care. See the 27 * comment in include/asm-generic/pgtable.h . On powerpc, this will only 28 * work for user pages and always return true for kernel pages. 29 */ 30 static inline int pte_protnone(pte_t pte) 31 { 32 return (pte_val(pte) & 33 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT; 34 } 35 36 static inline int pmd_protnone(pmd_t pmd) 37 { 38 return pte_protnone(pmd_pte(pmd)); 39 } 40 #endif /* CONFIG_NUMA_BALANCING */ 41 42 static inline int pte_present(pte_t pte) 43 { 44 return pte_val(pte) & _PAGE_PRESENT; 45 } 46 47 /* 48 * We only find page table entry in the last level 49 * Hence no need for other accessors 50 */ 51 #define pte_access_permitted pte_access_permitted 52 static inline bool pte_access_permitted(pte_t pte, bool write) 53 { 54 unsigned long pteval = pte_val(pte); 55 /* 56 * A read-only access is controlled by _PAGE_USER bit. 57 * We have _PAGE_READ set for WRITE and EXECUTE 58 */ 59 unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_USER; 60 61 if (write) 62 need_pte_bits |= _PAGE_WRITE; 63 64 if ((pteval & need_pte_bits) != need_pte_bits) 65 return false; 66 67 return true; 68 } 69 70 /* Conversion functions: convert a page and protection to a page entry, 71 * and a page entry and page directory to the page they refer to. 72 * 73 * Even if PTEs can be unsigned long long, a PFN is always an unsigned 74 * long for now. 75 */ 76 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) { 77 return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 78 pgprot_val(pgprot)); } 79 static inline unsigned long pte_pfn(pte_t pte) { 80 return pte_val(pte) >> PTE_RPN_SHIFT; } 81 82 /* Generic modifiers for PTE bits */ 83 static inline pte_t pte_wrprotect(pte_t pte) 84 { 85 pte_basic_t ptev; 86 87 ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE); 88 ptev |= _PAGE_RO; 89 return __pte(ptev); 90 } 91 92 static inline pte_t pte_mkclean(pte_t pte) 93 { 94 return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE)); 95 } 96 97 static inline pte_t pte_mkold(pte_t pte) 98 { 99 return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 100 } 101 102 static inline pte_t pte_mkwrite(pte_t pte) 103 { 104 pte_basic_t ptev; 105 106 ptev = pte_val(pte) & ~_PAGE_RO; 107 ptev |= _PAGE_RW; 108 return __pte(ptev); 109 } 110 111 static inline pte_t pte_mkdirty(pte_t pte) 112 { 113 return __pte(pte_val(pte) | _PAGE_DIRTY); 114 } 115 116 static inline pte_t pte_mkyoung(pte_t pte) 117 { 118 return __pte(pte_val(pte) | _PAGE_ACCESSED); 119 } 120 121 static inline pte_t pte_mkspecial(pte_t pte) 122 { 123 return __pte(pte_val(pte) | _PAGE_SPECIAL); 124 } 125 126 static inline pte_t pte_mkhuge(pte_t pte) 127 { 128 return __pte(pte_val(pte) | _PAGE_HUGE); 129 } 130 131 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 132 { 133 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 134 } 135 136 /* Insert a PTE, top-level function is out of line. It uses an inline 137 * low level function in the respective pgtable-* files 138 */ 139 extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 140 pte_t pte); 141 142 /* This low level function performs the actual PTE insertion 143 * Setting the PTE depends on the MMU type and other factors. It's 144 * an horrible mess that I'm not going to try to clean up now but 145 * I'm keeping it in one place rather than spread around 146 */ 147 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 148 pte_t *ptep, pte_t pte, int percpu) 149 { 150 /* Second case is 32-bit with 64-bit PTE. In this case, we 151 * can just store as long as we do the two halves in the right order 152 * with a barrier in between. 153 * In the percpu case, we also fallback to the simple update 154 */ 155 if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) { 156 __asm__ __volatile__("\ 157 stw%U0%X0 %2,%0\n\ 158 eieio\n\ 159 stw%U0%X0 %L2,%1" 160 : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 161 : "r" (pte) : "memory"); 162 return; 163 } 164 /* Anything else just stores the PTE normally. That covers all 64-bit 165 * cases, and 32-bit non-hash with 32-bit PTEs. 166 */ 167 *ptep = pte; 168 169 /* 170 * With hardware tablewalk, a sync is needed to ensure that 171 * subsequent accesses see the PTE we just wrote. Unlike userspace 172 * mappings, we can't tolerate spurious faults, so make sure 173 * the new PTE will be seen the first time. 174 */ 175 if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr)) 176 mb(); 177 } 178 179 180 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 181 extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 182 pte_t *ptep, pte_t entry, int dirty); 183 184 /* 185 * Macro to mark a page protection value as "uncacheable". 186 */ 187 188 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 189 _PAGE_WRITETHRU) 190 191 #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 192 _PAGE_NO_CACHE | _PAGE_GUARDED)) 193 194 #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 195 _PAGE_NO_CACHE)) 196 197 #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 198 _PAGE_COHERENT)) 199 200 #if _PAGE_WRITETHRU != 0 201 #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 202 _PAGE_COHERENT | _PAGE_WRITETHRU)) 203 #endif 204 205 #define pgprot_cached_noncoherent(prot) \ 206 (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL)) 207 208 #define pgprot_writecombine pgprot_noncached_wc 209 210 struct file; 211 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 212 unsigned long size, pgprot_t vma_prot); 213 #define __HAVE_PHYS_MEM_ACCESS_PROT 214 215 #ifdef CONFIG_HUGETLB_PAGE 216 static inline int hugepd_ok(hugepd_t hpd) 217 { 218 #ifdef CONFIG_PPC_8xx 219 return ((hpd_val(hpd) & 0x4) != 0); 220 #else 221 /* We clear the top bit to indicate hugepd */ 222 return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0); 223 #endif 224 } 225 226 static inline int pmd_huge(pmd_t pmd) 227 { 228 return 0; 229 } 230 231 static inline int pud_huge(pud_t pud) 232 { 233 return 0; 234 } 235 236 static inline int pgd_huge(pgd_t pgd) 237 { 238 return 0; 239 } 240 #define pgd_huge pgd_huge 241 242 #define is_hugepd(hpd) (hugepd_ok(hpd)) 243 #endif 244 245 #endif /* __ASSEMBLY__ */ 246 #endif 247