1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 217ed9e31SAneesh Kumar K.V #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H 317ed9e31SAneesh Kumar K.V #define _ASM_POWERPC_NOHASH_PGTABLE_H 417ed9e31SAneesh Kumar K.V 517ed9e31SAneesh Kumar K.V #if defined(CONFIG_PPC64) 617ed9e31SAneesh Kumar K.V #include <asm/nohash/64/pgtable.h> 717ed9e31SAneesh Kumar K.V #else 817ed9e31SAneesh Kumar K.V #include <asm/nohash/32/pgtable.h> 917ed9e31SAneesh Kumar K.V #endif 1017ed9e31SAneesh Kumar K.V 1117ed9e31SAneesh Kumar K.V #ifndef __ASSEMBLY__ 1217ed9e31SAneesh Kumar K.V 1317ed9e31SAneesh Kumar K.V /* Generic accessors to PTE bits */ 1417ed9e31SAneesh Kumar K.V static inline int pte_write(pte_t pte) 1517ed9e31SAneesh Kumar K.V { 1617ed9e31SAneesh Kumar K.V return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; 1717ed9e31SAneesh Kumar K.V } 18ca8afd40SChristophe Leroy static inline int pte_read(pte_t pte) { return 1; } 1917ed9e31SAneesh Kumar K.V static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 2017ed9e31SAneesh Kumar K.V static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 2117ed9e31SAneesh Kumar K.V static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 2217ed9e31SAneesh Kumar K.V static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 2317ed9e31SAneesh Kumar K.V static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 2417ed9e31SAneesh Kumar K.V 2517ed9e31SAneesh Kumar K.V #ifdef CONFIG_NUMA_BALANCING 2617ed9e31SAneesh Kumar K.V /* 2717ed9e31SAneesh Kumar K.V * These work without NUMA balancing but the kernel does not care. See the 2817ed9e31SAneesh Kumar K.V * comment in include/asm-generic/pgtable.h . On powerpc, this will only 2917ed9e31SAneesh Kumar K.V * work for user pages and always return true for kernel pages. 3017ed9e31SAneesh Kumar K.V */ 3117ed9e31SAneesh Kumar K.V static inline int pte_protnone(pte_t pte) 3217ed9e31SAneesh Kumar K.V { 3317ed9e31SAneesh Kumar K.V return (pte_val(pte) & 3417ed9e31SAneesh Kumar K.V (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT; 3517ed9e31SAneesh Kumar K.V } 3617ed9e31SAneesh Kumar K.V 3717ed9e31SAneesh Kumar K.V static inline int pmd_protnone(pmd_t pmd) 3817ed9e31SAneesh Kumar K.V { 3917ed9e31SAneesh Kumar K.V return pte_protnone(pmd_pte(pmd)); 4017ed9e31SAneesh Kumar K.V } 4117ed9e31SAneesh Kumar K.V #endif /* CONFIG_NUMA_BALANCING */ 4217ed9e31SAneesh Kumar K.V 4317ed9e31SAneesh Kumar K.V static inline int pte_present(pte_t pte) 4417ed9e31SAneesh Kumar K.V { 4517ed9e31SAneesh Kumar K.V return pte_val(pte) & _PAGE_PRESENT; 4617ed9e31SAneesh Kumar K.V } 4717ed9e31SAneesh Kumar K.V 485769beafSAneesh Kumar K.V /* 495769beafSAneesh Kumar K.V * We only find page table entry in the last level 505769beafSAneesh Kumar K.V * Hence no need for other accessors 515769beafSAneesh Kumar K.V */ 525769beafSAneesh Kumar K.V #define pte_access_permitted pte_access_permitted 535769beafSAneesh Kumar K.V static inline bool pte_access_permitted(pte_t pte, bool write) 545769beafSAneesh Kumar K.V { 555769beafSAneesh Kumar K.V unsigned long pteval = pte_val(pte); 565769beafSAneesh Kumar K.V /* 575769beafSAneesh Kumar K.V * A read-only access is controlled by _PAGE_USER bit. 585769beafSAneesh Kumar K.V * We have _PAGE_READ set for WRITE and EXECUTE 595769beafSAneesh Kumar K.V */ 605769beafSAneesh Kumar K.V unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_USER; 615769beafSAneesh Kumar K.V 625769beafSAneesh Kumar K.V if (write) 635769beafSAneesh Kumar K.V need_pte_bits |= _PAGE_WRITE; 645769beafSAneesh Kumar K.V 655769beafSAneesh Kumar K.V if ((pteval & need_pte_bits) != need_pte_bits) 665769beafSAneesh Kumar K.V return false; 675769beafSAneesh Kumar K.V 685769beafSAneesh Kumar K.V return true; 695769beafSAneesh Kumar K.V } 705769beafSAneesh Kumar K.V 7117ed9e31SAneesh Kumar K.V /* Conversion functions: convert a page and protection to a page entry, 7217ed9e31SAneesh Kumar K.V * and a page entry and page directory to the page they refer to. 7317ed9e31SAneesh Kumar K.V * 7417ed9e31SAneesh Kumar K.V * Even if PTEs can be unsigned long long, a PFN is always an unsigned 7517ed9e31SAneesh Kumar K.V * long for now. 7617ed9e31SAneesh Kumar K.V */ 7717ed9e31SAneesh Kumar K.V static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) { 7817ed9e31SAneesh Kumar K.V return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 7917ed9e31SAneesh Kumar K.V pgprot_val(pgprot)); } 8017ed9e31SAneesh Kumar K.V static inline unsigned long pte_pfn(pte_t pte) { 8117ed9e31SAneesh Kumar K.V return pte_val(pte) >> PTE_RPN_SHIFT; } 8217ed9e31SAneesh Kumar K.V 8317ed9e31SAneesh Kumar K.V /* Generic modifiers for PTE bits */ 8417ed9e31SAneesh Kumar K.V static inline pte_t pte_wrprotect(pte_t pte) 8517ed9e31SAneesh Kumar K.V { 8617ed9e31SAneesh Kumar K.V pte_basic_t ptev; 8717ed9e31SAneesh Kumar K.V 8817ed9e31SAneesh Kumar K.V ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE); 8917ed9e31SAneesh Kumar K.V ptev |= _PAGE_RO; 9017ed9e31SAneesh Kumar K.V return __pte(ptev); 9117ed9e31SAneesh Kumar K.V } 9217ed9e31SAneesh Kumar K.V 9317ed9e31SAneesh Kumar K.V static inline pte_t pte_mkclean(pte_t pte) 9417ed9e31SAneesh Kumar K.V { 9517ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE)); 9617ed9e31SAneesh Kumar K.V } 9717ed9e31SAneesh Kumar K.V 9817ed9e31SAneesh Kumar K.V static inline pte_t pte_mkold(pte_t pte) 9917ed9e31SAneesh Kumar K.V { 10017ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 10117ed9e31SAneesh Kumar K.V } 10217ed9e31SAneesh Kumar K.V 10317ed9e31SAneesh Kumar K.V static inline pte_t pte_mkwrite(pte_t pte) 10417ed9e31SAneesh Kumar K.V { 10517ed9e31SAneesh Kumar K.V pte_basic_t ptev; 10617ed9e31SAneesh Kumar K.V 10717ed9e31SAneesh Kumar K.V ptev = pte_val(pte) & ~_PAGE_RO; 10817ed9e31SAneesh Kumar K.V ptev |= _PAGE_RW; 10917ed9e31SAneesh Kumar K.V return __pte(ptev); 11017ed9e31SAneesh Kumar K.V } 11117ed9e31SAneesh Kumar K.V 11217ed9e31SAneesh Kumar K.V static inline pte_t pte_mkdirty(pte_t pte) 11317ed9e31SAneesh Kumar K.V { 11417ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) | _PAGE_DIRTY); 11517ed9e31SAneesh Kumar K.V } 11617ed9e31SAneesh Kumar K.V 11717ed9e31SAneesh Kumar K.V static inline pte_t pte_mkyoung(pte_t pte) 11817ed9e31SAneesh Kumar K.V { 11917ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) | _PAGE_ACCESSED); 12017ed9e31SAneesh Kumar K.V } 12117ed9e31SAneesh Kumar K.V 12217ed9e31SAneesh Kumar K.V static inline pte_t pte_mkspecial(pte_t pte) 12317ed9e31SAneesh Kumar K.V { 12417ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) | _PAGE_SPECIAL); 12517ed9e31SAneesh Kumar K.V } 12617ed9e31SAneesh Kumar K.V 12717ed9e31SAneesh Kumar K.V static inline pte_t pte_mkhuge(pte_t pte) 12817ed9e31SAneesh Kumar K.V { 12917ed9e31SAneesh Kumar K.V return pte; 13017ed9e31SAneesh Kumar K.V } 13117ed9e31SAneesh Kumar K.V 13217ed9e31SAneesh Kumar K.V static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 13317ed9e31SAneesh Kumar K.V { 13417ed9e31SAneesh Kumar K.V return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 13517ed9e31SAneesh Kumar K.V } 13617ed9e31SAneesh Kumar K.V 13717ed9e31SAneesh Kumar K.V /* Insert a PTE, top-level function is out of line. It uses an inline 13817ed9e31SAneesh Kumar K.V * low level function in the respective pgtable-* files 13917ed9e31SAneesh Kumar K.V */ 14017ed9e31SAneesh Kumar K.V extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 14117ed9e31SAneesh Kumar K.V pte_t pte); 14217ed9e31SAneesh Kumar K.V 14317ed9e31SAneesh Kumar K.V /* This low level function performs the actual PTE insertion 14417ed9e31SAneesh Kumar K.V * Setting the PTE depends on the MMU type and other factors. It's 14517ed9e31SAneesh Kumar K.V * an horrible mess that I'm not going to try to clean up now but 14617ed9e31SAneesh Kumar K.V * I'm keeping it in one place rather than spread around 14717ed9e31SAneesh Kumar K.V */ 14817ed9e31SAneesh Kumar K.V static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 14917ed9e31SAneesh Kumar K.V pte_t *ptep, pte_t pte, int percpu) 15017ed9e31SAneesh Kumar K.V { 15117ed9e31SAneesh Kumar K.V #if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT) 15217ed9e31SAneesh Kumar K.V /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the 15317ed9e31SAneesh Kumar K.V * helper pte_update() which does an atomic update. We need to do that 15417ed9e31SAneesh Kumar K.V * because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a 15517ed9e31SAneesh Kumar K.V * per-CPU PTE such as a kmap_atomic, we do a simple update preserving 15617ed9e31SAneesh Kumar K.V * the hash bits instead (ie, same as the non-SMP case) 15717ed9e31SAneesh Kumar K.V */ 15817ed9e31SAneesh Kumar K.V if (percpu) 15917ed9e31SAneesh Kumar K.V *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 16017ed9e31SAneesh Kumar K.V | (pte_val(pte) & ~_PAGE_HASHPTE)); 16117ed9e31SAneesh Kumar K.V else 16217ed9e31SAneesh Kumar K.V pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte)); 16317ed9e31SAneesh Kumar K.V 16417ed9e31SAneesh Kumar K.V #elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) 16517ed9e31SAneesh Kumar K.V /* Second case is 32-bit with 64-bit PTE. In this case, we 16617ed9e31SAneesh Kumar K.V * can just store as long as we do the two halves in the right order 16717ed9e31SAneesh Kumar K.V * with a barrier in between. This is possible because we take care, 16817ed9e31SAneesh Kumar K.V * in the hash code, to pre-invalidate if the PTE was already hashed, 16917ed9e31SAneesh Kumar K.V * which synchronizes us with any concurrent invalidation. 17017ed9e31SAneesh Kumar K.V * In the percpu case, we also fallback to the simple update preserving 17117ed9e31SAneesh Kumar K.V * the hash bits 17217ed9e31SAneesh Kumar K.V */ 17317ed9e31SAneesh Kumar K.V if (percpu) { 17417ed9e31SAneesh Kumar K.V *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 17517ed9e31SAneesh Kumar K.V | (pte_val(pte) & ~_PAGE_HASHPTE)); 17617ed9e31SAneesh Kumar K.V return; 17717ed9e31SAneesh Kumar K.V } 17817ed9e31SAneesh Kumar K.V #if _PAGE_HASHPTE != 0 17917ed9e31SAneesh Kumar K.V if (pte_val(*ptep) & _PAGE_HASHPTE) 18017ed9e31SAneesh Kumar K.V flush_hash_entry(mm, ptep, addr); 18117ed9e31SAneesh Kumar K.V #endif 18217ed9e31SAneesh Kumar K.V __asm__ __volatile__("\ 18317ed9e31SAneesh Kumar K.V stw%U0%X0 %2,%0\n\ 18417ed9e31SAneesh Kumar K.V eieio\n\ 18517ed9e31SAneesh Kumar K.V stw%U0%X0 %L2,%1" 18617ed9e31SAneesh Kumar K.V : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 18717ed9e31SAneesh Kumar K.V : "r" (pte) : "memory"); 18817ed9e31SAneesh Kumar K.V 18917ed9e31SAneesh Kumar K.V #elif defined(CONFIG_PPC_STD_MMU_32) 19017ed9e31SAneesh Kumar K.V /* Third case is 32-bit hash table in UP mode, we need to preserve 19117ed9e31SAneesh Kumar K.V * the _PAGE_HASHPTE bit since we may not have invalidated the previous 19217ed9e31SAneesh Kumar K.V * translation in the hash yet (done in a subsequent flush_tlb_xxx()) 19317ed9e31SAneesh Kumar K.V * and see we need to keep track that this PTE needs invalidating 19417ed9e31SAneesh Kumar K.V */ 19517ed9e31SAneesh Kumar K.V *ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE) 19617ed9e31SAneesh Kumar K.V | (pte_val(pte) & ~_PAGE_HASHPTE)); 19717ed9e31SAneesh Kumar K.V 19817ed9e31SAneesh Kumar K.V #else 19917ed9e31SAneesh Kumar K.V /* Anything else just stores the PTE normally. That covers all 64-bit 20017ed9e31SAneesh Kumar K.V * cases, and 32-bit non-hash with 32-bit PTEs. 20117ed9e31SAneesh Kumar K.V */ 20217ed9e31SAneesh Kumar K.V *ptep = pte; 20317ed9e31SAneesh Kumar K.V 20417ed9e31SAneesh Kumar K.V #ifdef CONFIG_PPC_BOOK3E_64 20517ed9e31SAneesh Kumar K.V /* 20617ed9e31SAneesh Kumar K.V * With hardware tablewalk, a sync is needed to ensure that 20717ed9e31SAneesh Kumar K.V * subsequent accesses see the PTE we just wrote. Unlike userspace 20817ed9e31SAneesh Kumar K.V * mappings, we can't tolerate spurious faults, so make sure 20917ed9e31SAneesh Kumar K.V * the new PTE will be seen the first time. 21017ed9e31SAneesh Kumar K.V */ 21117ed9e31SAneesh Kumar K.V if (is_kernel_addr(addr)) 21217ed9e31SAneesh Kumar K.V mb(); 21317ed9e31SAneesh Kumar K.V #endif 21417ed9e31SAneesh Kumar K.V #endif 21517ed9e31SAneesh Kumar K.V } 21617ed9e31SAneesh Kumar K.V 21717ed9e31SAneesh Kumar K.V 21817ed9e31SAneesh Kumar K.V #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 21917ed9e31SAneesh Kumar K.V extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 22017ed9e31SAneesh Kumar K.V pte_t *ptep, pte_t entry, int dirty); 22117ed9e31SAneesh Kumar K.V 22217ed9e31SAneesh Kumar K.V /* 22317ed9e31SAneesh Kumar K.V * Macro to mark a page protection value as "uncacheable". 22417ed9e31SAneesh Kumar K.V */ 22517ed9e31SAneesh Kumar K.V 22617ed9e31SAneesh Kumar K.V #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 22717ed9e31SAneesh Kumar K.V _PAGE_WRITETHRU) 22817ed9e31SAneesh Kumar K.V 22917ed9e31SAneesh Kumar K.V #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 23017ed9e31SAneesh Kumar K.V _PAGE_NO_CACHE | _PAGE_GUARDED)) 23117ed9e31SAneesh Kumar K.V 23217ed9e31SAneesh Kumar K.V #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 23317ed9e31SAneesh Kumar K.V _PAGE_NO_CACHE)) 23417ed9e31SAneesh Kumar K.V 23517ed9e31SAneesh Kumar K.V #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 23617ed9e31SAneesh Kumar K.V _PAGE_COHERENT)) 23717ed9e31SAneesh Kumar K.V 23817ed9e31SAneesh Kumar K.V #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 23917ed9e31SAneesh Kumar K.V _PAGE_COHERENT | _PAGE_WRITETHRU)) 24017ed9e31SAneesh Kumar K.V 24117ed9e31SAneesh Kumar K.V #define pgprot_cached_noncoherent(prot) \ 24217ed9e31SAneesh Kumar K.V (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL)) 24317ed9e31SAneesh Kumar K.V 24417ed9e31SAneesh Kumar K.V #define pgprot_writecombine pgprot_noncached_wc 24517ed9e31SAneesh Kumar K.V 24617ed9e31SAneesh Kumar K.V struct file; 24717ed9e31SAneesh Kumar K.V extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 24817ed9e31SAneesh Kumar K.V unsigned long size, pgprot_t vma_prot); 24917ed9e31SAneesh Kumar K.V #define __HAVE_PHYS_MEM_ACCESS_PROT 25017ed9e31SAneesh Kumar K.V 25126a344aeSAneesh Kumar K.V #ifdef CONFIG_HUGETLB_PAGE 25226a344aeSAneesh Kumar K.V static inline int hugepd_ok(hugepd_t hpd) 25326a344aeSAneesh Kumar K.V { 2544b914286SChristophe Leroy #ifdef CONFIG_PPC_8xx 25520717e1fSAneesh Kumar K.V return ((hpd_val(hpd) & 0x4) != 0); 2564b914286SChristophe Leroy #else 25720717e1fSAneesh Kumar K.V /* We clear the top bit to indicate hugepd */ 2583fb66a70SLaurentiu Tudor return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0); 2594b914286SChristophe Leroy #endif 26026a344aeSAneesh Kumar K.V } 26126a344aeSAneesh Kumar K.V 26226a344aeSAneesh Kumar K.V static inline int pmd_huge(pmd_t pmd) 26326a344aeSAneesh Kumar K.V { 26426a344aeSAneesh Kumar K.V return 0; 26526a344aeSAneesh Kumar K.V } 26626a344aeSAneesh Kumar K.V 26726a344aeSAneesh Kumar K.V static inline int pud_huge(pud_t pud) 26826a344aeSAneesh Kumar K.V { 26926a344aeSAneesh Kumar K.V return 0; 27026a344aeSAneesh Kumar K.V } 27126a344aeSAneesh Kumar K.V 27226a344aeSAneesh Kumar K.V static inline int pgd_huge(pgd_t pgd) 27326a344aeSAneesh Kumar K.V { 27426a344aeSAneesh Kumar K.V return 0; 27526a344aeSAneesh Kumar K.V } 27626a344aeSAneesh Kumar K.V #define pgd_huge pgd_huge 27726a344aeSAneesh Kumar K.V 27826a344aeSAneesh Kumar K.V #define is_hugepd(hpd) (hugepd_ok(hpd)) 27926a344aeSAneesh Kumar K.V #endif 28026a344aeSAneesh Kumar K.V 28117ed9e31SAneesh Kumar K.V #endif /* __ASSEMBLY__ */ 28217ed9e31SAneesh Kumar K.V #endif 283