1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 217ed9e31SAneesh Kumar K.V #ifndef _ASM_POWERPC_NOHASH_PGTABLE_H 317ed9e31SAneesh Kumar K.V #define _ASM_POWERPC_NOHASH_PGTABLE_H 417ed9e31SAneesh Kumar K.V 517ed9e31SAneesh Kumar K.V #if defined(CONFIG_PPC64) 617ed9e31SAneesh Kumar K.V #include <asm/nohash/64/pgtable.h> 717ed9e31SAneesh Kumar K.V #else 817ed9e31SAneesh Kumar K.V #include <asm/nohash/32/pgtable.h> 917ed9e31SAneesh Kumar K.V #endif 1017ed9e31SAneesh Kumar K.V 1117ed9e31SAneesh Kumar K.V #ifndef __ASSEMBLY__ 1217ed9e31SAneesh Kumar K.V 1317ed9e31SAneesh Kumar K.V /* Generic accessors to PTE bits */ 1417ed9e31SAneesh Kumar K.V static inline int pte_write(pte_t pte) 1517ed9e31SAneesh Kumar K.V { 1617ed9e31SAneesh Kumar K.V return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; 1717ed9e31SAneesh Kumar K.V } 18ca8afd40SChristophe Leroy static inline int pte_read(pte_t pte) { return 1; } 1917ed9e31SAneesh Kumar K.V static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 2017ed9e31SAneesh Kumar K.V static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; } 2117ed9e31SAneesh Kumar K.V static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; } 22daba7902SChristophe Leroy static inline bool pte_hashpte(pte_t pte) { return false; } 23daba7902SChristophe Leroy static inline bool pte_ci(pte_t pte) { return pte_val(pte) & _PAGE_NO_CACHE; } 24daba7902SChristophe Leroy static inline bool pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 2517ed9e31SAneesh Kumar K.V static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); } 2617ed9e31SAneesh Kumar K.V 2717ed9e31SAneesh Kumar K.V #ifdef CONFIG_NUMA_BALANCING 2817ed9e31SAneesh Kumar K.V /* 2917ed9e31SAneesh Kumar K.V * These work without NUMA balancing but the kernel does not care. See the 3017ed9e31SAneesh Kumar K.V * comment in include/asm-generic/pgtable.h . On powerpc, this will only 3117ed9e31SAneesh Kumar K.V * work for user pages and always return true for kernel pages. 3217ed9e31SAneesh Kumar K.V */ 3317ed9e31SAneesh Kumar K.V static inline int pte_protnone(pte_t pte) 3417ed9e31SAneesh Kumar K.V { 3526973fa5SChristophe Leroy return pte_present(pte) && !pte_user(pte); 3617ed9e31SAneesh Kumar K.V } 3717ed9e31SAneesh Kumar K.V 3817ed9e31SAneesh Kumar K.V static inline int pmd_protnone(pmd_t pmd) 3917ed9e31SAneesh Kumar K.V { 4017ed9e31SAneesh Kumar K.V return pte_protnone(pmd_pte(pmd)); 4117ed9e31SAneesh Kumar K.V } 4217ed9e31SAneesh Kumar K.V #endif /* CONFIG_NUMA_BALANCING */ 4317ed9e31SAneesh Kumar K.V 4417ed9e31SAneesh Kumar K.V static inline int pte_present(pte_t pte) 4517ed9e31SAneesh Kumar K.V { 4617ed9e31SAneesh Kumar K.V return pte_val(pte) & _PAGE_PRESENT; 4717ed9e31SAneesh Kumar K.V } 4817ed9e31SAneesh Kumar K.V 49daba7902SChristophe Leroy static inline bool pte_hw_valid(pte_t pte) 50daba7902SChristophe Leroy { 51daba7902SChristophe Leroy return pte_val(pte) & _PAGE_PRESENT; 52daba7902SChristophe Leroy } 53daba7902SChristophe Leroy 545769beafSAneesh Kumar K.V /* 555769beafSAneesh Kumar K.V * We only find page table entry in the last level 565769beafSAneesh Kumar K.V * Hence no need for other accessors 575769beafSAneesh Kumar K.V */ 585769beafSAneesh Kumar K.V #define pte_access_permitted pte_access_permitted 595769beafSAneesh Kumar K.V static inline bool pte_access_permitted(pte_t pte, bool write) 605769beafSAneesh Kumar K.V { 615769beafSAneesh Kumar K.V /* 625769beafSAneesh Kumar K.V * A read-only access is controlled by _PAGE_USER bit. 635769beafSAneesh Kumar K.V * We have _PAGE_READ set for WRITE and EXECUTE 645769beafSAneesh Kumar K.V */ 65810e9f86SChristophe Leroy if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte)) 66810e9f86SChristophe Leroy return false; 675769beafSAneesh Kumar K.V 68810e9f86SChristophe Leroy if (write && !pte_write(pte)) 695769beafSAneesh Kumar K.V return false; 705769beafSAneesh Kumar K.V 715769beafSAneesh Kumar K.V return true; 725769beafSAneesh Kumar K.V } 735769beafSAneesh Kumar K.V 7417ed9e31SAneesh Kumar K.V /* Conversion functions: convert a page and protection to a page entry, 7517ed9e31SAneesh Kumar K.V * and a page entry and page directory to the page they refer to. 7617ed9e31SAneesh Kumar K.V * 7717ed9e31SAneesh Kumar K.V * Even if PTEs can be unsigned long long, a PFN is always an unsigned 7817ed9e31SAneesh Kumar K.V * long for now. 7917ed9e31SAneesh Kumar K.V */ 8017ed9e31SAneesh Kumar K.V static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) { 8117ed9e31SAneesh Kumar K.V return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) | 8217ed9e31SAneesh Kumar K.V pgprot_val(pgprot)); } 8317ed9e31SAneesh Kumar K.V static inline unsigned long pte_pfn(pte_t pte) { 8417ed9e31SAneesh Kumar K.V return pte_val(pte) >> PTE_RPN_SHIFT; } 8517ed9e31SAneesh Kumar K.V 8617ed9e31SAneesh Kumar K.V /* Generic modifiers for PTE bits */ 87daba7902SChristophe Leroy static inline pte_t pte_exprotect(pte_t pte) 88daba7902SChristophe Leroy { 89daba7902SChristophe Leroy return __pte(pte_val(pte) & ~_PAGE_EXEC); 90daba7902SChristophe Leroy } 91daba7902SChristophe Leroy 9217ed9e31SAneesh Kumar K.V static inline pte_t pte_mkclean(pte_t pte) 9317ed9e31SAneesh Kumar K.V { 9417ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE)); 9517ed9e31SAneesh Kumar K.V } 9617ed9e31SAneesh Kumar K.V 9717ed9e31SAneesh Kumar K.V static inline pte_t pte_mkold(pte_t pte) 9817ed9e31SAneesh Kumar K.V { 9917ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) & ~_PAGE_ACCESSED); 10017ed9e31SAneesh Kumar K.V } 10117ed9e31SAneesh Kumar K.V 102daba7902SChristophe Leroy static inline pte_t pte_mkpte(pte_t pte) 103daba7902SChristophe Leroy { 104daba7902SChristophe Leroy return pte; 105daba7902SChristophe Leroy } 106daba7902SChristophe Leroy 10717ed9e31SAneesh Kumar K.V static inline pte_t pte_mkspecial(pte_t pte) 10817ed9e31SAneesh Kumar K.V { 10917ed9e31SAneesh Kumar K.V return __pte(pte_val(pte) | _PAGE_SPECIAL); 11017ed9e31SAneesh Kumar K.V } 11117ed9e31SAneesh Kumar K.V 11217ed9e31SAneesh Kumar K.V static inline pte_t pte_mkhuge(pte_t pte) 11317ed9e31SAneesh Kumar K.V { 114de0f9387SChristophe Leroy return __pte(pte_val(pte) | _PAGE_HUGE); 11517ed9e31SAneesh Kumar K.V } 11617ed9e31SAneesh Kumar K.V 117daba7902SChristophe Leroy static inline pte_t pte_mkprivileged(pte_t pte) 118daba7902SChristophe Leroy { 119daba7902SChristophe Leroy return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED); 120daba7902SChristophe Leroy } 121daba7902SChristophe Leroy 122daba7902SChristophe Leroy static inline pte_t pte_mkuser(pte_t pte) 123daba7902SChristophe Leroy { 124daba7902SChristophe Leroy return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER); 125daba7902SChristophe Leroy } 126daba7902SChristophe Leroy 12717ed9e31SAneesh Kumar K.V static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 12817ed9e31SAneesh Kumar K.V { 12917ed9e31SAneesh Kumar K.V return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 13017ed9e31SAneesh Kumar K.V } 13117ed9e31SAneesh Kumar K.V 13217ed9e31SAneesh Kumar K.V /* Insert a PTE, top-level function is out of line. It uses an inline 13317ed9e31SAneesh Kumar K.V * low level function in the respective pgtable-* files 13417ed9e31SAneesh Kumar K.V */ 13517ed9e31SAneesh Kumar K.V extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 13617ed9e31SAneesh Kumar K.V pte_t pte); 13717ed9e31SAneesh Kumar K.V 13817ed9e31SAneesh Kumar K.V /* This low level function performs the actual PTE insertion 13917ed9e31SAneesh Kumar K.V * Setting the PTE depends on the MMU type and other factors. It's 14017ed9e31SAneesh Kumar K.V * an horrible mess that I'm not going to try to clean up now but 14117ed9e31SAneesh Kumar K.V * I'm keeping it in one place rather than spread around 14217ed9e31SAneesh Kumar K.V */ 14317ed9e31SAneesh Kumar K.V static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 14417ed9e31SAneesh Kumar K.V pte_t *ptep, pte_t pte, int percpu) 14517ed9e31SAneesh Kumar K.V { 14617ed9e31SAneesh Kumar K.V /* Second case is 32-bit with 64-bit PTE. In this case, we 14717ed9e31SAneesh Kumar K.V * can just store as long as we do the two halves in the right order 14845201c87SChristophe Leroy * with a barrier in between. 14945201c87SChristophe Leroy * In the percpu case, we also fallback to the simple update 15017ed9e31SAneesh Kumar K.V */ 151d5808ffaSChristophe Leroy if (IS_ENABLED(CONFIG_PPC32) && IS_ENABLED(CONFIG_PTE_64BIT) && !percpu) { 15217ed9e31SAneesh Kumar K.V __asm__ __volatile__("\ 15317ed9e31SAneesh Kumar K.V stw%U0%X0 %2,%0\n\ 15417ed9e31SAneesh Kumar K.V eieio\n\ 15517ed9e31SAneesh Kumar K.V stw%U0%X0 %L2,%1" 15617ed9e31SAneesh Kumar K.V : "=m" (*ptep), "=m" (*((unsigned char *)ptep+4)) 15717ed9e31SAneesh Kumar K.V : "r" (pte) : "memory"); 158d5808ffaSChristophe Leroy return; 159d5808ffaSChristophe Leroy } 16017ed9e31SAneesh Kumar K.V /* Anything else just stores the PTE normally. That covers all 64-bit 16117ed9e31SAneesh Kumar K.V * cases, and 32-bit non-hash with 32-bit PTEs. 16217ed9e31SAneesh Kumar K.V */ 16317ed9e31SAneesh Kumar K.V *ptep = pte; 16417ed9e31SAneesh Kumar K.V 16517ed9e31SAneesh Kumar K.V /* 16617ed9e31SAneesh Kumar K.V * With hardware tablewalk, a sync is needed to ensure that 16717ed9e31SAneesh Kumar K.V * subsequent accesses see the PTE we just wrote. Unlike userspace 16817ed9e31SAneesh Kumar K.V * mappings, we can't tolerate spurious faults, so make sure 16917ed9e31SAneesh Kumar K.V * the new PTE will be seen the first time. 17017ed9e31SAneesh Kumar K.V */ 171d5808ffaSChristophe Leroy if (IS_ENABLED(CONFIG_PPC_BOOK3E_64) && is_kernel_addr(addr)) 17217ed9e31SAneesh Kumar K.V mb(); 17317ed9e31SAneesh Kumar K.V } 17417ed9e31SAneesh Kumar K.V 17517ed9e31SAneesh Kumar K.V 17617ed9e31SAneesh Kumar K.V #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 17717ed9e31SAneesh Kumar K.V extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, 17817ed9e31SAneesh Kumar K.V pte_t *ptep, pte_t entry, int dirty); 17917ed9e31SAneesh Kumar K.V 18017ed9e31SAneesh Kumar K.V /* 18117ed9e31SAneesh Kumar K.V * Macro to mark a page protection value as "uncacheable". 18217ed9e31SAneesh Kumar K.V */ 18317ed9e31SAneesh Kumar K.V 18417ed9e31SAneesh Kumar K.V #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \ 18517ed9e31SAneesh Kumar K.V _PAGE_WRITETHRU) 18617ed9e31SAneesh Kumar K.V 18717ed9e31SAneesh Kumar K.V #define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 18817ed9e31SAneesh Kumar K.V _PAGE_NO_CACHE | _PAGE_GUARDED)) 18917ed9e31SAneesh Kumar K.V 19017ed9e31SAneesh Kumar K.V #define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 19117ed9e31SAneesh Kumar K.V _PAGE_NO_CACHE)) 19217ed9e31SAneesh Kumar K.V 19317ed9e31SAneesh Kumar K.V #define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 19417ed9e31SAneesh Kumar K.V _PAGE_COHERENT)) 19517ed9e31SAneesh Kumar K.V 1965f356497SChristophe Leroy #if _PAGE_WRITETHRU != 0 19717ed9e31SAneesh Kumar K.V #define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \ 19817ed9e31SAneesh Kumar K.V _PAGE_COHERENT | _PAGE_WRITETHRU)) 19956f3c141SChristophe Leroy #else 20056f3c141SChristophe Leroy #define pgprot_cached_wthru(prot) pgprot_noncached(prot) 2015f356497SChristophe Leroy #endif 20217ed9e31SAneesh Kumar K.V 20317ed9e31SAneesh Kumar K.V #define pgprot_cached_noncoherent(prot) \ 20417ed9e31SAneesh Kumar K.V (__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL)) 20517ed9e31SAneesh Kumar K.V 20617ed9e31SAneesh Kumar K.V #define pgprot_writecombine pgprot_noncached_wc 20717ed9e31SAneesh Kumar K.V 20817ed9e31SAneesh Kumar K.V struct file; 20917ed9e31SAneesh Kumar K.V extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 21017ed9e31SAneesh Kumar K.V unsigned long size, pgprot_t vma_prot); 21117ed9e31SAneesh Kumar K.V #define __HAVE_PHYS_MEM_ACCESS_PROT 21217ed9e31SAneesh Kumar K.V 21326a344aeSAneesh Kumar K.V #ifdef CONFIG_HUGETLB_PAGE 21426a344aeSAneesh Kumar K.V static inline int hugepd_ok(hugepd_t hpd) 21526a344aeSAneesh Kumar K.V { 2164b914286SChristophe Leroy #ifdef CONFIG_PPC_8xx 21720717e1fSAneesh Kumar K.V return ((hpd_val(hpd) & 0x4) != 0); 2184b914286SChristophe Leroy #else 21920717e1fSAneesh Kumar K.V /* We clear the top bit to indicate hugepd */ 2203fb66a70SLaurentiu Tudor return (hpd_val(hpd) && (hpd_val(hpd) & PD_HUGE) == 0); 2214b914286SChristophe Leroy #endif 22226a344aeSAneesh Kumar K.V } 22326a344aeSAneesh Kumar K.V 22426a344aeSAneesh Kumar K.V static inline int pmd_huge(pmd_t pmd) 22526a344aeSAneesh Kumar K.V { 22626a344aeSAneesh Kumar K.V return 0; 22726a344aeSAneesh Kumar K.V } 22826a344aeSAneesh Kumar K.V 22926a344aeSAneesh Kumar K.V static inline int pud_huge(pud_t pud) 23026a344aeSAneesh Kumar K.V { 23126a344aeSAneesh Kumar K.V return 0; 23226a344aeSAneesh Kumar K.V } 23326a344aeSAneesh Kumar K.V 23426a344aeSAneesh Kumar K.V static inline int pgd_huge(pgd_t pgd) 23526a344aeSAneesh Kumar K.V { 23626a344aeSAneesh Kumar K.V return 0; 23726a344aeSAneesh Kumar K.V } 23826a344aeSAneesh Kumar K.V #define pgd_huge pgd_huge 23926a344aeSAneesh Kumar K.V 24026a344aeSAneesh Kumar K.V #define is_hugepd(hpd) (hugepd_ok(hpd)) 24126a344aeSAneesh Kumar K.V #endif 24226a344aeSAneesh Kumar K.V 24317ed9e31SAneesh Kumar K.V #endif /* __ASSEMBLY__ */ 24417ed9e31SAneesh Kumar K.V #endif 245