1 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_H 2 #define _ASM_POWERPC_NOHASH_64_PGTABLE_H 3 /* 4 * This file contains the functions and defines necessary to modify and use 5 * the ppc64 hashed page table. 6 */ 7 8 #ifdef CONFIG_PPC_64K_PAGES 9 #include <asm/nohash/64/pgtable-64k.h> 10 #else 11 #include <asm/nohash/64/pgtable-4k.h> 12 #endif 13 #include <asm/barrier.h> 14 15 #define FIRST_USER_ADDRESS 0UL 16 17 /* 18 * Size of EA range mapped by our pagetables. 19 */ 20 #define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \ 21 PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT) 22 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE) 23 24 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 25 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1) 26 #else 27 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 28 #endif 29 /* 30 * Define the address range of the kernel non-linear virtual area 31 */ 32 33 #ifdef CONFIG_PPC_BOOK3E 34 #define KERN_VIRT_START ASM_CONST(0x8000000000000000) 35 #else 36 #define KERN_VIRT_START ASM_CONST(0xD000000000000000) 37 #endif 38 #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000) 39 40 /* 41 * The vmalloc space starts at the beginning of that region, and 42 * occupies half of it on hash CPUs and a quarter of it on Book3E 43 * (we keep a quarter for the virtual memmap) 44 */ 45 #define VMALLOC_START KERN_VIRT_START 46 #ifdef CONFIG_PPC_BOOK3E 47 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2) 48 #else 49 #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) 50 #endif 51 #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) 52 53 /* 54 * The second half of the kernel virtual space is used for IO mappings, 55 * it's itself carved into the PIO region (ISA and PHB IO space) and 56 * the ioremap space 57 * 58 * ISA_IO_BASE = KERN_IO_START, 64K reserved area 59 * PHB_IO_BASE = ISA_IO_BASE + 64K to ISA_IO_BASE + 2G, PHB IO spaces 60 * IOREMAP_BASE = ISA_IO_BASE + 2G to VMALLOC_START + PGTABLE_RANGE 61 */ 62 #define KERN_IO_START (KERN_VIRT_START + (KERN_VIRT_SIZE >> 1)) 63 #define FULL_IO_SIZE 0x80000000ul 64 #define ISA_IO_BASE (KERN_IO_START) 65 #define ISA_IO_END (KERN_IO_START + 0x10000ul) 66 #define PHB_IO_BASE (ISA_IO_END) 67 #define PHB_IO_END (KERN_IO_START + FULL_IO_SIZE) 68 #define IOREMAP_BASE (PHB_IO_END) 69 #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) 70 71 72 /* 73 * Region IDs 74 */ 75 #define REGION_SHIFT 60UL 76 #define REGION_MASK (0xfUL << REGION_SHIFT) 77 #define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT) 78 79 #define VMALLOC_REGION_ID (REGION_ID(VMALLOC_START)) 80 #define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET)) 81 #define VMEMMAP_REGION_ID (0xfUL) /* Server only */ 82 #define USER_REGION_ID (0UL) 83 84 /* 85 * Defines the address of the vmemap area, in its own region on 86 * hash table CPUs and after the vmalloc space on Book3E 87 */ 88 #ifdef CONFIG_PPC_BOOK3E 89 #define VMEMMAP_BASE VMALLOC_END 90 #define VMEMMAP_END KERN_IO_START 91 #else 92 #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) 93 #endif 94 #define vmemmap ((struct page *)VMEMMAP_BASE) 95 96 97 /* 98 * Include the PTE bits definitions 99 */ 100 #include <asm/nohash/pte-book3e.h> 101 #include <asm/pte-common.h> 102 103 #ifdef CONFIG_PPC_MM_SLICES 104 #define HAVE_ARCH_UNMAPPED_AREA 105 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 106 #endif /* CONFIG_PPC_MM_SLICES */ 107 108 #ifndef __ASSEMBLY__ 109 /* pte_clear moved to later in this file */ 110 111 #define PMD_BAD_BITS (PTE_TABLE_SIZE-1) 112 #define PUD_BAD_BITS (PMD_TABLE_SIZE-1) 113 114 static inline void pmd_set(pmd_t *pmdp, unsigned long val) 115 { 116 *pmdp = __pmd(val); 117 } 118 119 static inline void pmd_clear(pmd_t *pmdp) 120 { 121 *pmdp = __pmd(0); 122 } 123 124 static inline pte_t pmd_pte(pmd_t pmd) 125 { 126 return __pte(pmd_val(pmd)); 127 } 128 129 #define pmd_none(pmd) (!pmd_val(pmd)) 130 #define pmd_bad(pmd) (!is_kernel_addr(pmd_val(pmd)) \ 131 || (pmd_val(pmd) & PMD_BAD_BITS)) 132 #define pmd_present(pmd) (!pmd_none(pmd)) 133 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & ~PMD_MASKED_BITS) 134 extern struct page *pmd_page(pmd_t pmd); 135 136 static inline void pud_set(pud_t *pudp, unsigned long val) 137 { 138 *pudp = __pud(val); 139 } 140 141 static inline void pud_clear(pud_t *pudp) 142 { 143 *pudp = __pud(0); 144 } 145 146 #define pud_none(pud) (!pud_val(pud)) 147 #define pud_bad(pud) (!is_kernel_addr(pud_val(pud)) \ 148 || (pud_val(pud) & PUD_BAD_BITS)) 149 #define pud_present(pud) (pud_val(pud) != 0) 150 #define pud_page_vaddr(pud) (pud_val(pud) & ~PUD_MASKED_BITS) 151 152 extern struct page *pud_page(pud_t pud); 153 154 static inline pte_t pud_pte(pud_t pud) 155 { 156 return __pte(pud_val(pud)); 157 } 158 159 static inline pud_t pte_pud(pte_t pte) 160 { 161 return __pud(pte_val(pte)); 162 } 163 #define pud_write(pud) pte_write(pud_pte(pud)) 164 #define pgd_write(pgd) pte_write(pgd_pte(pgd)) 165 166 static inline void pgd_set(pgd_t *pgdp, unsigned long val) 167 { 168 *pgdp = __pgd(val); 169 } 170 171 /* 172 * Find an entry in a page-table-directory. We combine the address region 173 * (the high order N bits) and the pgd portion of the address. 174 */ 175 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1)) 176 177 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 178 179 #define pmd_offset(pudp,addr) \ 180 (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) 181 182 #define pte_offset_kernel(dir,addr) \ 183 (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) 184 185 #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) 186 #define pte_unmap(pte) do { } while(0) 187 188 /* to find an entry in a kernel page-table-directory */ 189 /* This now only contains the vmalloc pages */ 190 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 191 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr, 192 pte_t *ptep, unsigned long pte, int huge); 193 194 /* Atomic PTE updates */ 195 static inline unsigned long pte_update(struct mm_struct *mm, 196 unsigned long addr, 197 pte_t *ptep, unsigned long clr, 198 unsigned long set, 199 int huge) 200 { 201 #ifdef PTE_ATOMIC_UPDATES 202 unsigned long old, tmp; 203 204 __asm__ __volatile__( 205 "1: ldarx %0,0,%3 # pte_update\n\ 206 andi. %1,%0,%6\n\ 207 bne- 1b \n\ 208 andc %1,%0,%4 \n\ 209 or %1,%1,%7\n\ 210 stdcx. %1,0,%3 \n\ 211 bne- 1b" 212 : "=&r" (old), "=&r" (tmp), "=m" (*ptep) 213 : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set) 214 : "cc" ); 215 #else 216 unsigned long old = pte_val(*ptep); 217 *ptep = __pte((old & ~clr) | set); 218 #endif 219 /* huge pages use the old page table lock */ 220 if (!huge) 221 assert_pte_locked(mm, addr); 222 223 #ifdef CONFIG_PPC_STD_MMU_64 224 if (old & _PAGE_HASHPTE) 225 hpte_need_flush(mm, addr, ptep, old, huge); 226 #endif 227 228 return old; 229 } 230 231 static inline int __ptep_test_and_clear_young(struct mm_struct *mm, 232 unsigned long addr, pte_t *ptep) 233 { 234 unsigned long old; 235 236 if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) 237 return 0; 238 old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); 239 return (old & _PAGE_ACCESSED) != 0; 240 } 241 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 242 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 243 ({ \ 244 int __r; \ 245 __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \ 246 __r; \ 247 }) 248 249 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 250 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 251 pte_t *ptep) 252 { 253 254 if ((pte_val(*ptep) & _PAGE_RW) == 0) 255 return; 256 257 pte_update(mm, addr, ptep, _PAGE_RW, 0, 0); 258 } 259 260 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 261 unsigned long addr, pte_t *ptep) 262 { 263 if ((pte_val(*ptep) & _PAGE_RW) == 0) 264 return; 265 266 pte_update(mm, addr, ptep, _PAGE_RW, 0, 1); 267 } 268 269 /* 270 * We currently remove entries from the hashtable regardless of whether 271 * the entry was young or dirty. The generic routines only flush if the 272 * entry was young or dirty which is not good enough. 273 * 274 * We should be more intelligent about this but for the moment we override 275 * these functions and force a tlb flush unconditionally 276 */ 277 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH 278 #define ptep_clear_flush_young(__vma, __address, __ptep) \ 279 ({ \ 280 int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \ 281 __ptep); \ 282 __young; \ 283 }) 284 285 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 286 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, 287 unsigned long addr, pte_t *ptep) 288 { 289 unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0); 290 return __pte(old); 291 } 292 293 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, 294 pte_t * ptep) 295 { 296 pte_update(mm, addr, ptep, ~0UL, 0, 0); 297 } 298 299 300 /* Set the dirty and/or accessed bits atomically in a linux PTE, this 301 * function doesn't need to flush the hash entry 302 */ 303 static inline void __ptep_set_access_flags(struct mm_struct *mm, 304 pte_t *ptep, pte_t entry) 305 { 306 unsigned long bits = pte_val(entry) & 307 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 308 309 #ifdef PTE_ATOMIC_UPDATES 310 unsigned long old, tmp; 311 312 __asm__ __volatile__( 313 "1: ldarx %0,0,%4\n\ 314 andi. %1,%0,%6\n\ 315 bne- 1b \n\ 316 or %0,%3,%0\n\ 317 stdcx. %0,0,%4\n\ 318 bne- 1b" 319 :"=&r" (old), "=&r" (tmp), "=m" (*ptep) 320 :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) 321 :"cc"); 322 #else 323 unsigned long old = pte_val(*ptep); 324 *ptep = __pte(old | bits); 325 #endif 326 } 327 328 #define __HAVE_ARCH_PTE_SAME 329 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0) 330 331 #define pte_ERROR(e) \ 332 pr_err("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 333 #define pmd_ERROR(e) \ 334 pr_err("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 335 #define pgd_ERROR(e) \ 336 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 337 338 /* Encode and de-code a swap entry */ 339 #define MAX_SWAPFILES_CHECK() do { \ 340 BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS); \ 341 /* \ 342 * Don't have overlapping bits with _PAGE_HPTEFLAGS \ 343 * We filter HPTEFLAGS on set_pte. \ 344 */ \ 345 BUILD_BUG_ON(_PAGE_HPTEFLAGS & (0x1f << _PAGE_BIT_SWAP_TYPE)); \ 346 } while (0) 347 /* 348 * on pte we don't need handle RADIX_TREE_EXCEPTIONAL_SHIFT; 349 */ 350 #define SWP_TYPE_BITS 5 351 #define __swp_type(x) (((x).val >> _PAGE_BIT_SWAP_TYPE) \ 352 & ((1UL << SWP_TYPE_BITS) - 1)) 353 #define __swp_offset(x) ((x).val >> PTE_RPN_SHIFT) 354 #define __swp_entry(type, offset) ((swp_entry_t) { \ 355 ((type) << _PAGE_BIT_SWAP_TYPE) \ 356 | ((offset) << PTE_RPN_SHIFT) }) 357 358 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) }) 359 #define __swp_entry_to_pte(x) __pte((x).val) 360 361 void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); 362 void pgtable_cache_init(void); 363 extern int map_kernel_page(unsigned long ea, unsigned long pa, 364 unsigned long flags); 365 extern int __meminit vmemmap_create_mapping(unsigned long start, 366 unsigned long page_size, 367 unsigned long phys); 368 extern void vmemmap_remove_mapping(unsigned long start, 369 unsigned long page_size); 370 #endif /* __ASSEMBLY__ */ 371 372 #endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_H */ 373