1 #ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H 2 #define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H 3 /* 4 * Entries per page directory level. The PTE level must use a 64b record 5 * for each page table entry. The PMD and PGD level use a 32b record for 6 * each entry by assuming that each entry is page aligned. 7 */ 8 #define PTE_INDEX_SIZE 9 9 #define PMD_INDEX_SIZE 7 10 #define PUD_INDEX_SIZE 9 11 #define PGD_INDEX_SIZE 9 12 13 #ifndef __ASSEMBLY__ 14 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 15 #define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE) 16 #define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE) 17 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 18 #endif /* __ASSEMBLY__ */ 19 20 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 21 #define PTRS_PER_PMD (1 << PMD_INDEX_SIZE) 22 #define PTRS_PER_PUD (1 << PUD_INDEX_SIZE) 23 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 24 25 /* PMD_SHIFT determines what a second-level page table entry can map */ 26 #define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 27 #define PMD_SIZE (1UL << PMD_SHIFT) 28 #define PMD_MASK (~(PMD_SIZE-1)) 29 30 /* PUD_SHIFT determines what a third-level page table entry can map */ 31 #define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE) 32 #define PUD_SIZE (1UL << PUD_SHIFT) 33 #define PUD_MASK (~(PUD_SIZE-1)) 34 35 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ 36 #define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE) 37 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 38 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 39 40 /* Bits to mask out from a PMD to get to the PTE page */ 41 #define PMD_MASKED_BITS 0 42 /* Bits to mask out from a PUD to get to the PMD page */ 43 #define PUD_MASKED_BITS 0 44 /* Bits to mask out from a PGD to get to the PUD page */ 45 #define PGD_MASKED_BITS 0 46 47 48 /* 49 * 4-level page tables related bits 50 */ 51 52 #define pgd_none(pgd) (!pgd_val(pgd)) 53 #define pgd_bad(pgd) (pgd_val(pgd) == 0) 54 #define pgd_present(pgd) (pgd_val(pgd) != 0) 55 #define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS) 56 57 #ifndef __ASSEMBLY__ 58 59 static inline void pgd_clear(pgd_t *pgdp) 60 { 61 *pgdp = __pgd(0); 62 } 63 64 static inline pte_t pgd_pte(pgd_t pgd) 65 { 66 return __pte(pgd_val(pgd)); 67 } 68 69 static inline pgd_t pte_pgd(pte_t pte) 70 { 71 return __pgd(pte_val(pte)); 72 } 73 extern struct page *pgd_page(pgd_t pgd); 74 75 #endif /* !__ASSEMBLY__ */ 76 77 #define pud_offset(pgdp, addr) \ 78 (((pud_t *) pgd_page_vaddr(*(pgdp))) + \ 79 (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))) 80 81 #define pud_ERROR(e) \ 82 pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e)) 83 84 /* 85 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */ 86 #define remap_4k_pfn(vma, addr, pfn, prot) \ 87 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot)) 88 89 #endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */ 90