1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_NOHASH_32_PTE_40x_H
3 #define _ASM_POWERPC_NOHASH_32_PTE_40x_H
4 #ifdef __KERNEL__
5 
6 /*
7  * At present, all PowerPC 400-class processors share a similar TLB
8  * architecture. The instruction and data sides share a unified,
9  * 64-entry, fully-associative TLB which is maintained totally under
10  * software control. In addition, the instruction side has a
11  * hardware-managed, 4-entry, fully-associative TLB which serves as a
12  * first level to the shared TLB. These two TLBs are known as the UTLB
13  * and ITLB, respectively (see "mmu.h" for definitions).
14  *
15  * There are several potential gotchas here.  The 40x hardware TLBLO
16  * field looks like this:
17  *
18  * 0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
19  * RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
20  *
21  * Where possible we make the Linux PTE bits match up with this
22  *
23  * - bits 20 and 21 must be cleared, because we use 4k pages (40x can
24  *   support down to 1k pages), this is done in the TLBMiss exception
25  *   handler.
26  * - We use only zones 0 (for kernel pages) and 1 (for user pages)
27  *   of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
28  *   miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
29  *   zone.
30  * - PRESENT *must* be in the bottom two bits because swap cache
31  *   entries use the top 30 bits.  Because 40x doesn't support SMP
32  *   anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
33  *   is cleared in the TLB miss handler before the TLB entry is loaded.
34  * - All other bits of the PTE are loaded into TLBLO without
35  *   modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
36  *   software PTE bits.  We actually use bits 21, 24, 25, and
37  *   30 respectively for the software bits: ACCESSED, DIRTY, RW, and
38  *   PRESENT.
39  */
40 
41 #define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */
42 #define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */
43 #define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */
44 #define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */
45 #define	_PAGE_USER	0x010	/* matches one of the zone permission bits */
46 #define	_PAGE_SPECIAL	0x020	/* software: Special page */
47 #define	_PAGE_DIRTY	0x080	/* software: dirty page */
48 #define _PAGE_RW	0x100	/* hardware: WR, anded with dirty in exception */
49 #define _PAGE_EXEC	0x200	/* hardware: EX permission */
50 #define _PAGE_ACCESSED	0x400	/* software: R: page referenced */
51 
52 /* No page size encoding in the linux PTE */
53 #define _PAGE_PSIZE		0
54 
55 /* cache related flags non existing on 40x */
56 #define _PAGE_COHERENT	0
57 
58 #define _PAGE_KERNEL_RO		0
59 #define _PAGE_KERNEL_ROX	_PAGE_EXEC
60 #define _PAGE_KERNEL_RW		(_PAGE_DIRTY | _PAGE_RW)
61 #define _PAGE_KERNEL_RWX	(_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
62 
63 #define _PMD_PRESENT	0x400	/* PMD points to page of PTEs */
64 #define _PMD_PRESENT_MASK	_PMD_PRESENT
65 #define _PMD_BAD	0x802
66 #define _PMD_SIZE_4M	0x0c0
67 #define _PMD_SIZE_16M	0x0e0
68 #define _PMD_USER	0
69 
70 #define _PTE_NONE_MASK	0
71 
72 /* Until my rework is finished, 40x still needs atomic PTE updates */
73 #define PTE_ATOMIC_UPDATES	1
74 
75 #define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)
76 #define _PAGE_BASE	(_PAGE_BASE_NC)
77 
78 /* Permission masks used to generate the __P and __S table */
79 #define PAGE_NONE	__pgprot(_PAGE_BASE)
80 #define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
81 #define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
82 #define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
83 #define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
84 #define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
85 #define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
86 
87 #endif /* __KERNEL__ */
88 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_40x_H */
89