1 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H 2 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H 3 4 #include <asm-generic/pgtable-nopmd.h> 5 6 #ifndef __ASSEMBLY__ 7 #include <linux/sched.h> 8 #include <linux/threads.h> 9 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ 10 11 extern unsigned long ioremap_bot; 12 13 #ifdef CONFIG_44x 14 extern int icache_44x_need_flush; 15 #endif 16 17 #endif /* __ASSEMBLY__ */ 18 19 #define PTE_INDEX_SIZE PTE_SHIFT 20 #define PMD_INDEX_SIZE 0 21 #define PUD_INDEX_SIZE 0 22 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 23 24 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 25 26 #ifndef __ASSEMBLY__ 27 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 28 #define PMD_TABLE_SIZE 0 29 #define PUD_TABLE_SIZE 0 30 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 31 #endif /* __ASSEMBLY__ */ 32 33 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 34 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 35 36 /* 37 * The normal case is that PTEs are 32-bits and we have a 1-page 38 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 39 * 40 * For any >32-bit physical address platform, we can use the following 41 * two level page table layout where the pgdir is 8KB and the MS 13 bits 42 * are an index to the second level table. The combined pgdir/pmd first 43 * level has 2048 entries and the second level has 512 64-bit PTE entries. 44 * -Matt 45 */ 46 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 47 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 48 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 49 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 50 51 /* Bits to mask out from a PGD to get to the PUD page */ 52 #define PGD_MASKED_BITS 0 53 54 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 55 #define FIRST_USER_ADDRESS 0UL 56 57 #define pte_ERROR(e) \ 58 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 59 (unsigned long long)pte_val(e)) 60 #define pgd_ERROR(e) \ 61 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 62 63 /* 64 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 65 * value (for now) on others, from where we can start layout kernel 66 * virtual space that goes below PKMAP and FIXMAP 67 */ 68 #ifdef CONFIG_HIGHMEM 69 #define KVIRT_TOP PKMAP_BASE 70 #else 71 #define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */ 72 #endif 73 74 /* 75 * ioremap_bot starts at that address. Early ioremaps move down from there, 76 * until mem_init() at which point this becomes the top of the vmalloc 77 * and ioremap space 78 */ 79 #ifdef CONFIG_NOT_COHERENT_CACHE 80 #define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK) 81 #else 82 #define IOREMAP_TOP KVIRT_TOP 83 #endif 84 85 /* 86 * Just any arbitrary offset to the start of the vmalloc VM area: the 87 * current 16MB value just means that there will be a 64MB "hole" after the 88 * physical memory until the kernel virtual memory starts. That means that 89 * any out-of-bounds memory accesses will hopefully be caught. 90 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 91 * area for the same reason. ;) 92 * 93 * We no longer map larger than phys RAM with the BATs so we don't have 94 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 95 * about clashes between our early calls to ioremap() that start growing down 96 * from IOREMAP_TOP being run into the VM area allocations (growing upwards 97 * from VMALLOC_START). For this reason we have ioremap_bot to check when 98 * we actually run into our mappings setup in the early boot with the VM 99 * system. This really does become a problem for machines with good amounts 100 * of RAM. -- Cort 101 */ 102 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 103 #ifdef PPC_PIN_SIZE 104 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 105 #else 106 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 107 #endif 108 #define VMALLOC_END ioremap_bot 109 110 /* 111 * Bits in a linux-style PTE. These match the bits in the 112 * (hardware-defined) PowerPC PTE as closely as possible. 113 */ 114 115 #if defined(CONFIG_40x) 116 #include <asm/nohash/32/pte-40x.h> 117 #elif defined(CONFIG_44x) 118 #include <asm/nohash/32/pte-44x.h> 119 #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) 120 #include <asm/nohash/pte-book3e.h> 121 #elif defined(CONFIG_FSL_BOOKE) 122 #include <asm/nohash/32/pte-fsl-booke.h> 123 #elif defined(CONFIG_8xx) 124 #include <asm/nohash/32/pte-8xx.h> 125 #endif 126 127 /* And here we include common definitions */ 128 #include <asm/pte-common.h> 129 130 #ifndef __ASSEMBLY__ 131 132 #define pte_clear(mm, addr, ptep) \ 133 do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0) 134 135 #define pmd_none(pmd) (!pmd_val(pmd)) 136 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 137 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 138 static inline void pmd_clear(pmd_t *pmdp) 139 { 140 *pmdp = __pmd(0); 141 } 142 143 144 145 /* 146 * When flushing the tlb entry for a page, we also need to flush the hash 147 * table entry. flush_hash_pages is assembler (for speed) in hashtable.S. 148 */ 149 extern int flush_hash_pages(unsigned context, unsigned long va, 150 unsigned long pmdval, int count); 151 152 /* Add an HPTE to the hash table */ 153 extern void add_hash_page(unsigned context, unsigned long va, 154 unsigned long pmdval); 155 156 /* Flush an entry from the TLB/hash table */ 157 extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep, 158 unsigned long address); 159 160 /* 161 * PTE updates. This function is called whenever an existing 162 * valid PTE is updated. This does -not- include set_pte_at() 163 * which nowadays only sets a new PTE. 164 * 165 * Depending on the type of MMU, we may need to use atomic updates 166 * and the PTE may be either 32 or 64 bit wide. In the later case, 167 * when using atomic updates, only the low part of the PTE is 168 * accessed atomically. 169 * 170 * In addition, on 44x, we also maintain a global flag indicating 171 * that an executable user mapping was modified, which is needed 172 * to properly flush the virtually tagged instruction cache of 173 * those implementations. 174 */ 175 #ifndef CONFIG_PTE_64BIT 176 static inline unsigned long pte_update(pte_t *p, 177 unsigned long clr, 178 unsigned long set) 179 { 180 #ifdef PTE_ATOMIC_UPDATES 181 unsigned long old, tmp; 182 183 __asm__ __volatile__("\ 184 1: lwarx %0,0,%3\n\ 185 andc %1,%0,%4\n\ 186 or %1,%1,%5\n" 187 PPC405_ERR77(0,%3) 188 " stwcx. %1,0,%3\n\ 189 bne- 1b" 190 : "=&r" (old), "=&r" (tmp), "=m" (*p) 191 : "r" (p), "r" (clr), "r" (set), "m" (*p) 192 : "cc" ); 193 #else /* PTE_ATOMIC_UPDATES */ 194 unsigned long old = pte_val(*p); 195 *p = __pte((old & ~clr) | set); 196 #endif /* !PTE_ATOMIC_UPDATES */ 197 198 #ifdef CONFIG_44x 199 if ((old & _PAGE_USER) && (old & _PAGE_EXEC)) 200 icache_44x_need_flush = 1; 201 #endif 202 return old; 203 } 204 #else /* CONFIG_PTE_64BIT */ 205 static inline unsigned long long pte_update(pte_t *p, 206 unsigned long clr, 207 unsigned long set) 208 { 209 #ifdef PTE_ATOMIC_UPDATES 210 unsigned long long old; 211 unsigned long tmp; 212 213 __asm__ __volatile__("\ 214 1: lwarx %L0,0,%4\n\ 215 lwzx %0,0,%3\n\ 216 andc %1,%L0,%5\n\ 217 or %1,%1,%6\n" 218 PPC405_ERR77(0,%3) 219 " stwcx. %1,0,%4\n\ 220 bne- 1b" 221 : "=&r" (old), "=&r" (tmp), "=m" (*p) 222 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) 223 : "cc" ); 224 #else /* PTE_ATOMIC_UPDATES */ 225 unsigned long long old = pte_val(*p); 226 *p = __pte((old & ~(unsigned long long)clr) | set); 227 #endif /* !PTE_ATOMIC_UPDATES */ 228 229 #ifdef CONFIG_44x 230 if ((old & _PAGE_USER) && (old & _PAGE_EXEC)) 231 icache_44x_need_flush = 1; 232 #endif 233 return old; 234 } 235 #endif /* CONFIG_PTE_64BIT */ 236 237 /* 238 * 2.6 calls this without flushing the TLB entry; this is wrong 239 * for our hash-based implementation, we fix that up here. 240 */ 241 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 242 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) 243 { 244 unsigned long old; 245 old = pte_update(ptep, _PAGE_ACCESSED, 0); 246 #if _PAGE_HASHPTE != 0 247 if (old & _PAGE_HASHPTE) { 248 unsigned long ptephys = __pa(ptep) & PAGE_MASK; 249 flush_hash_pages(context, addr, ptephys, 1); 250 } 251 #endif 252 return (old & _PAGE_ACCESSED) != 0; 253 } 254 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 255 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) 256 257 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 258 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 259 pte_t *ptep) 260 { 261 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0)); 262 } 263 264 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 265 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 266 pte_t *ptep) 267 { 268 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO); 269 } 270 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 271 unsigned long addr, pte_t *ptep) 272 { 273 ptep_set_wrprotect(mm, addr, ptep); 274 } 275 276 277 static inline void __ptep_set_access_flags(struct mm_struct *mm, 278 pte_t *ptep, pte_t entry, 279 unsigned long address) 280 { 281 unsigned long set = pte_val(entry) & 282 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 283 unsigned long clr = ~pte_val(entry) & _PAGE_RO; 284 285 pte_update(ptep, clr, set); 286 } 287 288 #define __HAVE_ARCH_PTE_SAME 289 #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) 290 291 /* 292 * Note that on Book E processors, the pmd contains the kernel virtual 293 * (lowmem) address of the pte page. The physical address is less useful 294 * because everything runs with translation enabled (even the TLB miss 295 * handler). On everything else the pmd contains the physical address 296 * of the pte page. -- paulus 297 */ 298 #ifndef CONFIG_BOOKE 299 #define pmd_page_vaddr(pmd) \ 300 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) 301 #define pmd_page(pmd) \ 302 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 303 #else 304 #define pmd_page_vaddr(pmd) \ 305 ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 306 #define pmd_page(pmd) \ 307 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 308 #endif 309 310 /* to find an entry in a kernel page-table-directory */ 311 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 312 313 /* to find an entry in a page-table-directory */ 314 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 315 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 316 317 /* Find an entry in the third-level page table.. */ 318 #define pte_index(address) \ 319 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 320 #define pte_offset_kernel(dir, addr) \ 321 (pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \ 322 pte_index(addr)) 323 #define pte_offset_map(dir, addr) \ 324 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) 325 #define pte_unmap(pte) kunmap_atomic(pte) 326 327 /* 328 * Encode and decode a swap entry. 329 * Note that the bits we use in a PTE for representing a swap entry 330 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used). 331 * -- paulus 332 */ 333 #define __swp_type(entry) ((entry).val & 0x1f) 334 #define __swp_offset(entry) ((entry).val >> 5) 335 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 336 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 337 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 338 339 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep, 340 pmd_t **pmdp); 341 342 #endif /* !__ASSEMBLY__ */ 343 344 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */ 345