1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H 3 #define _ASM_POWERPC_NOHASH_32_PGTABLE_H 4 5 #define __ARCH_USE_5LEVEL_HACK 6 #include <asm-generic/pgtable-nopmd.h> 7 8 #ifndef __ASSEMBLY__ 9 #include <linux/sched.h> 10 #include <linux/threads.h> 11 #include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */ 12 13 extern unsigned long ioremap_bot; 14 15 #ifdef CONFIG_44x 16 extern int icache_44x_need_flush; 17 #endif 18 19 #endif /* __ASSEMBLY__ */ 20 21 #define PTE_INDEX_SIZE PTE_SHIFT 22 #define PMD_INDEX_SIZE 0 23 #define PUD_INDEX_SIZE 0 24 #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT) 25 26 #define PMD_CACHE_INDEX PMD_INDEX_SIZE 27 #define PUD_CACHE_INDEX PUD_INDEX_SIZE 28 29 #ifndef __ASSEMBLY__ 30 #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE) 31 #define PMD_TABLE_SIZE 0 32 #define PUD_TABLE_SIZE 0 33 #define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE) 34 #endif /* __ASSEMBLY__ */ 35 36 #define PTRS_PER_PTE (1 << PTE_INDEX_SIZE) 37 #define PTRS_PER_PGD (1 << PGD_INDEX_SIZE) 38 39 /* 40 * The normal case is that PTEs are 32-bits and we have a 1-page 41 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus 42 * 43 * For any >32-bit physical address platform, we can use the following 44 * two level page table layout where the pgdir is 8KB and the MS 13 bits 45 * are an index to the second level table. The combined pgdir/pmd first 46 * level has 2048 entries and the second level has 512 64-bit PTE entries. 47 * -Matt 48 */ 49 /* PGDIR_SHIFT determines what a top-level page table entry can map */ 50 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE) 51 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 52 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 53 54 /* Bits to mask out from a PGD to get to the PUD page */ 55 #define PGD_MASKED_BITS 0 56 57 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 58 #define FIRST_USER_ADDRESS 0UL 59 60 #define pte_ERROR(e) \ 61 pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \ 62 (unsigned long long)pte_val(e)) 63 #define pgd_ERROR(e) \ 64 pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 65 66 /* 67 * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary 68 * value (for now) on others, from where we can start layout kernel 69 * virtual space that goes below PKMAP and FIXMAP 70 */ 71 #ifdef CONFIG_HIGHMEM 72 #define KVIRT_TOP PKMAP_BASE 73 #else 74 #define KVIRT_TOP (0xfe000000UL) /* for now, could be FIXMAP_BASE ? */ 75 #endif 76 77 /* 78 * ioremap_bot starts at that address. Early ioremaps move down from there, 79 * until mem_init() at which point this becomes the top of the vmalloc 80 * and ioremap space 81 */ 82 #ifdef CONFIG_NOT_COHERENT_CACHE 83 #define IOREMAP_TOP ((KVIRT_TOP - CONFIG_CONSISTENT_SIZE) & PAGE_MASK) 84 #else 85 #define IOREMAP_TOP KVIRT_TOP 86 #endif 87 88 /* 89 * Just any arbitrary offset to the start of the vmalloc VM area: the 90 * current 16MB value just means that there will be a 64MB "hole" after the 91 * physical memory until the kernel virtual memory starts. That means that 92 * any out-of-bounds memory accesses will hopefully be caught. 93 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 94 * area for the same reason. ;) 95 * 96 * We no longer map larger than phys RAM with the BATs so we don't have 97 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry 98 * about clashes between our early calls to ioremap() that start growing down 99 * from IOREMAP_TOP being run into the VM area allocations (growing upwards 100 * from VMALLOC_START). For this reason we have ioremap_bot to check when 101 * we actually run into our mappings setup in the early boot with the VM 102 * system. This really does become a problem for machines with good amounts 103 * of RAM. -- Cort 104 */ 105 #define VMALLOC_OFFSET (0x1000000) /* 16M */ 106 #ifdef PPC_PIN_SIZE 107 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 108 #else 109 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) 110 #endif 111 #define VMALLOC_END ioremap_bot 112 113 /* 114 * Bits in a linux-style PTE. These match the bits in the 115 * (hardware-defined) PowerPC PTE as closely as possible. 116 */ 117 118 #if defined(CONFIG_40x) 119 #include <asm/nohash/32/pte-40x.h> 120 #elif defined(CONFIG_44x) 121 #include <asm/nohash/32/pte-44x.h> 122 #elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) 123 #include <asm/nohash/pte-book3e.h> 124 #elif defined(CONFIG_FSL_BOOKE) 125 #include <asm/nohash/32/pte-fsl-booke.h> 126 #elif defined(CONFIG_PPC_8xx) 127 #include <asm/nohash/32/pte-8xx.h> 128 #endif 129 130 /* And here we include common definitions */ 131 #include <asm/pte-common.h> 132 133 #ifndef __ASSEMBLY__ 134 135 #define pte_clear(mm, addr, ptep) \ 136 do { pte_update(ptep, ~0, 0); } while (0) 137 138 #define pmd_none(pmd) (!pmd_val(pmd)) 139 #define pmd_bad(pmd) (pmd_val(pmd) & _PMD_BAD) 140 #define pmd_present(pmd) (pmd_val(pmd) & _PMD_PRESENT_MASK) 141 static inline void pmd_clear(pmd_t *pmdp) 142 { 143 *pmdp = __pmd(0); 144 } 145 146 147 148 /* 149 * PTE updates. This function is called whenever an existing 150 * valid PTE is updated. This does -not- include set_pte_at() 151 * which nowadays only sets a new PTE. 152 * 153 * Depending on the type of MMU, we may need to use atomic updates 154 * and the PTE may be either 32 or 64 bit wide. In the later case, 155 * when using atomic updates, only the low part of the PTE is 156 * accessed atomically. 157 * 158 * In addition, on 44x, we also maintain a global flag indicating 159 * that an executable user mapping was modified, which is needed 160 * to properly flush the virtually tagged instruction cache of 161 * those implementations. 162 */ 163 #ifndef CONFIG_PTE_64BIT 164 static inline unsigned long pte_update(pte_t *p, 165 unsigned long clr, 166 unsigned long set) 167 { 168 #ifdef PTE_ATOMIC_UPDATES 169 unsigned long old, tmp; 170 171 __asm__ __volatile__("\ 172 1: lwarx %0,0,%3\n\ 173 andc %1,%0,%4\n\ 174 or %1,%1,%5\n" 175 PPC405_ERR77(0,%3) 176 " stwcx. %1,0,%3\n\ 177 bne- 1b" 178 : "=&r" (old), "=&r" (tmp), "=m" (*p) 179 : "r" (p), "r" (clr), "r" (set), "m" (*p) 180 : "cc" ); 181 #else /* PTE_ATOMIC_UPDATES */ 182 unsigned long old = pte_val(*p); 183 *p = __pte((old & ~clr) | set); 184 #endif /* !PTE_ATOMIC_UPDATES */ 185 186 #ifdef CONFIG_44x 187 if ((old & _PAGE_USER) && (old & _PAGE_EXEC)) 188 icache_44x_need_flush = 1; 189 #endif 190 return old; 191 } 192 #else /* CONFIG_PTE_64BIT */ 193 static inline unsigned long long pte_update(pte_t *p, 194 unsigned long clr, 195 unsigned long set) 196 { 197 #ifdef PTE_ATOMIC_UPDATES 198 unsigned long long old; 199 unsigned long tmp; 200 201 __asm__ __volatile__("\ 202 1: lwarx %L0,0,%4\n\ 203 lwzx %0,0,%3\n\ 204 andc %1,%L0,%5\n\ 205 or %1,%1,%6\n" 206 PPC405_ERR77(0,%3) 207 " stwcx. %1,0,%4\n\ 208 bne- 1b" 209 : "=&r" (old), "=&r" (tmp), "=m" (*p) 210 : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) 211 : "cc" ); 212 #else /* PTE_ATOMIC_UPDATES */ 213 unsigned long long old = pte_val(*p); 214 *p = __pte((old & ~(unsigned long long)clr) | set); 215 #endif /* !PTE_ATOMIC_UPDATES */ 216 217 #ifdef CONFIG_44x 218 if ((old & _PAGE_USER) && (old & _PAGE_EXEC)) 219 icache_44x_need_flush = 1; 220 #endif 221 return old; 222 } 223 #endif /* CONFIG_PTE_64BIT */ 224 225 /* 226 * 2.6 calls this without flushing the TLB entry; this is wrong 227 * for our hash-based implementation, we fix that up here. 228 */ 229 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 230 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep) 231 { 232 unsigned long old; 233 old = pte_update(ptep, _PAGE_ACCESSED, 0); 234 return (old & _PAGE_ACCESSED) != 0; 235 } 236 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \ 237 __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep) 238 239 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 240 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 241 pte_t *ptep) 242 { 243 return __pte(pte_update(ptep, ~0, 0)); 244 } 245 246 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 247 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, 248 pte_t *ptep) 249 { 250 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), _PAGE_RO); 251 } 252 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm, 253 unsigned long addr, pte_t *ptep) 254 { 255 ptep_set_wrprotect(mm, addr, ptep); 256 } 257 258 259 static inline void __ptep_set_access_flags(struct vm_area_struct *vma, 260 pte_t *ptep, pte_t entry, 261 unsigned long address, 262 int psize) 263 { 264 unsigned long set = pte_val(entry) & 265 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); 266 unsigned long clr = ~pte_val(entry) & (_PAGE_RO | _PAGE_NA); 267 268 pte_update(ptep, clr, set); 269 270 flush_tlb_page(vma, address); 271 } 272 273 static inline int pte_young(pte_t pte) 274 { 275 return pte_val(pte) & _PAGE_ACCESSED; 276 } 277 278 #define __HAVE_ARCH_PTE_SAME 279 #define pte_same(A,B) ((pte_val(A) ^ pte_val(B)) == 0) 280 281 /* 282 * Note that on Book E processors, the pmd contains the kernel virtual 283 * (lowmem) address of the pte page. The physical address is less useful 284 * because everything runs with translation enabled (even the TLB miss 285 * handler). On everything else the pmd contains the physical address 286 * of the pte page. -- paulus 287 */ 288 #ifndef CONFIG_BOOKE 289 #define pmd_page_vaddr(pmd) \ 290 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) 291 #define pmd_page(pmd) \ 292 pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT) 293 #else 294 #define pmd_page_vaddr(pmd) \ 295 ((unsigned long) (pmd_val(pmd) & PAGE_MASK)) 296 #define pmd_page(pmd) \ 297 pfn_to_page((__pa(pmd_val(pmd)) >> PAGE_SHIFT)) 298 #endif 299 300 /* to find an entry in a kernel page-table-directory */ 301 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 302 303 /* to find an entry in a page-table-directory */ 304 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 305 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) 306 307 /* Find an entry in the third-level page table.. */ 308 #define pte_index(address) \ 309 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 310 #define pte_offset_kernel(dir, addr) \ 311 (pmd_bad(*(dir)) ? NULL : (pte_t *)pmd_page_vaddr(*(dir)) + \ 312 pte_index(addr)) 313 #define pte_offset_map(dir, addr) \ 314 ((pte_t *) kmap_atomic(pmd_page(*(dir))) + pte_index(addr)) 315 #define pte_unmap(pte) kunmap_atomic(pte) 316 317 /* 318 * Encode and decode a swap entry. 319 * Note that the bits we use in a PTE for representing a swap entry 320 * must not include the _PAGE_PRESENT bit. 321 * -- paulus 322 */ 323 #define __swp_type(entry) ((entry).val & 0x1f) 324 #define __swp_offset(entry) ((entry).val >> 5) 325 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 5) }) 326 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 3 }) 327 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 3 }) 328 329 int map_kernel_page(unsigned long va, phys_addr_t pa, int flags); 330 331 #endif /* !__ASSEMBLY__ */ 332 333 #endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */ 334