1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_MMU_8XX_H_ 3 #define _ASM_POWERPC_MMU_8XX_H_ 4 /* 5 * PPC8xx support 6 */ 7 8 /* Control/status registers for the MPC8xx. 9 * A write operation to these registers causes serialized access. 10 * During software tablewalk, the registers used perform mask/shift-add 11 * operations when written/read. A TLB entry is created when the Mx_RPN 12 * is written, and the contents of several registers are used to 13 * create the entry. 14 */ 15 #define SPRN_MI_CTR 784 /* Instruction TLB control register */ 16 #define MI_GPM 0x80000000 /* Set domain manager mode */ 17 #define MI_PPM 0x40000000 /* Set subpage protection */ 18 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 19 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 20 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 21 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ 22 #define MI_RESETVAL 0x00000000 /* Value of register at reset */ 23 24 /* These are the Ks and Kp from the PowerPC books. For proper operation, 25 * Ks = 0, Kp = 1. 26 */ 27 #define SPRN_MI_AP 786 28 #define MI_Ks 0x80000000 /* Should not be set */ 29 #define MI_Kp 0x40000000 /* Should always be set */ 30 31 /* 32 * All pages' PP data bits are set to either 001 or 011 by copying _PAGE_EXEC 33 * into bit 21 in the ITLBmiss handler (bit 21 is the middle bit), which means 34 * respectively NA for All or X for Supervisor and no access for User. 35 * Then we use the APG to say whether accesses are according to Page rules or 36 * "all Supervisor" rules (Access to all) 37 * Therefore, we define 2 APG groups. lsb is _PMD_USER 38 * 0 => No user => 01 (all accesses performed according to page definition) 39 * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 40 * We define all 16 groups so that all other bits of APG can take any value 41 */ 42 #define MI_APG_INIT 0x44444444 43 44 /* The effective page number register. When read, contains the information 45 * about the last instruction TLB miss. When MI_RPN is written, bits in 46 * this register are used to create the TLB entry. 47 */ 48 #define SPRN_MI_EPN 787 49 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ 50 #define MI_EVALID 0x00000200 /* Entry is valid */ 51 #define MI_ASIDMASK 0x0000000f /* ASID match value */ 52 /* Reset value is undefined */ 53 54 /* A "level 1" or "segment" or whatever you want to call it register. 55 * For the instruction TLB, it contains bits that get loaded into the 56 * TLB entry when the MI_RPN is written. 57 */ 58 #define SPRN_MI_TWC 789 59 #define MI_APG 0x000001e0 /* Access protection group (0) */ 60 #define MI_GUARDED 0x00000010 /* Guarded storage */ 61 #define MI_PSMASK 0x0000000c /* Mask of page size bits */ 62 #define MI_PS8MEG 0x0000000c /* 8M page size */ 63 #define MI_PS512K 0x00000004 /* 512K page size */ 64 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ 65 #define MI_SVALID 0x00000001 /* Segment entry is valid */ 66 /* Reset value is undefined */ 67 68 /* Real page number. Defined by the pte. Writing this register 69 * causes a TLB entry to be created for the instruction TLB, using 70 * additional information from the MI_EPN, and MI_TWC registers. 71 */ 72 #define SPRN_MI_RPN 790 73 #define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ 74 75 /* Define an RPN value for mapping kernel memory to large virtual 76 * pages for boot initialization. This has real page number of 0, 77 * large page size, shared page, cache enabled, and valid. 78 * Also mark all subpages valid and write access. 79 */ 80 #define MI_BOOTINIT 0x000001fd 81 82 #define SPRN_MD_CTR 792 /* Data TLB control register */ 83 #define MD_GPM 0x80000000 /* Set domain manager mode */ 84 #define MD_PPM 0x40000000 /* Set subpage protection */ 85 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 86 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ 87 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 88 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ 89 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 90 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ 91 #define MD_RESETVAL 0x04000000 /* Value of register at reset */ 92 93 #define SPRN_M_CASID 793 /* Address space ID (context) to match */ 94 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ 95 96 97 /* These are the Ks and Kp from the PowerPC books. For proper operation, 98 * Ks = 0, Kp = 1. 99 */ 100 #define SPRN_MD_AP 794 101 #define MD_Ks 0x80000000 /* Should not be set */ 102 #define MD_Kp 0x40000000 /* Should always be set */ 103 104 /* 105 * All pages' PP data bits are set to either 000 or 011 or 001, which means 106 * respectively RW for Supervisor and no access for User, or RO for 107 * Supervisor and no access for user and NA for ALL. 108 * Then we use the APG to say whether accesses are according to Page rules or 109 * "all Supervisor" rules (Access to all) 110 * Therefore, we define 2 APG groups. lsb is _PMD_USER 111 * 0 => No user => 01 (all accesses performed according to page definition) 112 * 1 => User => 00 (all accesses performed as supervisor iaw page definition) 113 * We define all 16 groups so that all other bits of APG can take any value 114 */ 115 #define MD_APG_INIT 0x44444444 116 117 /* The effective page number register. When read, contains the information 118 * about the last instruction TLB miss. When MD_RPN is written, bits in 119 * this register are used to create the TLB entry. 120 */ 121 #define SPRN_MD_EPN 795 122 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ 123 #define MD_EVALID 0x00000200 /* Entry is valid */ 124 #define MD_ASIDMASK 0x0000000f /* ASID match value */ 125 /* Reset value is undefined */ 126 127 /* The pointer to the base address of the first level page table. 128 * During a software tablewalk, reading this register provides the address 129 * of the entry associated with MD_EPN. 130 */ 131 #define SPRN_M_TWB 796 132 #define M_L1TB 0xfffff000 /* Level 1 table base address */ 133 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ 134 /* Reset value is undefined */ 135 136 /* A "level 1" or "segment" or whatever you want to call it register. 137 * For the data TLB, it contains bits that get loaded into the TLB entry 138 * when the MD_RPN is written. It is also provides the hardware assist 139 * for finding the PTE address during software tablewalk. 140 */ 141 #define SPRN_MD_TWC 797 142 #define MD_L2TB 0xfffff000 /* Level 2 table base address */ 143 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ 144 #define MD_APG 0x000001e0 /* Access protection group (0) */ 145 #define MD_GUARDED 0x00000010 /* Guarded storage */ 146 #define MD_PSMASK 0x0000000c /* Mask of page size bits */ 147 #define MD_PS8MEG 0x0000000c /* 8M page size */ 148 #define MD_PS512K 0x00000004 /* 512K page size */ 149 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ 150 #define MD_WT 0x00000002 /* Use writethrough page attribute */ 151 #define MD_SVALID 0x00000001 /* Segment entry is valid */ 152 /* Reset value is undefined */ 153 154 155 /* Real page number. Defined by the pte. Writing this register 156 * causes a TLB entry to be created for the data TLB, using 157 * additional information from the MD_EPN, and MD_TWC registers. 158 */ 159 #define SPRN_MD_RPN 798 160 #define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */ 161 162 /* This is a temporary storage register that could be used to save 163 * a processor working register during a tablewalk. 164 */ 165 #define SPRN_M_TW 799 166 167 #ifdef CONFIG_PPC_MM_SLICES 168 #include <asm/nohash/32/slice.h> 169 #define SLICE_ARRAY_SIZE (1 << (32 - SLICE_LOW_SHIFT - 1)) 170 #endif 171 172 #ifndef __ASSEMBLY__ 173 struct slice_mask { 174 u64 low_slices; 175 DECLARE_BITMAP(high_slices, 0); 176 }; 177 178 typedef struct { 179 unsigned int id; 180 unsigned int active; 181 unsigned long vdso_base; 182 #ifdef CONFIG_PPC_MM_SLICES 183 u16 user_psize; /* page size index */ 184 unsigned char low_slices_psize[SLICE_ARRAY_SIZE]; 185 unsigned char high_slices_psize[0]; 186 unsigned long slb_addr_limit; 187 struct slice_mask mask_base_psize; /* 4k or 16k */ 188 # ifdef CONFIG_HUGETLB_PAGE 189 struct slice_mask mask_512k; 190 struct slice_mask mask_8m; 191 # endif 192 #endif 193 void *pte_frag; 194 } mm_context_t; 195 196 #define PHYS_IMMR_BASE (mfspr(SPRN_IMMR) & 0xfff80000) 197 #define VIRT_IMMR_BASE (__fix_to_virt(FIX_IMMR_BASE)) 198 199 /* Page size definitions, common between 32 and 64-bit 200 * 201 * shift : is the "PAGE_SHIFT" value for that page size 202 * penc : is the pte encoding mask 203 * 204 */ 205 struct mmu_psize_def { 206 unsigned int shift; /* number of bits */ 207 unsigned int enc; /* PTE encoding */ 208 unsigned int ind; /* Corresponding indirect page size shift */ 209 unsigned int flags; 210 #define MMU_PAGE_SIZE_DIRECT 0x1 /* Supported as a direct size */ 211 #define MMU_PAGE_SIZE_INDIRECT 0x2 /* Supported as an indirect size */ 212 }; 213 214 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 215 216 static inline int shift_to_mmu_psize(unsigned int shift) 217 { 218 int psize; 219 220 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) 221 if (mmu_psize_defs[psize].shift == shift) 222 return psize; 223 return -1; 224 } 225 226 static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 227 { 228 if (mmu_psize_defs[mmu_psize].shift) 229 return mmu_psize_defs[mmu_psize].shift; 230 BUG(); 231 } 232 233 /* patch sites */ 234 extern s32 patch__itlbmiss_linmem_top; 235 extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp; 236 extern s32 patch__fixupdar_linmem_top; 237 238 extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2; 239 extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3; 240 extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf; 241 242 #endif /* !__ASSEMBLY__ */ 243 244 #if defined(CONFIG_PPC_4K_PAGES) 245 #define mmu_virtual_psize MMU_PAGE_4K 246 #elif defined(CONFIG_PPC_16K_PAGES) 247 #define mmu_virtual_psize MMU_PAGE_16K 248 #define PTE_FRAG_NR 4 249 #define PTE_FRAG_SIZE_SHIFT 12 250 #define PTE_FRAG_SIZE (1UL << 12) 251 #else 252 #error "Unsupported PAGE_SIZE" 253 #endif 254 255 #define mmu_linear_psize MMU_PAGE_8M 256 257 #endif /* _ASM_POWERPC_MMU_8XX_H_ */ 258