1994da93dSChristophe Leroy /* SPDX-License-Identifier: GPL-2.0 */ 2994da93dSChristophe Leroy #ifndef _ASM_POWERPC_MMU_44X_H_ 3994da93dSChristophe Leroy #define _ASM_POWERPC_MMU_44X_H_ 4994da93dSChristophe Leroy /* 5994da93dSChristophe Leroy * PPC440 support 6994da93dSChristophe Leroy */ 7994da93dSChristophe Leroy 8994da93dSChristophe Leroy #include <asm/asm-const.h> 9994da93dSChristophe Leroy 10994da93dSChristophe Leroy #define PPC44x_MMUCR_TID 0x000000ff 11994da93dSChristophe Leroy #define PPC44x_MMUCR_STS 0x00010000 12994da93dSChristophe Leroy 13994da93dSChristophe Leroy #define PPC44x_TLB_PAGEID 0 14994da93dSChristophe Leroy #define PPC44x_TLB_XLAT 1 15994da93dSChristophe Leroy #define PPC44x_TLB_ATTRIB 2 16994da93dSChristophe Leroy 17994da93dSChristophe Leroy /* Page identification fields */ 18994da93dSChristophe Leroy #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ 19994da93dSChristophe Leroy #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ 20994da93dSChristophe Leroy #define PPC44x_TLB_TS 0x00000100 /* Translation address space */ 21994da93dSChristophe Leroy #define PPC44x_TLB_1K 0x00000000 /* Page sizes */ 22994da93dSChristophe Leroy #define PPC44x_TLB_4K 0x00000010 23994da93dSChristophe Leroy #define PPC44x_TLB_16K 0x00000020 24994da93dSChristophe Leroy #define PPC44x_TLB_64K 0x00000030 25994da93dSChristophe Leroy #define PPC44x_TLB_256K 0x00000040 26994da93dSChristophe Leroy #define PPC44x_TLB_1M 0x00000050 27994da93dSChristophe Leroy #define PPC44x_TLB_16M 0x00000070 28994da93dSChristophe Leroy #define PPC44x_TLB_256M 0x00000090 29994da93dSChristophe Leroy 30994da93dSChristophe Leroy /* Translation fields */ 31994da93dSChristophe Leroy #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ 32994da93dSChristophe Leroy #define PPC44x_TLB_ERPN_MASK 0x0000000f 33994da93dSChristophe Leroy 34994da93dSChristophe Leroy /* Storage attribute and access control fields */ 35994da93dSChristophe Leroy #define PPC44x_TLB_ATTR_MASK 0x0000ff80 36994da93dSChristophe Leroy #define PPC44x_TLB_U0 0x00008000 /* User 0 */ 37994da93dSChristophe Leroy #define PPC44x_TLB_U1 0x00004000 /* User 1 */ 38994da93dSChristophe Leroy #define PPC44x_TLB_U2 0x00002000 /* User 2 */ 39994da93dSChristophe Leroy #define PPC44x_TLB_U3 0x00001000 /* User 3 */ 40994da93dSChristophe Leroy #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ 41994da93dSChristophe Leroy #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ 42994da93dSChristophe Leroy #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ 43994da93dSChristophe Leroy #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ 44994da93dSChristophe Leroy #define PPC44x_TLB_E 0x00000080 /* Memory is little endian */ 45994da93dSChristophe Leroy 46994da93dSChristophe Leroy #define PPC44x_TLB_PERM_MASK 0x0000003f 47994da93dSChristophe Leroy #define PPC44x_TLB_UX 0x00000020 /* User execution */ 48994da93dSChristophe Leroy #define PPC44x_TLB_UW 0x00000010 /* User write */ 49994da93dSChristophe Leroy #define PPC44x_TLB_UR 0x00000008 /* User read */ 50994da93dSChristophe Leroy #define PPC44x_TLB_SX 0x00000004 /* Super execution */ 51994da93dSChristophe Leroy #define PPC44x_TLB_SW 0x00000002 /* Super write */ 52994da93dSChristophe Leroy #define PPC44x_TLB_SR 0x00000001 /* Super read */ 53994da93dSChristophe Leroy 54994da93dSChristophe Leroy /* Number of TLB entries */ 55994da93dSChristophe Leroy #define PPC44x_TLB_SIZE 64 56994da93dSChristophe Leroy 57994da93dSChristophe Leroy /* 47x bits */ 58994da93dSChristophe Leroy #define PPC47x_MMUCR_TID 0x0000ffff 59994da93dSChristophe Leroy #define PPC47x_MMUCR_STS 0x00010000 60994da93dSChristophe Leroy 61994da93dSChristophe Leroy /* Page identification fields */ 62994da93dSChristophe Leroy #define PPC47x_TLB0_EPN_MASK 0xfffff000 /* Effective Page Number */ 63994da93dSChristophe Leroy #define PPC47x_TLB0_VALID 0x00000800 /* Valid flag */ 64994da93dSChristophe Leroy #define PPC47x_TLB0_TS 0x00000400 /* Translation address space */ 65994da93dSChristophe Leroy #define PPC47x_TLB0_4K 0x00000000 66994da93dSChristophe Leroy #define PPC47x_TLB0_16K 0x00000010 67994da93dSChristophe Leroy #define PPC47x_TLB0_64K 0x00000030 68994da93dSChristophe Leroy #define PPC47x_TLB0_1M 0x00000070 69994da93dSChristophe Leroy #define PPC47x_TLB0_16M 0x000000f0 70994da93dSChristophe Leroy #define PPC47x_TLB0_256M 0x000001f0 71994da93dSChristophe Leroy #define PPC47x_TLB0_1G 0x000003f0 72994da93dSChristophe Leroy #define PPC47x_TLB0_BOLTED_R 0x00000008 /* tlbre only */ 73994da93dSChristophe Leroy 74994da93dSChristophe Leroy /* Translation fields */ 75994da93dSChristophe Leroy #define PPC47x_TLB1_RPN_MASK 0xfffff000 /* Real Page Number */ 76994da93dSChristophe Leroy #define PPC47x_TLB1_ERPN_MASK 0x000003ff 77994da93dSChristophe Leroy 78994da93dSChristophe Leroy /* Storage attribute and access control fields */ 79994da93dSChristophe Leroy #define PPC47x_TLB2_ATTR_MASK 0x0003ff80 80994da93dSChristophe Leroy #define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */ 81994da93dSChristophe Leroy #define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */ 82994da93dSChristophe Leroy #define PPC47x_TLB2_U0 0x00008000 /* User 0 */ 83994da93dSChristophe Leroy #define PPC47x_TLB2_U1 0x00004000 /* User 1 */ 84994da93dSChristophe Leroy #define PPC47x_TLB2_U2 0x00002000 /* User 2 */ 85994da93dSChristophe Leroy #define PPC47x_TLB2_U3 0x00001000 /* User 3 */ 86994da93dSChristophe Leroy #define PPC47x_TLB2_W 0x00000800 /* Caching is write-through */ 87994da93dSChristophe Leroy #define PPC47x_TLB2_I 0x00000400 /* Caching is inhibited */ 88994da93dSChristophe Leroy #define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */ 89994da93dSChristophe Leroy #define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */ 90994da93dSChristophe Leroy #define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */ 91994da93dSChristophe Leroy #define PPC47x_TLB2_PERM_MASK 0x0000003f 92994da93dSChristophe Leroy #define PPC47x_TLB2_UX 0x00000020 /* User execution */ 93994da93dSChristophe Leroy #define PPC47x_TLB2_UW 0x00000010 /* User write */ 94994da93dSChristophe Leroy #define PPC47x_TLB2_UR 0x00000008 /* User read */ 95994da93dSChristophe Leroy #define PPC47x_TLB2_SX 0x00000004 /* Super execution */ 96994da93dSChristophe Leroy #define PPC47x_TLB2_SW 0x00000002 /* Super write */ 97994da93dSChristophe Leroy #define PPC47x_TLB2_SR 0x00000001 /* Super read */ 98994da93dSChristophe Leroy #define PPC47x_TLB2_U_RWX (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR) 99994da93dSChristophe Leroy #define PPC47x_TLB2_S_RWX (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR) 100994da93dSChristophe Leroy #define PPC47x_TLB2_S_RW (PPC47x_TLB2_SW | PPC47x_TLB2_SR) 101994da93dSChristophe Leroy #define PPC47x_TLB2_IMG (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G) 102994da93dSChristophe Leroy 103994da93dSChristophe Leroy #ifndef __ASSEMBLY__ 104994da93dSChristophe Leroy 105994da93dSChristophe Leroy extern unsigned int tlb_44x_hwater; 106994da93dSChristophe Leroy extern unsigned int tlb_44x_index; 107994da93dSChristophe Leroy 108994da93dSChristophe Leroy typedef struct { 109994da93dSChristophe Leroy unsigned int id; 110994da93dSChristophe Leroy unsigned int active; 111994da93dSChristophe Leroy unsigned long vdso_base; 112994da93dSChristophe Leroy } mm_context_t; 113994da93dSChristophe Leroy 114994da93dSChristophe Leroy #endif /* !__ASSEMBLY__ */ 115994da93dSChristophe Leroy 116994da93dSChristophe Leroy #ifndef CONFIG_PPC_EARLY_DEBUG_44x 117994da93dSChristophe Leroy #define PPC44x_EARLY_TLBS 1 118994da93dSChristophe Leroy #else 119994da93dSChristophe Leroy #define PPC44x_EARLY_TLBS 2 120994da93dSChristophe Leroy #define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \ 121994da93dSChristophe Leroy | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff)) 122994da93dSChristophe Leroy #endif 123994da93dSChristophe Leroy 124994da93dSChristophe Leroy /* Size of the TLBs used for pinning in lowmem */ 125994da93dSChristophe Leroy #define PPC_PIN_SIZE (1 << 28) /* 256M */ 126994da93dSChristophe Leroy 127994da93dSChristophe Leroy #if defined(CONFIG_PPC_4K_PAGES) 128994da93dSChristophe Leroy #define PPC44x_TLBE_SIZE PPC44x_TLB_4K 129994da93dSChristophe Leroy #define PPC47x_TLBE_SIZE PPC47x_TLB0_4K 130994da93dSChristophe Leroy #define mmu_virtual_psize MMU_PAGE_4K 131994da93dSChristophe Leroy #elif defined(CONFIG_PPC_16K_PAGES) 132994da93dSChristophe Leroy #define PPC44x_TLBE_SIZE PPC44x_TLB_16K 133994da93dSChristophe Leroy #define PPC47x_TLBE_SIZE PPC47x_TLB0_16K 134994da93dSChristophe Leroy #define mmu_virtual_psize MMU_PAGE_16K 135994da93dSChristophe Leroy #elif defined(CONFIG_PPC_64K_PAGES) 136994da93dSChristophe Leroy #define PPC44x_TLBE_SIZE PPC44x_TLB_64K 137994da93dSChristophe Leroy #define PPC47x_TLBE_SIZE PPC47x_TLB0_64K 138994da93dSChristophe Leroy #define mmu_virtual_psize MMU_PAGE_64K 139994da93dSChristophe Leroy #elif defined(CONFIG_PPC_256K_PAGES) 140994da93dSChristophe Leroy #define PPC44x_TLBE_SIZE PPC44x_TLB_256K 141994da93dSChristophe Leroy #define mmu_virtual_psize MMU_PAGE_256K 142994da93dSChristophe Leroy #else 143994da93dSChristophe Leroy #error "Unsupported PAGE_SIZE" 144994da93dSChristophe Leroy #endif 145994da93dSChristophe Leroy 146994da93dSChristophe Leroy #define mmu_linear_psize MMU_PAGE_256M 147994da93dSChristophe Leroy 148994da93dSChristophe Leroy #define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2) 149994da93dSChristophe Leroy #define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2) 150994da93dSChristophe Leroy #define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2) 151994da93dSChristophe Leroy #define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT) 152994da93dSChristophe Leroy 153994da93dSChristophe Leroy #endif /* _ASM_POWERPC_MMU_44X_H_ */ 154