1 /* 2 * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; version 2 of the 7 * License. 8 * 9 */ 10 11 #ifndef _ASM_MPIC_MSGR_H 12 #define _ASM_MPIC_MSGR_H 13 14 #include <linux/types.h> 15 #include <linux/spinlock.h> 16 #include <asm/smp.h> 17 18 struct mpic_msgr { 19 u32 __iomem *base; 20 u32 __iomem *mer; 21 int irq; 22 unsigned char in_use; 23 raw_spinlock_t lock; 24 int num; 25 }; 26 27 /* Get a message register 28 * 29 * @reg_num: the MPIC message register to get 30 * 31 * A pointer to the message register is returned. If 32 * the message register asked for is already in use, then 33 * EBUSY is returned. If the number given is not associated 34 * with an actual message register, then ENODEV is returned. 35 * Successfully getting the register marks it as in use. 36 */ 37 extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num); 38 39 /* Relinquish a message register 40 * 41 * @msgr: the message register to return 42 * 43 * Disables the given message register and marks it as free. 44 * After this call has completed successully the message 45 * register is available to be acquired by a call to 46 * mpic_msgr_get. 47 */ 48 extern void mpic_msgr_put(struct mpic_msgr *msgr); 49 50 /* Enable a message register 51 * 52 * @msgr: the message register to enable 53 * 54 * The given message register is enabled for sending 55 * messages. 56 */ 57 extern void mpic_msgr_enable(struct mpic_msgr *msgr); 58 59 /* Disable a message register 60 * 61 * @msgr: the message register to disable 62 * 63 * The given message register is disabled for sending 64 * messages. 65 */ 66 extern void mpic_msgr_disable(struct mpic_msgr *msgr); 67 68 /* Write a message to a message register 69 * 70 * @msgr: the message register to write to 71 * @message: the message to write 72 * 73 * The given 32-bit message is written to the given message 74 * register. Writing to an enabled message registers fires 75 * an interrupt. 76 */ 77 static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message) 78 { 79 out_be32(msgr->base, message); 80 } 81 82 /* Read a message from a message register 83 * 84 * @msgr: the message register to read from 85 * 86 * Returns the 32-bit value currently in the given message register. 87 * Upon reading the register any interrupts for that register are 88 * cleared. 89 */ 90 static inline u32 mpic_msgr_read(struct mpic_msgr *msgr) 91 { 92 return in_be32(msgr->base); 93 } 94 95 /* Clear a message register 96 * 97 * @msgr: the message register to clear 98 * 99 * Clears any interrupts associated with the given message register. 100 */ 101 static inline void mpic_msgr_clear(struct mpic_msgr *msgr) 102 { 103 (void) mpic_msgr_read(msgr); 104 } 105 106 /* Set the destination CPU for the message register 107 * 108 * @msgr: the message register whose destination is to be set 109 * @cpu_num: the Linux CPU number to bind the message register to 110 * 111 * Note that the CPU number given is the CPU number used by the kernel 112 * and *not* the actual hardware CPU number. 113 */ 114 static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr, 115 u32 cpu_num) 116 { 117 out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num)); 118 } 119 120 /* Get the IRQ number for the message register 121 * @msgr: the message register whose IRQ is to be returned 122 * 123 * Returns the IRQ number associated with the given message register. 124 * NO_IRQ is returned if this message register is not capable of 125 * receiving interrupts. What message register can and cannot receive 126 * interrupts is specified in the device tree for the system. 127 */ 128 static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr) 129 { 130 return msgr->irq; 131 } 132 133 #endif 134