1 /*
2  * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; version 2 of the
7  * License.
8  *
9  */
10 
11 #ifndef _ASM_MPIC_MSGR_H
12 #define _ASM_MPIC_MSGR_H
13 
14 #include <linux/types.h>
15 #include <linux/spinlock.h>
16 #include <asm/smp.h>
17 #include <asm/io.h>
18 
19 struct mpic_msgr {
20 	u32 __iomem *base;
21 	u32 __iomem *mer;
22 	int irq;
23 	unsigned char in_use;
24 	raw_spinlock_t lock;
25 	int num;
26 };
27 
28 /* Get a message register
29  *
30  * @reg_num:	the MPIC message register to get
31  *
32  * A pointer to the message register is returned.  If
33  * the message register asked for is already in use, then
34  * EBUSY is returned.  If the number given is not associated
35  * with an actual message register, then ENODEV is returned.
36  * Successfully getting the register marks it as in use.
37  */
38 extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
39 
40 /* Relinquish a message register
41  *
42  * @msgr:	the message register to return
43  *
44  * Disables the given message register and marks it as free.
45  * After this call has completed successully the message
46  * register is available to be acquired by a call to
47  * mpic_msgr_get.
48  */
49 extern void mpic_msgr_put(struct mpic_msgr *msgr);
50 
51 /* Enable a message register
52  *
53  * @msgr:	the message register to enable
54  *
55  * The given message register is enabled for sending
56  * messages.
57  */
58 extern void mpic_msgr_enable(struct mpic_msgr *msgr);
59 
60 /* Disable a message register
61  *
62  * @msgr:	the message register to disable
63  *
64  * The given message register is disabled for sending
65  * messages.
66  */
67 extern void mpic_msgr_disable(struct mpic_msgr *msgr);
68 
69 /* Write a message to a message register
70  *
71  * @msgr:	the message register to write to
72  * @message:	the message to write
73  *
74  * The given 32-bit message is written to the given message
75  * register.  Writing to an enabled message registers fires
76  * an interrupt.
77  */
78 static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
79 {
80 	out_be32(msgr->base, message);
81 }
82 
83 /* Read a message from a message register
84  *
85  * @msgr:	the message register to read from
86  *
87  * Returns the 32-bit value currently in the given message register.
88  * Upon reading the register any interrupts for that register are
89  * cleared.
90  */
91 static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
92 {
93 	return in_be32(msgr->base);
94 }
95 
96 /* Clear a message register
97  *
98  * @msgr:	the message register to clear
99  *
100  * Clears any interrupts associated with the given message register.
101  */
102 static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
103 {
104 	(void) mpic_msgr_read(msgr);
105 }
106 
107 /* Set the destination CPU for the message register
108  *
109  * @msgr:	the message register whose destination is to be set
110  * @cpu_num:	the Linux CPU number to bind the message register to
111  *
112  * Note that the CPU number given is the CPU number used by the kernel
113  * and *not* the actual hardware CPU number.
114  */
115 static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
116 					     u32 cpu_num)
117 {
118 	out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
119 }
120 
121 /* Get the IRQ number for the message register
122  * @msgr:	the message register whose IRQ is to be returned
123  *
124  * Returns the IRQ number associated with the given message register.
125  * NO_IRQ is returned if this message register is not capable of
126  * receiving interrupts.  What message register can and cannot receive
127  * interrupts is specified in the device tree for the system.
128  */
129 static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
130 {
131 	return msgr->irq;
132 }
133 
134 #endif
135