xref: /openbmc/linux/arch/powerpc/include/asm/mpc5121.h (revision 4f3db074)
1 /*
2  * MPC5121 Prototypes and definitions
3  *
4  * This file is licensed under the terms of the GNU General Public
5  * License version 2.
6  */
7 
8 #ifndef __ASM_POWERPC_MPC5121_H__
9 #define __ASM_POWERPC_MPC5121_H__
10 
11 /* MPC512x Reset module registers */
12 struct mpc512x_reset_module {
13 	u32	rcwlr;	/* Reset Configuration Word Low Register */
14 	u32	rcwhr;	/* Reset Configuration Word High Register */
15 	u32	reserved1;
16 	u32	reserved2;
17 	u32	rsr;	/* Reset Status Register */
18 	u32	rmr;	/* Reset Mode Register */
19 	u32	rpr;	/* Reset Protection Register */
20 	u32	rcr;	/* Reset Control Register */
21 	u32	rcer;	/* Reset Control Enable Register */
22 };
23 
24 /*
25  * Clock Control Module
26  */
27 struct mpc512x_ccm {
28 	u32	spmr;	/* System PLL Mode Register */
29 	u32	sccr1;	/* System Clock Control Register 1 */
30 	u32	sccr2;	/* System Clock Control Register 2 */
31 	u32	scfr1;	/* System Clock Frequency Register 1 */
32 	u32	scfr2;	/* System Clock Frequency Register 2 */
33 	u32	scfr2s;	/* System Clock Frequency Shadow Register 2 */
34 	u32	bcr;	/* Bread Crumb Register */
35 	u32	psc_ccr[12];	/* PSC Clock Control Registers */
36 	u32	spccr;	/* SPDIF Clock Control Register */
37 	u32	cccr;	/* CFM Clock Control Register */
38 	u32	dccr;	/* DIU Clock Control Register */
39 	u32	mscan_ccr[4];	/* MSCAN Clock Control Registers */
40 	u32	out_ccr[4];	/* OUT CLK Configure Registers */
41 	u32	rsv0[2];	/* Reserved */
42 	u32	scfr3;		/* System Clock Frequency Register 3 */
43 	u32	rsv1[3];	/* Reserved */
44 	u32	spll_lock_cnt;	/* System PLL Lock Counter */
45 	u8	res[0x6c];	/* Reserved */
46 };
47 
48 /*
49  * LPC Module
50  */
51 struct mpc512x_lpc {
52 	u32	cs_cfg[8];	/* CS config */
53 	u32	cs_ctrl;	/* CS Control Register */
54 	u32	cs_status;	/* CS Status Register */
55 	u32	burst_ctrl;	/* CS Burst Control Register */
56 	u32	deadcycle_ctrl;	/* CS Deadcycle Control Register */
57 	u32	holdcycle_ctrl;	/* CS Holdcycle Control Register */
58 	u32	alt;		/* Address Latch Timing Register */
59 };
60 
61 int mpc512x_cs_config(unsigned int cs, u32 val);
62 
63 #endif /* __ASM_POWERPC_MPC5121_H__ */
64