1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <linux/types.h> 6 7 #include <asm/asm-compat.h> 8 #include <asm/feature-fixups.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * First half is MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_3E ASM_CONST(0x00000020) 23 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000040) 24 25 /* 26 * This is individual features 27 */ 28 29 /* Enable use of high BAT registers */ 30 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 31 32 /* Enable >32-bit physical addresses on 32-bit processor, only used 33 * by CONFIG_6xx currently as BookE supports that from day 1 34 */ 35 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 36 37 /* Enable use of broadcast TLB invalidations. We don't always set it 38 * on processors that support it due to other constraints with the 39 * use of such invalidations 40 */ 41 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 42 43 /* Enable use of tlbilx invalidate instructions. 44 */ 45 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 46 47 /* This indicates that the processor cannot handle multiple outstanding 48 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 49 * around such invalidate forms. 50 */ 51 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 52 53 /* This indicates that the processor doesn't handle way selection 54 * properly and needs SW to track and update the LRU state. This 55 * is specific to an errata on e300c2/c3/c4 class parts 56 */ 57 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 58 59 /* Enable use of TLB reservation. Processor should support tlbsrx. 60 * instruction and MAS0[WQ]. 61 */ 62 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 63 64 /* Use paired MAS registers (MAS7||MAS3, etc.) 65 */ 66 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 67 68 /* MMU is SLB-based 69 */ 70 #define MMU_FTR_SLB ASM_CONST(0x02000000) 71 72 /* Support 16M large pages 73 */ 74 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 75 76 /* Supports TLBIEL variant 77 */ 78 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 79 80 /* Supports tlbies w/o locking 81 */ 82 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 83 84 /* Large pages can be marked CI 85 */ 86 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 87 88 /* 1T segments available 89 */ 90 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 91 92 /* Doesn't support the B bit (1T segment) in SLBIE 93 */ 94 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000) 95 96 /* MMU feature bit sets for various CPUs */ 97 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ 98 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 99 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 100 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 101 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 102 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 103 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 104 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 105 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 106 MMU_FTR_CI_LARGE_PAGE 107 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 108 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 109 #define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \ 110 MMU_FTR_USE_TLBIVAX_BCAST | \ 111 MMU_FTR_LOCK_BCAST_INVAL | \ 112 MMU_FTR_USE_TLBRSRV | \ 113 MMU_FTR_USE_PAIRED_MAS | \ 114 MMU_FTR_TLBIEL | \ 115 MMU_FTR_16M_PAGE 116 #ifndef __ASSEMBLY__ 117 #include <asm/cputable.h> 118 119 #ifdef CONFIG_PPC_FSL_BOOK3E 120 #include <asm/percpu.h> 121 DECLARE_PER_CPU(int, next_tlbcam_idx); 122 #endif 123 124 static inline int mmu_has_feature(unsigned long feature) 125 { 126 return (cur_cpu_spec->mmu_features & feature); 127 } 128 129 static inline void mmu_clear_feature(unsigned long feature) 130 { 131 cur_cpu_spec->mmu_features &= ~feature; 132 } 133 134 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 135 136 /* MMU initialization */ 137 extern void early_init_mmu(void); 138 extern void early_init_mmu_secondary(void); 139 140 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 141 phys_addr_t first_memblock_size); 142 143 #ifdef CONFIG_PPC64 144 /* This is our real memory area size on ppc64 server, on embedded, we 145 * make it match the size our of bolted TLB area 146 */ 147 extern u64 ppc64_rma_size; 148 #endif /* CONFIG_PPC64 */ 149 150 struct mm_struct; 151 #ifdef CONFIG_DEBUG_VM 152 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 153 #else /* CONFIG_DEBUG_VM */ 154 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 155 { 156 } 157 #endif /* !CONFIG_DEBUG_VM */ 158 159 #endif /* !__ASSEMBLY__ */ 160 161 /* The kernel use the constants below to index in the page sizes array. 162 * The use of fixed constants for this purpose is better for performances 163 * of the low level hash refill handlers. 164 * 165 * A non supported page size has a "shift" field set to 0 166 * 167 * Any new page size being implemented can get a new entry in here. Whether 168 * the kernel will use it or not is a different matter though. The actual page 169 * size used by hugetlbfs is not defined here and may be made variable 170 * 171 * Note: This array ended up being a false good idea as it's growing to the 172 * point where I wonder if we should replace it with something different, 173 * to think about, feedback welcome. --BenH. 174 */ 175 176 /* These are #defines as they have to be used in assembly */ 177 #define MMU_PAGE_4K 0 178 #define MMU_PAGE_16K 1 179 #define MMU_PAGE_64K 2 180 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 181 #define MMU_PAGE_256K 4 182 #define MMU_PAGE_1M 5 183 #define MMU_PAGE_2M 6 184 #define MMU_PAGE_4M 7 185 #define MMU_PAGE_8M 8 186 #define MMU_PAGE_16M 9 187 #define MMU_PAGE_64M 10 188 #define MMU_PAGE_256M 11 189 #define MMU_PAGE_1G 12 190 #define MMU_PAGE_16G 13 191 #define MMU_PAGE_64G 14 192 193 #define MMU_PAGE_COUNT 15 194 195 #if defined(CONFIG_PPC_STD_MMU_64) 196 /* 64-bit classic hash table MMU */ 197 # include <asm/mmu-hash64.h> 198 #elif defined(CONFIG_PPC_STD_MMU_32) 199 /* 32-bit classic hash table MMU */ 200 # include <asm/mmu-hash32.h> 201 #elif defined(CONFIG_40x) 202 /* 40x-style software loaded TLB */ 203 # include <asm/mmu-40x.h> 204 #elif defined(CONFIG_44x) 205 /* 44x-style software loaded TLB */ 206 # include <asm/mmu-44x.h> 207 #elif defined(CONFIG_PPC_BOOK3E_MMU) 208 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 209 # include <asm/mmu-book3e.h> 210 #elif defined (CONFIG_PPC_8xx) 211 /* Motorola/Freescale 8xx software loaded TLB */ 212 # include <asm/mmu-8xx.h> 213 #endif 214 215 216 #endif /* __KERNEL__ */ 217 #endif /* _ASM_POWERPC_MMU_H_ */ 218