1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <asm/asm-compat.h> 6 #include <asm/feature-fixups.h> 7 8 /* 9 * MMU features bit definitions 10 */ 11 12 /* 13 * First half is MMU families 14 */ 15 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 16 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 17 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 18 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 19 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 20 #define MMU_FTR_TYPE_3E ASM_CONST(0x00000020) 21 22 /* 23 * This is individual features 24 */ 25 26 /* Enable use of high BAT registers */ 27 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 28 29 /* Enable >32-bit physical addresses on 32-bit processor, only used 30 * by CONFIG_6xx currently as BookE supports that from day 1 31 */ 32 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 33 34 /* Enable use of broadcast TLB invalidations. We don't always set it 35 * on processors that support it due to other constraints with the 36 * use of such invalidations 37 */ 38 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 39 40 /* Enable use of tlbilx invalidate instructions. 41 */ 42 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 43 44 /* This indicates that the processor cannot handle multiple outstanding 45 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 46 * around such invalidate forms. 47 */ 48 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 49 50 /* This indicates that the processor doesn't handle way selection 51 * properly and needs SW to track and update the LRU state. This 52 * is specific to an errata on e300c2/c3/c4 class parts 53 */ 54 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 55 56 /* This indicates that the processor uses the ISA 2.06 server tlbie 57 * mnemonics 58 */ 59 #define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000) 60 61 /* Enable use of TLB reservation. Processor should support tlbsrx. 62 * instruction and MAS0[WQ]. 63 */ 64 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 65 66 /* Use paired MAS registers (MAS7||MAS3, etc.) 67 */ 68 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 69 70 #ifndef __ASSEMBLY__ 71 #include <asm/cputable.h> 72 73 static inline int mmu_has_feature(unsigned long feature) 74 { 75 return (cur_cpu_spec->mmu_features & feature); 76 } 77 78 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 79 80 /* MMU initialization (64-bit only fo now) */ 81 extern void early_init_mmu(void); 82 extern void early_init_mmu_secondary(void); 83 84 #endif /* !__ASSEMBLY__ */ 85 86 /* The kernel use the constants below to index in the page sizes array. 87 * The use of fixed constants for this purpose is better for performances 88 * of the low level hash refill handlers. 89 * 90 * A non supported page size has a "shift" field set to 0 91 * 92 * Any new page size being implemented can get a new entry in here. Whether 93 * the kernel will use it or not is a different matter though. The actual page 94 * size used by hugetlbfs is not defined here and may be made variable 95 * 96 * Note: This array ended up being a false good idea as it's growing to the 97 * point where I wonder if we should replace it with something different, 98 * to think about, feedback welcome. --BenH. 99 */ 100 101 /* There are #define as they have to be used in assembly 102 * 103 * WARNING: If you change this list, make sure to update the array of 104 * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will 105 * happen 106 */ 107 #define MMU_PAGE_4K 0 108 #define MMU_PAGE_16K 1 109 #define MMU_PAGE_64K 2 110 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 111 #define MMU_PAGE_256K 4 112 #define MMU_PAGE_1M 5 113 #define MMU_PAGE_8M 6 114 #define MMU_PAGE_16M 7 115 #define MMU_PAGE_256M 8 116 #define MMU_PAGE_1G 9 117 #define MMU_PAGE_16G 10 118 #define MMU_PAGE_64G 11 119 #define MMU_PAGE_COUNT 12 120 121 122 #if defined(CONFIG_PPC_STD_MMU_64) 123 /* 64-bit classic hash table MMU */ 124 # include <asm/mmu-hash64.h> 125 #elif defined(CONFIG_PPC_STD_MMU_32) 126 /* 32-bit classic hash table MMU */ 127 # include <asm/mmu-hash32.h> 128 #elif defined(CONFIG_40x) 129 /* 40x-style software loaded TLB */ 130 # include <asm/mmu-40x.h> 131 #elif defined(CONFIG_44x) 132 /* 44x-style software loaded TLB */ 133 # include <asm/mmu-44x.h> 134 #elif defined(CONFIG_PPC_BOOK3E_MMU) 135 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 136 # include <asm/mmu-book3e.h> 137 #elif defined (CONFIG_PPC_8xx) 138 /* Motorola/Freescale 8xx software loaded TLB */ 139 # include <asm/mmu-8xx.h> 140 #endif 141 142 143 #endif /* __KERNEL__ */ 144 #endif /* _ASM_POWERPC_MMU_H_ */ 145