1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <linux/types.h> 6 7 #include <asm/asm-compat.h> 8 #include <asm/feature-fixups.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * First half is MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 23 24 /* 25 * This is individual features 26 */ 27 28 /* Enable use of high BAT registers */ 29 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 30 31 /* Enable >32-bit physical addresses on 32-bit processor, only used 32 * by CONFIG_6xx currently as BookE supports that from day 1 33 */ 34 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 35 36 /* Enable use of broadcast TLB invalidations. We don't always set it 37 * on processors that support it due to other constraints with the 38 * use of such invalidations 39 */ 40 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 41 42 /* Enable use of tlbilx invalidate instructions. 43 */ 44 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 45 46 /* This indicates that the processor cannot handle multiple outstanding 47 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 48 * around such invalidate forms. 49 */ 50 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 51 52 /* This indicates that the processor doesn't handle way selection 53 * properly and needs SW to track and update the LRU state. This 54 * is specific to an errata on e300c2/c3/c4 class parts 55 */ 56 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 57 58 /* Enable use of TLB reservation. Processor should support tlbsrx. 59 * instruction and MAS0[WQ]. 60 */ 61 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 62 63 /* Use paired MAS registers (MAS7||MAS3, etc.) 64 */ 65 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 66 67 /* Doesn't support the B bit (1T segment) in SLBIE 68 */ 69 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) 70 71 /* Support 16M large pages 72 */ 73 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 74 75 /* Supports TLBIEL variant 76 */ 77 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 78 79 /* Supports tlbies w/o locking 80 */ 81 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 82 83 /* Large pages can be marked CI 84 */ 85 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 86 87 /* 1T segments available 88 */ 89 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 90 91 /* 92 * Radix page table available 93 */ 94 #define MMU_FTR_RADIX ASM_CONST(0x80000000) 95 96 /* MMU feature bit sets for various CPUs */ 97 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ 98 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 99 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 100 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 101 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 102 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 103 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 104 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 105 #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 106 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 107 MMU_FTR_CI_LARGE_PAGE 108 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 109 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 110 #ifndef __ASSEMBLY__ 111 #include <asm/cputable.h> 112 113 #ifdef CONFIG_PPC_FSL_BOOK3E 114 #include <asm/percpu.h> 115 DECLARE_PER_CPU(int, next_tlbcam_idx); 116 #endif 117 118 enum { 119 MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx | 120 MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E | 121 MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS | 122 MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX | 123 MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU | 124 MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS | 125 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 126 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 127 MMU_FTR_1T_SEGMENT | 128 #ifdef CONFIG_PPC_RADIX_MMU 129 MMU_FTR_RADIX | 130 #endif 131 0, 132 }; 133 134 static inline int mmu_has_feature(unsigned long feature) 135 { 136 return (MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); 137 } 138 139 static inline void mmu_clear_feature(unsigned long feature) 140 { 141 cur_cpu_spec->mmu_features &= ~feature; 142 } 143 144 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 145 146 #ifdef CONFIG_PPC64 147 /* This is our real memory area size on ppc64 server, on embedded, we 148 * make it match the size our of bolted TLB area 149 */ 150 extern u64 ppc64_rma_size; 151 #endif /* CONFIG_PPC64 */ 152 153 struct mm_struct; 154 #ifdef CONFIG_DEBUG_VM 155 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 156 #else /* CONFIG_DEBUG_VM */ 157 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 158 { 159 } 160 #endif /* !CONFIG_DEBUG_VM */ 161 162 #endif /* !__ASSEMBLY__ */ 163 164 /* The kernel use the constants below to index in the page sizes array. 165 * The use of fixed constants for this purpose is better for performances 166 * of the low level hash refill handlers. 167 * 168 * A non supported page size has a "shift" field set to 0 169 * 170 * Any new page size being implemented can get a new entry in here. Whether 171 * the kernel will use it or not is a different matter though. The actual page 172 * size used by hugetlbfs is not defined here and may be made variable 173 * 174 * Note: This array ended up being a false good idea as it's growing to the 175 * point where I wonder if we should replace it with something different, 176 * to think about, feedback welcome. --BenH. 177 */ 178 179 /* These are #defines as they have to be used in assembly */ 180 #define MMU_PAGE_4K 0 181 #define MMU_PAGE_16K 1 182 #define MMU_PAGE_64K 2 183 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 184 #define MMU_PAGE_256K 4 185 #define MMU_PAGE_1M 5 186 #define MMU_PAGE_2M 6 187 #define MMU_PAGE_4M 7 188 #define MMU_PAGE_8M 8 189 #define MMU_PAGE_16M 9 190 #define MMU_PAGE_64M 10 191 #define MMU_PAGE_256M 11 192 #define MMU_PAGE_1G 12 193 #define MMU_PAGE_16G 13 194 #define MMU_PAGE_64G 14 195 196 #define MMU_PAGE_COUNT 15 197 198 #ifdef CONFIG_PPC_BOOK3S_64 199 #include <asm/book3s/64/mmu.h> 200 #else /* CONFIG_PPC_BOOK3S_64 */ 201 202 #ifndef __ASSEMBLY__ 203 /* MMU initialization */ 204 extern void early_init_mmu(void); 205 extern void early_init_mmu_secondary(void); 206 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 207 phys_addr_t first_memblock_size); 208 #endif /* __ASSEMBLY__ */ 209 #endif 210 211 #if defined(CONFIG_PPC_STD_MMU_32) 212 /* 32-bit classic hash table MMU */ 213 #include <asm/book3s/32/mmu-hash.h> 214 #elif defined(CONFIG_40x) 215 /* 40x-style software loaded TLB */ 216 # include <asm/mmu-40x.h> 217 #elif defined(CONFIG_44x) 218 /* 44x-style software loaded TLB */ 219 # include <asm/mmu-44x.h> 220 #elif defined(CONFIG_PPC_BOOK3E_MMU) 221 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 222 # include <asm/mmu-book3e.h> 223 #elif defined (CONFIG_PPC_8xx) 224 /* Motorola/Freescale 8xx software loaded TLB */ 225 # include <asm/mmu-8xx.h> 226 #endif 227 228 #ifndef radix_enabled 229 #define radix_enabled() (0) 230 #endif 231 232 #endif /* __KERNEL__ */ 233 #endif /* _ASM_POWERPC_MMU_H_ */ 234