1 #ifndef _ASM_POWERPC_MMU_H_ 2 #define _ASM_POWERPC_MMU_H_ 3 #ifdef __KERNEL__ 4 5 #include <linux/types.h> 6 7 #include <asm/asm-compat.h> 8 #include <asm/feature-fixups.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * First half is MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 23 24 /* 25 * This is individual features 26 */ 27 28 /* Enable use of high BAT registers */ 29 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 30 31 /* Enable >32-bit physical addresses on 32-bit processor, only used 32 * by CONFIG_6xx currently as BookE supports that from day 1 33 */ 34 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 35 36 /* Enable use of broadcast TLB invalidations. We don't always set it 37 * on processors that support it due to other constraints with the 38 * use of such invalidations 39 */ 40 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 41 42 /* Enable use of tlbilx invalidate instructions. 43 */ 44 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 45 46 /* This indicates that the processor cannot handle multiple outstanding 47 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 48 * around such invalidate forms. 49 */ 50 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 51 52 /* This indicates that the processor doesn't handle way selection 53 * properly and needs SW to track and update the LRU state. This 54 * is specific to an errata on e300c2/c3/c4 class parts 55 */ 56 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 57 58 /* Enable use of TLB reservation. Processor should support tlbsrx. 59 * instruction and MAS0[WQ]. 60 */ 61 #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) 62 63 /* Use paired MAS registers (MAS7||MAS3, etc.) 64 */ 65 #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) 66 67 /* MMU is SLB-based 68 */ 69 #define MMU_FTR_SLB ASM_CONST(0x02000000) 70 71 /* Support 16M large pages 72 */ 73 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 74 75 /* Supports TLBIEL variant 76 */ 77 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 78 79 /* Supports tlbies w/o locking 80 */ 81 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 82 83 /* Large pages can be marked CI 84 */ 85 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 86 87 /* 1T segments available 88 */ 89 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 90 91 /* Doesn't support the B bit (1T segment) in SLBIE 92 */ 93 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000) 94 95 /* MMU feature bit sets for various CPUs */ 96 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ 97 MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 98 #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 99 #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 100 #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 101 #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 102 #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 103 #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE 104 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 105 MMU_FTR_CI_LARGE_PAGE 106 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 107 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 108 #ifndef __ASSEMBLY__ 109 #include <asm/cputable.h> 110 111 #ifdef CONFIG_PPC_FSL_BOOK3E 112 #include <asm/percpu.h> 113 DECLARE_PER_CPU(int, next_tlbcam_idx); 114 #endif 115 116 static inline int mmu_has_feature(unsigned long feature) 117 { 118 return (cur_cpu_spec->mmu_features & feature); 119 } 120 121 static inline void mmu_clear_feature(unsigned long feature) 122 { 123 cur_cpu_spec->mmu_features &= ~feature; 124 } 125 126 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 127 128 /* MMU initialization */ 129 extern void early_init_mmu(void); 130 extern void early_init_mmu_secondary(void); 131 132 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 133 phys_addr_t first_memblock_size); 134 135 #ifdef CONFIG_PPC64 136 /* This is our real memory area size on ppc64 server, on embedded, we 137 * make it match the size our of bolted TLB area 138 */ 139 extern u64 ppc64_rma_size; 140 #endif /* CONFIG_PPC64 */ 141 142 struct mm_struct; 143 #ifdef CONFIG_DEBUG_VM 144 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 145 #else /* CONFIG_DEBUG_VM */ 146 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 147 { 148 } 149 #endif /* !CONFIG_DEBUG_VM */ 150 151 #endif /* !__ASSEMBLY__ */ 152 153 /* The kernel use the constants below to index in the page sizes array. 154 * The use of fixed constants for this purpose is better for performances 155 * of the low level hash refill handlers. 156 * 157 * A non supported page size has a "shift" field set to 0 158 * 159 * Any new page size being implemented can get a new entry in here. Whether 160 * the kernel will use it or not is a different matter though. The actual page 161 * size used by hugetlbfs is not defined here and may be made variable 162 * 163 * Note: This array ended up being a false good idea as it's growing to the 164 * point where I wonder if we should replace it with something different, 165 * to think about, feedback welcome. --BenH. 166 */ 167 168 /* These are #defines as they have to be used in assembly */ 169 #define MMU_PAGE_4K 0 170 #define MMU_PAGE_16K 1 171 #define MMU_PAGE_64K 2 172 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 173 #define MMU_PAGE_256K 4 174 #define MMU_PAGE_1M 5 175 #define MMU_PAGE_2M 6 176 #define MMU_PAGE_4M 7 177 #define MMU_PAGE_8M 8 178 #define MMU_PAGE_16M 9 179 #define MMU_PAGE_64M 10 180 #define MMU_PAGE_256M 11 181 #define MMU_PAGE_1G 12 182 #define MMU_PAGE_16G 13 183 #define MMU_PAGE_64G 14 184 185 #define MMU_PAGE_COUNT 15 186 187 #if defined(CONFIG_PPC_STD_MMU_64) 188 /* 64-bit classic hash table MMU */ 189 # include <asm/mmu-hash64.h> 190 #elif defined(CONFIG_PPC_STD_MMU_32) 191 /* 32-bit classic hash table MMU */ 192 # include <asm/mmu-hash32.h> 193 #elif defined(CONFIG_40x) 194 /* 40x-style software loaded TLB */ 195 # include <asm/mmu-40x.h> 196 #elif defined(CONFIG_44x) 197 /* 44x-style software loaded TLB */ 198 # include <asm/mmu-44x.h> 199 #elif defined(CONFIG_PPC_BOOK3E_MMU) 200 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ 201 # include <asm/mmu-book3e.h> 202 #elif defined (CONFIG_PPC_8xx) 203 /* Motorola/Freescale 8xx software loaded TLB */ 204 # include <asm/mmu-8xx.h> 205 #endif 206 207 208 #endif /* __KERNEL__ */ 209 #endif /* _ASM_POWERPC_MMU_H_ */ 210