1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_POWERPC_MMU_H_ 3 #define _ASM_POWERPC_MMU_H_ 4 #ifdef __KERNEL__ 5 6 #include <linux/types.h> 7 8 #include <asm/asm-const.h> 9 10 /* 11 * MMU features bit definitions 12 */ 13 14 /* 15 * MMU families 16 */ 17 #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) 18 #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) 19 #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) 20 #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) 21 #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) 22 #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) 23 24 /* Radix page table supported and enabled */ 25 #define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040) 26 27 /* 28 * Individual features below. 29 */ 30 31 /* 32 * Supports KUAP feature 33 * key 0 controlling userspace addresses on radix 34 * Key 3 on hash 35 */ 36 #define MMU_FTR_BOOK3S_KUAP ASM_CONST(0x00000200) 37 38 /* 39 * Supports KUEP feature 40 * key 0 controlling userspace addresses on radix 41 * Key 3 on hash 42 */ 43 #define MMU_FTR_BOOK3S_KUEP ASM_CONST(0x00000400) 44 45 /* 46 * Support for memory protection keys. 47 */ 48 #define MMU_FTR_PKEY ASM_CONST(0x00000800) 49 50 /* Guest Translation Shootdown Enable */ 51 #define MMU_FTR_GTSE ASM_CONST(0x00001000) 52 53 /* 54 * Support for 68 bit VA space. We added that from ISA 2.05 55 */ 56 #define MMU_FTR_68_BIT_VA ASM_CONST(0x00002000) 57 /* 58 * Kernel read only support. 59 * We added the ppp value 0b110 in ISA 2.04. 60 */ 61 #define MMU_FTR_KERNEL_RO ASM_CONST(0x00004000) 62 63 /* 64 * We need to clear top 16bits of va (from the remaining 64 bits )in 65 * tlbie* instructions 66 */ 67 #define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000) 68 69 /* Enable use of high BAT registers */ 70 #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) 71 72 /* Enable >32-bit physical addresses on 32-bit processor, only used 73 * by CONFIG_PPC_BOOK3S_32 currently as BookE supports that from day 1 74 */ 75 #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) 76 77 /* Enable use of broadcast TLB invalidations. We don't always set it 78 * on processors that support it due to other constraints with the 79 * use of such invalidations 80 */ 81 #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) 82 83 /* Enable use of tlbilx invalidate instructions. 84 */ 85 #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) 86 87 /* This indicates that the processor cannot handle multiple outstanding 88 * broadcast tlbivax or tlbsync. This makes the code use a spinlock 89 * around such invalidate forms. 90 */ 91 #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) 92 93 /* This indicates that the processor doesn't handle way selection 94 * properly and needs SW to track and update the LRU state. This 95 * is specific to an errata on e300c2/c3/c4 class parts 96 */ 97 #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) 98 99 /* Doesn't support the B bit (1T segment) in SLBIE 100 */ 101 #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) 102 103 /* Support 16M large pages 104 */ 105 #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) 106 107 /* Supports TLBIEL variant 108 */ 109 #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) 110 111 /* Supports tlbies w/o locking 112 */ 113 #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) 114 115 /* Large pages can be marked CI 116 */ 117 #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) 118 119 /* 1T segments available 120 */ 121 #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) 122 123 /* MMU feature bit sets for various CPUs */ 124 #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 (MMU_FTR_HPTE_TABLE | MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 125 #define MMU_FTRS_POWER MMU_FTRS_DEFAULT_HPTE_ARCH_V2 126 #define MMU_FTRS_PPC970 MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA 127 #define MMU_FTRS_POWER5 MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE 128 #define MMU_FTRS_POWER6 MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA 129 #define MMU_FTRS_POWER7 MMU_FTRS_POWER6 130 #define MMU_FTRS_POWER8 MMU_FTRS_POWER6 131 #define MMU_FTRS_POWER9 MMU_FTRS_POWER6 132 #define MMU_FTRS_POWER10 MMU_FTRS_POWER6 133 #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 134 MMU_FTR_CI_LARGE_PAGE 135 #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ 136 MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B 137 #ifndef __ASSEMBLY__ 138 #include <linux/bug.h> 139 #include <asm/cputable.h> 140 #include <asm/page.h> 141 142 typedef pte_t *pgtable_t; 143 144 #ifdef CONFIG_PPC_FSL_BOOK3E 145 #include <asm/percpu.h> 146 DECLARE_PER_CPU(int, next_tlbcam_idx); 147 #endif 148 149 enum { 150 MMU_FTRS_POSSIBLE = 151 #if defined(CONFIG_PPC_BOOK3S_604) 152 MMU_FTR_HPTE_TABLE | 153 #endif 154 #ifdef CONFIG_PPC_8xx 155 MMU_FTR_TYPE_8xx | 156 #endif 157 #ifdef CONFIG_40x 158 MMU_FTR_TYPE_40x | 159 #endif 160 #ifdef CONFIG_PPC_47x 161 MMU_FTR_TYPE_47x | MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL | 162 #elif defined(CONFIG_44x) 163 MMU_FTR_TYPE_44x | 164 #endif 165 #ifdef CONFIG_E500 166 MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX | 167 #endif 168 #ifdef CONFIG_PPC_BOOK3S_32 169 MMU_FTR_USE_HIGH_BATS | 170 #endif 171 #ifdef CONFIG_PPC_83xx 172 MMU_FTR_NEED_DTLB_SW_LRU | 173 #endif 174 #ifdef CONFIG_PPC_BOOK3S_64 175 MMU_FTR_KERNEL_RO | 176 #ifdef CONFIG_PPC_64S_HASH_MMU 177 MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL | 178 MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE | 179 MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA | 180 MMU_FTR_68_BIT_VA | MMU_FTR_HPTE_TABLE | 181 #endif 182 #ifdef CONFIG_PPC_RADIX_MMU 183 MMU_FTR_TYPE_RADIX | 184 MMU_FTR_GTSE | 185 #endif /* CONFIG_PPC_RADIX_MMU */ 186 #endif 187 #ifdef CONFIG_PPC_KUAP 188 MMU_FTR_BOOK3S_KUAP | 189 #endif /* CONFIG_PPC_KUAP */ 190 #ifdef CONFIG_PPC_MEM_KEYS 191 MMU_FTR_PKEY | 192 #endif 193 #ifdef CONFIG_PPC_KUEP 194 MMU_FTR_BOOK3S_KUEP | 195 #endif /* CONFIG_PPC_KUAP */ 196 197 0, 198 }; 199 200 #if defined(CONFIG_PPC_BOOK3S_604) && !defined(CONFIG_PPC_BOOK3S_603) 201 #define MMU_FTRS_ALWAYS MMU_FTR_HPTE_TABLE 202 #endif 203 #ifdef CONFIG_PPC_8xx 204 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_8xx 205 #endif 206 #ifdef CONFIG_40x 207 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_40x 208 #endif 209 #ifdef CONFIG_PPC_47x 210 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_47x 211 #elif defined(CONFIG_44x) 212 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_44x 213 #endif 214 #ifdef CONFIG_E500 215 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_FSL_E 216 #endif 217 218 /* BOOK3S_64 options */ 219 #if defined(CONFIG_PPC_RADIX_MMU) && !defined(CONFIG_PPC_64S_HASH_MMU) 220 #define MMU_FTRS_ALWAYS MMU_FTR_TYPE_RADIX 221 #elif !defined(CONFIG_PPC_RADIX_MMU) && defined(CONFIG_PPC_64S_HASH_MMU) 222 #define MMU_FTRS_ALWAYS MMU_FTR_HPTE_TABLE 223 #endif 224 225 #ifndef MMU_FTRS_ALWAYS 226 #define MMU_FTRS_ALWAYS 0 227 #endif 228 229 static __always_inline bool early_mmu_has_feature(unsigned long feature) 230 { 231 if (MMU_FTRS_ALWAYS & feature) 232 return true; 233 234 return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature); 235 } 236 237 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 238 #include <linux/jump_label.h> 239 240 #define NUM_MMU_FTR_KEYS 32 241 242 extern struct static_key_true mmu_feature_keys[NUM_MMU_FTR_KEYS]; 243 244 extern void mmu_feature_keys_init(void); 245 246 static __always_inline bool mmu_has_feature(unsigned long feature) 247 { 248 int i; 249 250 #ifndef __clang__ /* clang can't cope with this */ 251 BUILD_BUG_ON(!__builtin_constant_p(feature)); 252 #endif 253 254 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECK_DEBUG 255 if (!static_key_initialized) { 256 printk("Warning! mmu_has_feature() used prior to jump label init!\n"); 257 dump_stack(); 258 return early_mmu_has_feature(feature); 259 } 260 #endif 261 262 if (MMU_FTRS_ALWAYS & feature) 263 return true; 264 265 if (!(MMU_FTRS_POSSIBLE & feature)) 266 return false; 267 268 i = __builtin_ctzl(feature); 269 return static_branch_likely(&mmu_feature_keys[i]); 270 } 271 272 static inline void mmu_clear_feature(unsigned long feature) 273 { 274 int i; 275 276 i = __builtin_ctzl(feature); 277 cur_cpu_spec->mmu_features &= ~feature; 278 static_branch_disable(&mmu_feature_keys[i]); 279 } 280 #else 281 282 static inline void mmu_feature_keys_init(void) 283 { 284 285 } 286 287 static __always_inline bool mmu_has_feature(unsigned long feature) 288 { 289 return early_mmu_has_feature(feature); 290 } 291 292 static inline void mmu_clear_feature(unsigned long feature) 293 { 294 cur_cpu_spec->mmu_features &= ~feature; 295 } 296 #endif /* CONFIG_JUMP_LABEL */ 297 298 extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; 299 300 #ifdef CONFIG_PPC64 301 /* This is our real memory area size on ppc64 server, on embedded, we 302 * make it match the size our of bolted TLB area 303 */ 304 extern u64 ppc64_rma_size; 305 306 /* Cleanup function used by kexec */ 307 extern void mmu_cleanup_all(void); 308 extern void radix__mmu_cleanup_all(void); 309 310 /* Functions for creating and updating partition table on POWER9 */ 311 extern void mmu_partition_table_init(void); 312 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0, 313 unsigned long dw1, bool flush); 314 #endif /* CONFIG_PPC64 */ 315 316 struct mm_struct; 317 #ifdef CONFIG_DEBUG_VM 318 extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); 319 #else /* CONFIG_DEBUG_VM */ 320 static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) 321 { 322 } 323 #endif /* !CONFIG_DEBUG_VM */ 324 325 static __always_inline bool radix_enabled(void) 326 { 327 return mmu_has_feature(MMU_FTR_TYPE_RADIX); 328 } 329 330 static __always_inline bool early_radix_enabled(void) 331 { 332 return early_mmu_has_feature(MMU_FTR_TYPE_RADIX); 333 } 334 335 #ifdef CONFIG_STRICT_KERNEL_RWX 336 static inline bool strict_kernel_rwx_enabled(void) 337 { 338 return rodata_enabled; 339 } 340 #else 341 static inline bool strict_kernel_rwx_enabled(void) 342 { 343 return false; 344 } 345 #endif 346 347 static inline bool strict_module_rwx_enabled(void) 348 { 349 return IS_ENABLED(CONFIG_STRICT_MODULE_RWX) && strict_kernel_rwx_enabled(); 350 } 351 #endif /* !__ASSEMBLY__ */ 352 353 /* The kernel use the constants below to index in the page sizes array. 354 * The use of fixed constants for this purpose is better for performances 355 * of the low level hash refill handlers. 356 * 357 * A non supported page size has a "shift" field set to 0 358 * 359 * Any new page size being implemented can get a new entry in here. Whether 360 * the kernel will use it or not is a different matter though. The actual page 361 * size used by hugetlbfs is not defined here and may be made variable 362 * 363 * Note: This array ended up being a false good idea as it's growing to the 364 * point where I wonder if we should replace it with something different, 365 * to think about, feedback welcome. --BenH. 366 */ 367 368 /* These are #defines as they have to be used in assembly */ 369 #define MMU_PAGE_4K 0 370 #define MMU_PAGE_16K 1 371 #define MMU_PAGE_64K 2 372 #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ 373 #define MMU_PAGE_256K 4 374 #define MMU_PAGE_512K 5 375 #define MMU_PAGE_1M 6 376 #define MMU_PAGE_2M 7 377 #define MMU_PAGE_4M 8 378 #define MMU_PAGE_8M 9 379 #define MMU_PAGE_16M 10 380 #define MMU_PAGE_64M 11 381 #define MMU_PAGE_256M 12 382 #define MMU_PAGE_1G 13 383 #define MMU_PAGE_16G 14 384 #define MMU_PAGE_64G 15 385 386 /* 387 * N.B. we need to change the type of hpte_page_sizes if this gets to be > 16 388 * Also we need to change he type of mm_context.low/high_slices_psize. 389 */ 390 #define MMU_PAGE_COUNT 16 391 392 #ifdef CONFIG_PPC_BOOK3S_64 393 #include <asm/book3s/64/mmu.h> 394 #else /* CONFIG_PPC_BOOK3S_64 */ 395 396 #ifndef __ASSEMBLY__ 397 /* MMU initialization */ 398 extern void early_init_mmu(void); 399 extern void early_init_mmu_secondary(void); 400 extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, 401 phys_addr_t first_memblock_size); 402 static inline void mmu_early_init_devtree(void) { } 403 404 static inline void pkey_early_init_devtree(void) {} 405 406 extern void *abatron_pteptrs[2]; 407 #endif /* __ASSEMBLY__ */ 408 #endif 409 410 #if defined(CONFIG_PPC_BOOK3S_32) 411 /* 32-bit classic hash table MMU */ 412 #include <asm/book3s/32/mmu-hash.h> 413 #elif defined(CONFIG_PPC_MMU_NOHASH) 414 #include <asm/nohash/mmu.h> 415 #endif 416 417 #endif /* __KERNEL__ */ 418 #endif /* _ASM_POWERPC_MMU_H_ */ 419