1 /* 2 * lppaca.h 3 * Copyright (C) 2001 Mike Corrigan IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 #ifndef _ASM_POWERPC_LPPACA_H 20 #define _ASM_POWERPC_LPPACA_H 21 #ifdef __KERNEL__ 22 23 /* These definitions relate to hypervisors that only exist when using 24 * a server type processor 25 */ 26 #ifdef CONFIG_PPC_BOOK3S 27 28 //============================================================================= 29 // 30 // This control block contains the data that is shared between the 31 // hypervisor (PLIC) and the OS. 32 // 33 // 34 //---------------------------------------------------------------------------- 35 #include <linux/cache.h> 36 #include <asm/types.h> 37 #include <asm/mmu.h> 38 39 /* The Hypervisor barfs if the lppaca crosses a page boundary. A 1k 40 * alignment is sufficient to prevent this */ 41 struct lppaca { 42 //============================================================================= 43 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data 44 // NOTE: The xDynXyz fields are fields that will be dynamically changed by 45 // PLIC when preparing to bring a processor online or when dispatching a 46 // virtual processor! 47 //============================================================================= 48 u32 desc; // Eye catcher 0xD397D781 x00-x03 49 u16 size; // Size of this struct x04-x05 50 u16 reserved1; // Reserved x06-x07 51 u16 reserved2:14; // Reserved x08-x09 52 u8 shared_proc:1; // Shared processor indicator ... 53 u8 secondary_thread:1; // Secondary thread indicator ... 54 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A 55 u8 secondary_thread_count; // Secondary thread count x0B-x0B 56 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D 57 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F 58 u32 decr_val; // Value for Decr programming x10-x13 59 u32 pmc_val; // Value for PMC regs x14-x17 60 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B 61 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F 62 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 63 u32 dsei_data; // DSEI data x24-x27 64 u64 sprg3; // SPRG3 value x28-x2F 65 u8 reserved3[40]; // Reserved x30-x57 66 volatile u8 vphn_assoc_counts[8]; // Virtual processor home node 67 // associativity change counters x58-x5F 68 u8 reserved4[32]; // Reserved x60-x7F 69 70 //============================================================================= 71 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 72 //============================================================================= 73 // This Dword contains a byte for each type of interrupt that can occur. 74 // The IPI is a count while the others are just a binary 1 or 0. 75 union { 76 u64 any_int; 77 struct { 78 u16 reserved; // Reserved - cleared by #mpasmbl 79 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO 80 u8 ipi_cnt; // IPI Count 81 u8 decr_int; // DECR interrupt occurred 82 u8 pdc_int; // PDC interrupt occurred 83 u8 quantum_int; // Interrupt quantum reached 84 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending 85 } fields; 86 } int_dword; 87 88 // Whenever any fields in this Dword are set then PLIC will defer the 89 // processing of external interrupts. Note that PLIC will store the 90 // XIRR directly into the xXirrValue field so that another XIRR will 91 // not be presented until this one clears. The layout of the low 92 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the 93 // entire Dword is zero or not. A non-zero value in the low order 94 // 2-bytes will result in SLIC being granted the highest thread 95 // priority upon return. A 0 will return to SLIC as medium priority. 96 u64 plic_defer_ints_area; // Entire Dword 97 98 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to 99 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid. 100 u64 saved_srr0; // Saved SRR0 x10-x17 101 u64 saved_srr1; // Saved SRR1 x18-x1F 102 103 // Used to pass parms from the OS to PLIC for SetAsrAndRfid 104 u64 saved_gpr3; // Saved GPR3 x20-x27 105 u64 saved_gpr4; // Saved GPR4 x28-x2F 106 union { 107 u64 saved_gpr5; /* Saved GPR5 x30-x37 */ 108 struct { 109 u8 cede_latency_hint; /* x30 */ 110 u8 reserved[7]; /* x31-x36 */ 111 } fields; 112 } gpr5_dword; 113 114 115 u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 116 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 117 u8 fpregs_in_use; // FP regs in use x3A-x3A 118 u8 pmcregs_in_use; // PMC regs in use x3B-x3B 119 volatile u32 saved_decr; // Saved Decr Value x3C-x3F 120 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47 121 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F 122 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57 123 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F 124 u64 end_of_quantum; // TB at end of quantum x60-x67 125 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F 126 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77 127 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B 128 u16 slb_count; // # of SLBs to maintain x7C-x7D 129 u8 idle; // Indicate OS is idle x7E 130 u8 vmxregs_in_use; // VMX registers in use x7F 131 132 133 //============================================================================= 134 // CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors 135 //============================================================================= 136 // This is the yield_count. An "odd" value (low bit on) means that 137 // the processor is yielded (either because of an OS yield or a PLIC 138 // preempt). An even value implies that the processor is currently 139 // executing. 140 // NOTE: This value will ALWAYS be zero for dedicated processors and 141 // will NEVER be zero for shared processors (ie, initialized to a 1). 142 volatile u32 yield_count; // PLIC increments each dispatchx00-x03 143 volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 144 volatile u64 cmo_faults; // CMO page fault count x08-x0F 145 volatile u64 cmo_fault_time; // CMO page fault time x10-x17 146 u8 reserved7[104]; // Reserved x18-x7F 147 148 //============================================================================= 149 // CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data 150 //============================================================================= 151 u32 page_ins; // CMO Hint - # page ins by OS x00-x03 152 u8 reserved8[148]; // Reserved x04-x97 153 volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F 154 u8 reserved9[96]; // Reserved xA0-xFF 155 } __attribute__((__aligned__(0x400))); 156 157 extern struct lppaca lppaca[]; 158 159 #define lppaca_of(cpu) (*paca[cpu].lppaca_ptr) 160 161 /* 162 * SLB shadow buffer structure as defined in the PAPR. The save_area 163 * contains adjacent ESID and VSID pairs for each shadowed SLB. The 164 * ESID is stored in the lower 64bits, then the VSID. 165 */ 166 struct slb_shadow { 167 u32 persistent; // Number of persistent SLBs x00-x03 168 u32 buffer_length; // Total shadow buffer length x04-x07 169 u64 reserved; // Alignment x08-x0f 170 struct { 171 u64 esid; 172 u64 vsid; 173 } save_area[SLB_NUM_BOLTED]; // x10-x40 174 } ____cacheline_aligned; 175 176 extern struct slb_shadow slb_shadow[]; 177 178 /* 179 * Layout of entries in the hypervisor's dispatch trace log buffer. 180 */ 181 struct dtl_entry { 182 u8 dispatch_reason; 183 u8 preempt_reason; 184 u16 processor_id; 185 u32 enqueue_to_dispatch_time; 186 u32 ready_to_enqueue_time; 187 u32 waiting_to_ready_time; 188 u64 timebase; 189 u64 fault_addr; 190 u64 srr0; 191 u64 srr1; 192 }; 193 194 #define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */ 195 #define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry)) 196 197 /* 198 * When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls 199 * reading from the dispatch trace log. If other code wants to consume 200 * DTL entries, it can set this pointer to a function that will get 201 * called once for each DTL entry that gets processed. 202 */ 203 extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index); 204 205 #endif /* CONFIG_PPC_BOOK3S */ 206 #endif /* __KERNEL__ */ 207 #endif /* _ASM_POWERPC_LPPACA_H */ 208