1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright SUSE Linux Products GmbH 2010 16 * 17 * Authors: Alexander Graf <agraf@suse.de> 18 */ 19 20 #ifndef __ASM_KVM_BOOK3S_64_H__ 21 #define __ASM_KVM_BOOK3S_64_H__ 22 23 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 24 static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu) 25 { 26 preempt_disable(); 27 return &get_paca()->shadow_vcpu; 28 } 29 30 static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu) 31 { 32 preempt_enable(); 33 } 34 #endif 35 36 #define SPAPR_TCE_SHIFT 12 37 38 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 39 #define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */ 40 #endif 41 42 #define VRMA_VSID 0x1ffffffUL /* 1TB VSID reserved for VRMA */ 43 44 /* 45 * We use a lock bit in HPTE dword 0 to synchronize updates and 46 * accesses to each HPTE, and another bit to indicate non-present 47 * HPTEs. 48 */ 49 #define HPTE_V_HVLOCK 0x40UL 50 #define HPTE_V_ABSENT 0x20UL 51 52 /* 53 * We use this bit in the guest_rpte field of the revmap entry 54 * to indicate a modified HPTE. 55 */ 56 #define HPTE_GR_MODIFIED (1ul << 62) 57 58 /* These bits are reserved in the guest view of the HPTE */ 59 #define HPTE_GR_RESERVED HPTE_GR_MODIFIED 60 61 static inline long try_lock_hpte(__be64 *hpte, unsigned long bits) 62 { 63 unsigned long tmp, old; 64 __be64 be_lockbit, be_bits; 65 66 /* 67 * We load/store in native endian, but the HTAB is in big endian. If 68 * we byte swap all data we apply on the PTE we're implicitly correct 69 * again. 70 */ 71 be_lockbit = cpu_to_be64(HPTE_V_HVLOCK); 72 be_bits = cpu_to_be64(bits); 73 74 asm volatile(" ldarx %0,0,%2\n" 75 " and. %1,%0,%3\n" 76 " bne 2f\n" 77 " or %0,%0,%4\n" 78 " stdcx. %0,0,%2\n" 79 " beq+ 2f\n" 80 " mr %1,%3\n" 81 "2: isync" 82 : "=&r" (tmp), "=&r" (old) 83 : "r" (hpte), "r" (be_bits), "r" (be_lockbit) 84 : "cc", "memory"); 85 return old == 0; 86 } 87 88 static inline int __hpte_actual_psize(unsigned int lp, int psize) 89 { 90 int i, shift; 91 unsigned int mask; 92 93 /* start from 1 ignoring MMU_PAGE_4K */ 94 for (i = 1; i < MMU_PAGE_COUNT; i++) { 95 96 /* invalid penc */ 97 if (mmu_psize_defs[psize].penc[i] == -1) 98 continue; 99 /* 100 * encoding bits per actual page size 101 * PTE LP actual page size 102 * rrrr rrrz >=8KB 103 * rrrr rrzz >=16KB 104 * rrrr rzzz >=32KB 105 * rrrr zzzz >=64KB 106 * ....... 107 */ 108 shift = mmu_psize_defs[i].shift - LP_SHIFT; 109 if (shift > LP_BITS) 110 shift = LP_BITS; 111 mask = (1 << shift) - 1; 112 if ((lp & mask) == mmu_psize_defs[psize].penc[i]) 113 return i; 114 } 115 return -1; 116 } 117 118 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r, 119 unsigned long pte_index) 120 { 121 int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K; 122 unsigned int penc; 123 unsigned long rb = 0, va_low, sllp; 124 unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1); 125 126 if (v & HPTE_V_LARGE) { 127 for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) { 128 129 /* valid entries have a shift value */ 130 if (!mmu_psize_defs[b_psize].shift) 131 continue; 132 133 a_psize = __hpte_actual_psize(lp, b_psize); 134 if (a_psize != -1) 135 break; 136 } 137 } 138 /* 139 * Ignore the top 14 bits of va 140 * v have top two bits covering segment size, hence move 141 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits. 142 * AVA field in v also have the lower 23 bits ignored. 143 * For base page size 4K we need 14 .. 65 bits (so need to 144 * collect extra 11 bits) 145 * For others we need 14..14+i 146 */ 147 /* This covers 14..54 bits of va*/ 148 rb = (v & ~0x7fUL) << 16; /* AVA field */ 149 150 rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */ 151 /* 152 * AVA in v had cleared lower 23 bits. We need to derive 153 * that from pteg index 154 */ 155 va_low = pte_index >> 3; 156 if (v & HPTE_V_SECONDARY) 157 va_low = ~va_low; 158 /* 159 * get the vpn bits from va_low using reverse of hashing. 160 * In v we have va with 23 bits dropped and then left shifted 161 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need 162 * right shift it with (SID_SHIFT - (23 - 7)) 163 */ 164 if (!(v & HPTE_V_1TB_SEG)) 165 va_low ^= v >> (SID_SHIFT - 16); 166 else 167 va_low ^= v >> (SID_SHIFT_1T - 16); 168 va_low &= 0x7ff; 169 170 switch (b_psize) { 171 case MMU_PAGE_4K: 172 sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) | 173 ((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4); 174 rb |= sllp << 5; /* AP field */ 175 rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */ 176 break; 177 default: 178 { 179 int aval_shift; 180 /* 181 * remaining bits of AVA/LP fields 182 * Also contain the rr bits of LP 183 */ 184 rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000; 185 /* 186 * Now clear not needed LP bits based on actual psize 187 */ 188 rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1); 189 /* 190 * AVAL field 58..77 - base_page_shift bits of va 191 * we have space for 58..64 bits, Missing bits should 192 * be zero filled. +1 is to take care of L bit shift 193 */ 194 aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1; 195 rb |= ((va_low << aval_shift) & 0xfe); 196 197 rb |= 1; /* L field */ 198 penc = mmu_psize_defs[b_psize].penc[a_psize]; 199 rb |= penc << 12; /* LP field */ 200 break; 201 } 202 } 203 rb |= (v >> 54) & 0x300; /* B field */ 204 return rb; 205 } 206 207 static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l, 208 bool is_base_size) 209 { 210 211 int size, a_psize; 212 /* Look at the 8 bit LP value */ 213 unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1); 214 215 /* only handle 4k, 64k and 16M pages for now */ 216 if (!(h & HPTE_V_LARGE)) 217 return 1ul << 12; 218 else { 219 for (size = 0; size < MMU_PAGE_COUNT; size++) { 220 /* valid entries have a shift value */ 221 if (!mmu_psize_defs[size].shift) 222 continue; 223 224 a_psize = __hpte_actual_psize(lp, size); 225 if (a_psize != -1) { 226 if (is_base_size) 227 return 1ul << mmu_psize_defs[size].shift; 228 return 1ul << mmu_psize_defs[a_psize].shift; 229 } 230 } 231 232 } 233 return 0; 234 } 235 236 static inline unsigned long hpte_page_size(unsigned long h, unsigned long l) 237 { 238 return __hpte_page_size(h, l, 0); 239 } 240 241 static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l) 242 { 243 return __hpte_page_size(h, l, 1); 244 } 245 246 static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize) 247 { 248 return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT; 249 } 250 251 static inline int hpte_is_writable(unsigned long ptel) 252 { 253 unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP); 254 255 return pp != PP_RXRX && pp != PP_RXXX; 256 } 257 258 static inline unsigned long hpte_make_readonly(unsigned long ptel) 259 { 260 if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX) 261 ptel = (ptel & ~HPTE_R_PP) | PP_RXXX; 262 else 263 ptel |= PP_RXRX; 264 return ptel; 265 } 266 267 static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type) 268 { 269 unsigned int wimg = ptel & HPTE_R_WIMG; 270 271 /* Handle SAO */ 272 if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) && 273 cpu_has_feature(CPU_FTR_ARCH_206)) 274 wimg = HPTE_R_M; 275 276 if (!io_type) 277 return wimg == HPTE_R_M; 278 279 return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type; 280 } 281 282 /* 283 * If it's present and writable, atomically set dirty and referenced bits and 284 * return the PTE, otherwise return 0. If we find a transparent hugepage 285 * and if it is marked splitting we return 0; 286 */ 287 static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing, 288 unsigned int hugepage) 289 { 290 pte_t old_pte, new_pte = __pte(0); 291 292 while (1) { 293 old_pte = pte_val(*ptep); 294 /* 295 * wait until _PAGE_BUSY is clear then set it atomically 296 */ 297 if (unlikely(old_pte & _PAGE_BUSY)) { 298 cpu_relax(); 299 continue; 300 } 301 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 302 /* If hugepage and is trans splitting return None */ 303 if (unlikely(hugepage && 304 pmd_trans_splitting(pte_pmd(old_pte)))) 305 return __pte(0); 306 #endif 307 /* If pte is not present return None */ 308 if (unlikely(!(old_pte & _PAGE_PRESENT))) 309 return __pte(0); 310 311 new_pte = pte_mkyoung(old_pte); 312 if (writing && pte_write(old_pte)) 313 new_pte = pte_mkdirty(new_pte); 314 315 if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte, 316 new_pte)) 317 break; 318 } 319 return new_pte; 320 } 321 322 323 /* Return HPTE cache control bits corresponding to Linux pte bits */ 324 static inline unsigned long hpte_cache_bits(unsigned long pte_val) 325 { 326 #if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W 327 return pte_val & (HPTE_R_W | HPTE_R_I); 328 #else 329 return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) + 330 ((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0); 331 #endif 332 } 333 334 static inline bool hpte_read_permission(unsigned long pp, unsigned long key) 335 { 336 if (key) 337 return PP_RWRX <= pp && pp <= PP_RXRX; 338 return 1; 339 } 340 341 static inline bool hpte_write_permission(unsigned long pp, unsigned long key) 342 { 343 if (key) 344 return pp == PP_RWRW; 345 return pp <= PP_RWRW; 346 } 347 348 static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr) 349 { 350 unsigned long skey; 351 352 skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) | 353 ((hpte_r & HPTE_R_KEY_LO) >> 9); 354 return (amr >> (62 - 2 * skey)) & 3; 355 } 356 357 static inline void lock_rmap(unsigned long *rmap) 358 { 359 do { 360 while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap)) 361 cpu_relax(); 362 } while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap)); 363 } 364 365 static inline void unlock_rmap(unsigned long *rmap) 366 { 367 __clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap); 368 } 369 370 static inline bool slot_is_aligned(struct kvm_memory_slot *memslot, 371 unsigned long pagesize) 372 { 373 unsigned long mask = (pagesize >> PAGE_SHIFT) - 1; 374 375 if (pagesize <= PAGE_SIZE) 376 return 1; 377 return !(memslot->base_gfn & mask) && !(memslot->npages & mask); 378 } 379 380 /* 381 * This works for 4k, 64k and 16M pages on POWER7, 382 * and 4k and 16M pages on PPC970. 383 */ 384 static inline unsigned long slb_pgsize_encoding(unsigned long psize) 385 { 386 unsigned long senc = 0; 387 388 if (psize > 0x1000) { 389 senc = SLB_VSID_L; 390 if (psize == 0x10000) 391 senc |= SLB_VSID_LP_01; 392 } 393 return senc; 394 } 395 396 static inline int is_vrma_hpte(unsigned long hpte_v) 397 { 398 return (hpte_v & ~0xffffffUL) == 399 (HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16))); 400 } 401 402 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 403 /* 404 * Note modification of an HPTE; set the HPTE modified bit 405 * if anyone is interested. 406 */ 407 static inline void note_hpte_modification(struct kvm *kvm, 408 struct revmap_entry *rev) 409 { 410 if (atomic_read(&kvm->arch.hpte_mod_interest)) 411 rev->guest_rpte |= HPTE_GR_MODIFIED; 412 } 413 414 /* 415 * Like kvm_memslots(), but for use in real mode when we can't do 416 * any RCU stuff (since the secondary threads are offline from the 417 * kernel's point of view), and we can't print anything. 418 * Thus we use rcu_dereference_raw() rather than rcu_dereference_check(). 419 */ 420 static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm) 421 { 422 return rcu_dereference_raw_notrace(kvm->memslots); 423 } 424 425 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 426 427 #endif /* __ASM_KVM_BOOK3S_64_H__ */ 428