1 /*
2  * This program is free software; you can redistribute it and/or modify
3  * it under the terms of the GNU General Public License, version 2, as
4  * published by the Free Software Foundation.
5  *
6  * This program is distributed in the hope that it will be useful,
7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9  * GNU General Public License for more details.
10  *
11  * You should have received a copy of the GNU General Public License
12  * along with this program; if not, write to the Free Software
13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
14  *
15  * Copyright SUSE Linux Products GmbH 2010
16  *
17  * Authors: Alexander Graf <agraf@suse.de>
18  */
19 
20 #ifndef __ASM_KVM_BOOK3S_64_H__
21 #define __ASM_KVM_BOOK3S_64_H__
22 
23 #include <linux/string.h>
24 #include <asm/bitops.h>
25 #include <asm/book3s/64/mmu-hash.h>
26 #include <asm/cpu_has_feature.h>
27 #include <asm/ppc-opcode.h>
28 
29 #ifdef CONFIG_PPC_PSERIES
30 static inline bool kvmhv_on_pseries(void)
31 {
32 	return !cpu_has_feature(CPU_FTR_HVMODE);
33 }
34 #else
35 static inline bool kvmhv_on_pseries(void)
36 {
37 	return false;
38 }
39 #endif
40 
41 /*
42  * Structure for a nested guest, that is, for a guest that is managed by
43  * one of our guests.
44  */
45 struct kvm_nested_guest {
46 	struct kvm *l1_host;		/* L1 VM that owns this nested guest */
47 	int l1_lpid;			/* lpid L1 guest thinks this guest is */
48 	int shadow_lpid;		/* real lpid of this nested guest */
49 	pgd_t *shadow_pgtable;		/* our page table for this guest */
50 	u64 l1_gr_to_hr;		/* L1's addr of part'n-scoped table */
51 	u64 process_table;		/* process table entry for this guest */
52 	long refcnt;			/* number of pointers to this struct */
53 	struct mutex tlb_lock;		/* serialize page faults and tlbies */
54 	struct kvm_nested_guest *next;
55 	cpumask_t need_tlb_flush;
56 	cpumask_t cpu_in_guest;
57 	short prev_cpu[NR_CPUS];
58 	u8 radix;			/* is this nested guest radix */
59 };
60 
61 /*
62  * We define a nested rmap entry as a single 64-bit quantity
63  * 0xFFF0000000000000	12-bit lpid field
64  * 0x000FFFFFFFFFF000	40-bit guest 4k page frame number
65  * 0x0000000000000001	1-bit  single entry flag
66  */
67 #define RMAP_NESTED_LPID_MASK		0xFFF0000000000000UL
68 #define RMAP_NESTED_LPID_SHIFT		(52)
69 #define RMAP_NESTED_GPA_MASK		0x000FFFFFFFFFF000UL
70 #define RMAP_NESTED_IS_SINGLE_ENTRY	0x0000000000000001UL
71 
72 /* Structure for a nested guest rmap entry */
73 struct rmap_nested {
74 	struct llist_node list;
75 	u64 rmap;
76 };
77 
78 /*
79  * for_each_nest_rmap_safe - iterate over the list of nested rmap entries
80  *			     safe against removal of the list entry or NULL list
81  * @pos:	a (struct rmap_nested *) to use as a loop cursor
82  * @node:	pointer to the first entry
83  *		NOTE: this can be NULL
84  * @rmapp:	an (unsigned long *) in which to return the rmap entries on each
85  *		iteration
86  *		NOTE: this must point to already allocated memory
87  *
88  * The nested_rmap is a llist of (struct rmap_nested) entries pointed to by the
89  * rmap entry in the memslot. The list is always terminated by a "single entry"
90  * stored in the list element of the final entry of the llist. If there is ONLY
91  * a single entry then this is itself in the rmap entry of the memslot, not a
92  * llist head pointer.
93  *
94  * Note that the iterator below assumes that a nested rmap entry is always
95  * non-zero.  This is true for our usage because the LPID field is always
96  * non-zero (zero is reserved for the host).
97  *
98  * This should be used to iterate over the list of rmap_nested entries with
99  * processing done on the u64 rmap value given by each iteration. This is safe
100  * against removal of list entries and it is always safe to call free on (pos).
101  *
102  * e.g.
103  * struct rmap_nested *cursor;
104  * struct llist_node *first;
105  * unsigned long rmap;
106  * for_each_nest_rmap_safe(cursor, first, &rmap) {
107  *	do_something(rmap);
108  *	free(cursor);
109  * }
110  */
111 #define for_each_nest_rmap_safe(pos, node, rmapp)			       \
112 	for ((pos) = llist_entry((node), typeof(*(pos)), list);		       \
113 	     (node) &&							       \
114 	     (*(rmapp) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ?     \
115 			  ((u64) (node)) : ((pos)->rmap))) &&		       \
116 	     (((node) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ?      \
117 			 ((struct llist_node *) ((pos) = NULL)) :	       \
118 			 (pos)->list.next)), true);			       \
119 	     (pos) = llist_entry((node), typeof(*(pos)), list))
120 
121 struct kvm_nested_guest *kvmhv_get_nested(struct kvm *kvm, int l1_lpid,
122 					  bool create);
123 void kvmhv_put_nested(struct kvm_nested_guest *gp);
124 int kvmhv_nested_next_lpid(struct kvm *kvm, int lpid);
125 
126 /* Encoding of first parameter for H_TLB_INVALIDATE */
127 #define H_TLBIE_P1_ENC(ric, prs, r)	(___PPC_RIC(ric) | ___PPC_PRS(prs) | \
128 					 ___PPC_R(r))
129 
130 /* Power architecture requires HPT is at least 256kiB, at most 64TiB */
131 #define PPC_MIN_HPT_ORDER	18
132 #define PPC_MAX_HPT_ORDER	46
133 
134 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
135 static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
136 {
137 	preempt_disable();
138 	return &get_paca()->shadow_vcpu;
139 }
140 
141 static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
142 {
143 	preempt_enable();
144 }
145 #endif
146 
147 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
148 
149 static inline bool kvm_is_radix(struct kvm *kvm)
150 {
151 	return kvm->arch.radix;
152 }
153 
154 static inline bool kvmhv_vcpu_is_radix(struct kvm_vcpu *vcpu)
155 {
156 	bool radix;
157 
158 	if (vcpu->arch.nested)
159 		radix = vcpu->arch.nested->radix;
160 	else
161 		radix = kvm_is_radix(vcpu->kvm);
162 
163 	return radix;
164 }
165 
166 #define KVM_DEFAULT_HPT_ORDER	24	/* 16MB HPT by default */
167 #endif
168 
169 /*
170  * We use a lock bit in HPTE dword 0 to synchronize updates and
171  * accesses to each HPTE, and another bit to indicate non-present
172  * HPTEs.
173  */
174 #define HPTE_V_HVLOCK	0x40UL
175 #define HPTE_V_ABSENT	0x20UL
176 
177 /*
178  * We use this bit in the guest_rpte field of the revmap entry
179  * to indicate a modified HPTE.
180  */
181 #define HPTE_GR_MODIFIED	(1ul << 62)
182 
183 /* These bits are reserved in the guest view of the HPTE */
184 #define HPTE_GR_RESERVED	HPTE_GR_MODIFIED
185 
186 static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
187 {
188 	unsigned long tmp, old;
189 	__be64 be_lockbit, be_bits;
190 
191 	/*
192 	 * We load/store in native endian, but the HTAB is in big endian. If
193 	 * we byte swap all data we apply on the PTE we're implicitly correct
194 	 * again.
195 	 */
196 	be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
197 	be_bits = cpu_to_be64(bits);
198 
199 	asm volatile("	ldarx	%0,0,%2\n"
200 		     "	and.	%1,%0,%3\n"
201 		     "	bne	2f\n"
202 		     "	or	%0,%0,%4\n"
203 		     "  stdcx.	%0,0,%2\n"
204 		     "	beq+	2f\n"
205 		     "	mr	%1,%3\n"
206 		     "2:	isync"
207 		     : "=&r" (tmp), "=&r" (old)
208 		     : "r" (hpte), "r" (be_bits), "r" (be_lockbit)
209 		     : "cc", "memory");
210 	return old == 0;
211 }
212 
213 static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v)
214 {
215 	hpte_v &= ~HPTE_V_HVLOCK;
216 	asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
217 	hpte[0] = cpu_to_be64(hpte_v);
218 }
219 
220 /* Without barrier */
221 static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v)
222 {
223 	hpte_v &= ~HPTE_V_HVLOCK;
224 	hpte[0] = cpu_to_be64(hpte_v);
225 }
226 
227 /*
228  * These functions encode knowledge of the POWER7/8/9 hardware
229  * interpretations of the HPTE LP (large page size) field.
230  */
231 static inline int kvmppc_hpte_page_shifts(unsigned long h, unsigned long l)
232 {
233 	unsigned int lphi;
234 
235 	if (!(h & HPTE_V_LARGE))
236 		return 12;	/* 4kB */
237 	lphi = (l >> 16) & 0xf;
238 	switch ((l >> 12) & 0xf) {
239 	case 0:
240 		return !lphi ? 24 : 0;		/* 16MB */
241 		break;
242 	case 1:
243 		return 16;			/* 64kB */
244 		break;
245 	case 3:
246 		return !lphi ? 34 : 0;		/* 16GB */
247 		break;
248 	case 7:
249 		return (16 << 8) + 12;		/* 64kB in 4kB */
250 		break;
251 	case 8:
252 		if (!lphi)
253 			return (24 << 8) + 16;	/* 16MB in 64kkB */
254 		if (lphi == 3)
255 			return (24 << 8) + 12;	/* 16MB in 4kB */
256 		break;
257 	}
258 	return 0;
259 }
260 
261 static inline int kvmppc_hpte_base_page_shift(unsigned long h, unsigned long l)
262 {
263 	return kvmppc_hpte_page_shifts(h, l) & 0xff;
264 }
265 
266 static inline int kvmppc_hpte_actual_page_shift(unsigned long h, unsigned long l)
267 {
268 	int tmp = kvmppc_hpte_page_shifts(h, l);
269 
270 	if (tmp >= 0x100)
271 		tmp >>= 8;
272 	return tmp;
273 }
274 
275 static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r)
276 {
277 	int shift = kvmppc_hpte_actual_page_shift(v, r);
278 
279 	if (shift)
280 		return 1ul << shift;
281 	return 0;
282 }
283 
284 static inline int kvmppc_pgsize_lp_encoding(int base_shift, int actual_shift)
285 {
286 	switch (base_shift) {
287 	case 12:
288 		switch (actual_shift) {
289 		case 12:
290 			return 0;
291 		case 16:
292 			return 7;
293 		case 24:
294 			return 0x38;
295 		}
296 		break;
297 	case 16:
298 		switch (actual_shift) {
299 		case 16:
300 			return 1;
301 		case 24:
302 			return 8;
303 		}
304 		break;
305 	case 24:
306 		return 0;
307 	}
308 	return -1;
309 }
310 
311 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
312 					     unsigned long pte_index)
313 {
314 	int a_pgshift, b_pgshift;
315 	unsigned long rb = 0, va_low, sllp;
316 
317 	b_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r);
318 	if (a_pgshift >= 0x100) {
319 		b_pgshift &= 0xff;
320 		a_pgshift >>= 8;
321 	}
322 
323 	/*
324 	 * Ignore the top 14 bits of va
325 	 * v have top two bits covering segment size, hence move
326 	 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
327 	 * AVA field in v also have the lower 23 bits ignored.
328 	 * For base page size 4K we need 14 .. 65 bits (so need to
329 	 * collect extra 11 bits)
330 	 * For others we need 14..14+i
331 	 */
332 	/* This covers 14..54 bits of va*/
333 	rb = (v & ~0x7fUL) << 16;		/* AVA field */
334 
335 	/*
336 	 * AVA in v had cleared lower 23 bits. We need to derive
337 	 * that from pteg index
338 	 */
339 	va_low = pte_index >> 3;
340 	if (v & HPTE_V_SECONDARY)
341 		va_low = ~va_low;
342 	/*
343 	 * get the vpn bits from va_low using reverse of hashing.
344 	 * In v we have va with 23 bits dropped and then left shifted
345 	 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
346 	 * right shift it with (SID_SHIFT - (23 - 7))
347 	 */
348 	if (!(v & HPTE_V_1TB_SEG))
349 		va_low ^= v >> (SID_SHIFT - 16);
350 	else
351 		va_low ^= v >> (SID_SHIFT_1T - 16);
352 	va_low &= 0x7ff;
353 
354 	if (b_pgshift <= 12) {
355 		if (a_pgshift > 12) {
356 			sllp = (a_pgshift == 16) ? 5 : 4;
357 			rb |= sllp << 5;	/*  AP field */
358 		}
359 		rb |= (va_low & 0x7ff) << 12;	/* remaining 11 bits of AVA */
360 	} else {
361 		int aval_shift;
362 		/*
363 		 * remaining bits of AVA/LP fields
364 		 * Also contain the rr bits of LP
365 		 */
366 		rb |= (va_low << b_pgshift) & 0x7ff000;
367 		/*
368 		 * Now clear not needed LP bits based on actual psize
369 		 */
370 		rb &= ~((1ul << a_pgshift) - 1);
371 		/*
372 		 * AVAL field 58..77 - base_page_shift bits of va
373 		 * we have space for 58..64 bits, Missing bits should
374 		 * be zero filled. +1 is to take care of L bit shift
375 		 */
376 		aval_shift = 64 - (77 - b_pgshift) + 1;
377 		rb |= ((va_low << aval_shift) & 0xfe);
378 
379 		rb |= 1;		/* L field */
380 		rb |= r & 0xff000 & ((1ul << a_pgshift) - 1); /* LP field */
381 	}
382 	rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8;	/* B field */
383 	return rb;
384 }
385 
386 static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
387 {
388 	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
389 }
390 
391 static inline int hpte_is_writable(unsigned long ptel)
392 {
393 	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
394 
395 	return pp != PP_RXRX && pp != PP_RXXX;
396 }
397 
398 static inline unsigned long hpte_make_readonly(unsigned long ptel)
399 {
400 	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
401 		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
402 	else
403 		ptel |= PP_RXRX;
404 	return ptel;
405 }
406 
407 static inline bool hpte_cache_flags_ok(unsigned long hptel, bool is_ci)
408 {
409 	unsigned int wimg = hptel & HPTE_R_WIMG;
410 
411 	/* Handle SAO */
412 	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
413 	    cpu_has_feature(CPU_FTR_ARCH_206))
414 		wimg = HPTE_R_M;
415 
416 	if (!is_ci)
417 		return wimg == HPTE_R_M;
418 	/*
419 	 * if host is mapped cache inhibited, make sure hptel also have
420 	 * cache inhibited.
421 	 */
422 	if (wimg & HPTE_R_W) /* FIXME!! is this ok for all guest. ? */
423 		return false;
424 	return !!(wimg & HPTE_R_I);
425 }
426 
427 /*
428  * If it's present and writable, atomically set dirty and referenced bits and
429  * return the PTE, otherwise return 0.
430  */
431 static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing)
432 {
433 	pte_t old_pte, new_pte = __pte(0);
434 
435 	while (1) {
436 		/*
437 		 * Make sure we don't reload from ptep
438 		 */
439 		old_pte = READ_ONCE(*ptep);
440 		/*
441 		 * wait until H_PAGE_BUSY is clear then set it atomically
442 		 */
443 		if (unlikely(pte_val(old_pte) & H_PAGE_BUSY)) {
444 			cpu_relax();
445 			continue;
446 		}
447 		/* If pte is not present return None */
448 		if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
449 			return __pte(0);
450 
451 		new_pte = pte_mkyoung(old_pte);
452 		if (writing && pte_write(old_pte))
453 			new_pte = pte_mkdirty(new_pte);
454 
455 		if (pte_xchg(ptep, old_pte, new_pte))
456 			break;
457 	}
458 	return new_pte;
459 }
460 
461 static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
462 {
463 	if (key)
464 		return PP_RWRX <= pp && pp <= PP_RXRX;
465 	return true;
466 }
467 
468 static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
469 {
470 	if (key)
471 		return pp == PP_RWRW;
472 	return pp <= PP_RWRW;
473 }
474 
475 static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
476 {
477 	unsigned long skey;
478 
479 	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
480 		((hpte_r & HPTE_R_KEY_LO) >> 9);
481 	return (amr >> (62 - 2 * skey)) & 3;
482 }
483 
484 static inline void lock_rmap(unsigned long *rmap)
485 {
486 	do {
487 		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
488 			cpu_relax();
489 	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
490 }
491 
492 static inline void unlock_rmap(unsigned long *rmap)
493 {
494 	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
495 }
496 
497 static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
498 				   unsigned long pagesize)
499 {
500 	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
501 
502 	if (pagesize <= PAGE_SIZE)
503 		return true;
504 	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
505 }
506 
507 /*
508  * This works for 4k, 64k and 16M pages on POWER7,
509  * and 4k and 16M pages on PPC970.
510  */
511 static inline unsigned long slb_pgsize_encoding(unsigned long psize)
512 {
513 	unsigned long senc = 0;
514 
515 	if (psize > 0x1000) {
516 		senc = SLB_VSID_L;
517 		if (psize == 0x10000)
518 			senc |= SLB_VSID_LP_01;
519 	}
520 	return senc;
521 }
522 
523 static inline int is_vrma_hpte(unsigned long hpte_v)
524 {
525 	return (hpte_v & ~0xffffffUL) ==
526 		(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
527 }
528 
529 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
530 /*
531  * Note modification of an HPTE; set the HPTE modified bit
532  * if anyone is interested.
533  */
534 static inline void note_hpte_modification(struct kvm *kvm,
535 					  struct revmap_entry *rev)
536 {
537 	if (atomic_read(&kvm->arch.hpte_mod_interest))
538 		rev->guest_rpte |= HPTE_GR_MODIFIED;
539 }
540 
541 /*
542  * Like kvm_memslots(), but for use in real mode when we can't do
543  * any RCU stuff (since the secondary threads are offline from the
544  * kernel's point of view), and we can't print anything.
545  * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
546  */
547 static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
548 {
549 	return rcu_dereference_raw_notrace(kvm->memslots[0]);
550 }
551 
552 extern void kvmppc_mmu_debugfs_init(struct kvm *kvm);
553 extern void kvmhv_radix_debugfs_init(struct kvm *kvm);
554 
555 extern void kvmhv_rm_send_ipi(int cpu);
556 
557 static inline unsigned long kvmppc_hpt_npte(struct kvm_hpt_info *hpt)
558 {
559 	/* HPTEs are 2**4 bytes long */
560 	return 1UL << (hpt->order - 4);
561 }
562 
563 static inline unsigned long kvmppc_hpt_mask(struct kvm_hpt_info *hpt)
564 {
565 	/* 128 (2**7) bytes in each HPTEG */
566 	return (1UL << (hpt->order - 7)) - 1;
567 }
568 
569 /* Set bits in a dirty bitmap, which is in LE format */
570 static inline void set_dirty_bits(unsigned long *map, unsigned long i,
571 				  unsigned long npages)
572 {
573 
574 	if (npages >= 8)
575 		memset((char *)map + i / 8, 0xff, npages / 8);
576 	else
577 		for (; npages; ++i, --npages)
578 			__set_bit_le(i, map);
579 }
580 
581 static inline void set_dirty_bits_atomic(unsigned long *map, unsigned long i,
582 					 unsigned long npages)
583 {
584 	if (npages >= 8)
585 		memset((char *)map + i / 8, 0xff, npages / 8);
586 	else
587 		for (; npages; ++i, --npages)
588 			set_bit_le(i, map);
589 }
590 
591 static inline u64 sanitize_msr(u64 msr)
592 {
593 	msr &= ~MSR_HV;
594 	msr |= MSR_ME;
595 	return msr;
596 }
597 
598 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
599 static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu)
600 {
601 	vcpu->arch.regs.ccr  = vcpu->arch.cr_tm;
602 	vcpu->arch.regs.xer = vcpu->arch.xer_tm;
603 	vcpu->arch.regs.link  = vcpu->arch.lr_tm;
604 	vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
605 	vcpu->arch.amr = vcpu->arch.amr_tm;
606 	vcpu->arch.ppr = vcpu->arch.ppr_tm;
607 	vcpu->arch.dscr = vcpu->arch.dscr_tm;
608 	vcpu->arch.tar = vcpu->arch.tar_tm;
609 	memcpy(vcpu->arch.regs.gpr, vcpu->arch.gpr_tm,
610 	       sizeof(vcpu->arch.regs.gpr));
611 	vcpu->arch.fp  = vcpu->arch.fp_tm;
612 	vcpu->arch.vr  = vcpu->arch.vr_tm;
613 	vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
614 }
615 
616 static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu)
617 {
618 	vcpu->arch.cr_tm  = vcpu->arch.regs.ccr;
619 	vcpu->arch.xer_tm = vcpu->arch.regs.xer;
620 	vcpu->arch.lr_tm  = vcpu->arch.regs.link;
621 	vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
622 	vcpu->arch.amr_tm = vcpu->arch.amr;
623 	vcpu->arch.ppr_tm = vcpu->arch.ppr;
624 	vcpu->arch.dscr_tm = vcpu->arch.dscr;
625 	vcpu->arch.tar_tm = vcpu->arch.tar;
626 	memcpy(vcpu->arch.gpr_tm, vcpu->arch.regs.gpr,
627 	       sizeof(vcpu->arch.regs.gpr));
628 	vcpu->arch.fp_tm  = vcpu->arch.fp;
629 	vcpu->arch.vr_tm  = vcpu->arch.vr;
630 	vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
631 }
632 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
633 
634 extern int kvmppc_create_pte(struct kvm *kvm, pgd_t *pgtable, pte_t pte,
635 			     unsigned long gpa, unsigned int level,
636 			     unsigned long mmu_seq, unsigned int lpid,
637 			     unsigned long *rmapp, struct rmap_nested **n_rmap);
638 extern void kvmhv_insert_nest_rmap(struct kvm *kvm, unsigned long *rmapp,
639 				   struct rmap_nested **n_rmap);
640 extern void kvmhv_update_nest_rmap_rc_list(struct kvm *kvm, unsigned long *rmapp,
641 					   unsigned long clr, unsigned long set,
642 					   unsigned long hpa, unsigned long nbytes);
643 extern void kvmhv_remove_nest_rmap_range(struct kvm *kvm,
644 				const struct kvm_memory_slot *memslot,
645 				unsigned long gpa, unsigned long hpa,
646 				unsigned long nbytes);
647 
648 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
649 
650 #endif /* __ASM_KVM_BOOK3S_64_H__ */
651