1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * 4 * Copyright SUSE Linux Products GmbH 2010 5 * 6 * Authors: Alexander Graf <agraf@suse.de> 7 */ 8 9 #ifndef __ASM_KVM_BOOK3S_64_H__ 10 #define __ASM_KVM_BOOK3S_64_H__ 11 12 #include <linux/string.h> 13 #include <asm/bitops.h> 14 #include <asm/book3s/64/mmu-hash.h> 15 #include <asm/cpu_has_feature.h> 16 #include <asm/ppc-opcode.h> 17 #include <asm/pte-walk.h> 18 19 #ifdef CONFIG_PPC_PSERIES 20 static inline bool kvmhv_on_pseries(void) 21 { 22 return !cpu_has_feature(CPU_FTR_HVMODE); 23 } 24 #else 25 static inline bool kvmhv_on_pseries(void) 26 { 27 return false; 28 } 29 #endif 30 31 /* 32 * Structure for a nested guest, that is, for a guest that is managed by 33 * one of our guests. 34 */ 35 struct kvm_nested_guest { 36 struct kvm *l1_host; /* L1 VM that owns this nested guest */ 37 int l1_lpid; /* lpid L1 guest thinks this guest is */ 38 int shadow_lpid; /* real lpid of this nested guest */ 39 pgd_t *shadow_pgtable; /* our page table for this guest */ 40 u64 l1_gr_to_hr; /* L1's addr of part'n-scoped table */ 41 u64 process_table; /* process table entry for this guest */ 42 u64 hfscr; /* HFSCR that the L1 requested for this nested guest */ 43 long refcnt; /* number of pointers to this struct */ 44 struct mutex tlb_lock; /* serialize page faults and tlbies */ 45 struct kvm_nested_guest *next; 46 cpumask_t need_tlb_flush; 47 short prev_cpu[NR_CPUS]; 48 u8 radix; /* is this nested guest radix */ 49 }; 50 51 /* 52 * We define a nested rmap entry as a single 64-bit quantity 53 * 0xFFF0000000000000 12-bit lpid field 54 * 0x000FFFFFFFFFF000 40-bit guest 4k page frame number 55 * 0x0000000000000001 1-bit single entry flag 56 */ 57 #define RMAP_NESTED_LPID_MASK 0xFFF0000000000000UL 58 #define RMAP_NESTED_LPID_SHIFT (52) 59 #define RMAP_NESTED_GPA_MASK 0x000FFFFFFFFFF000UL 60 #define RMAP_NESTED_IS_SINGLE_ENTRY 0x0000000000000001UL 61 62 /* Structure for a nested guest rmap entry */ 63 struct rmap_nested { 64 struct llist_node list; 65 u64 rmap; 66 }; 67 68 /* 69 * for_each_nest_rmap_safe - iterate over the list of nested rmap entries 70 * safe against removal of the list entry or NULL list 71 * @pos: a (struct rmap_nested *) to use as a loop cursor 72 * @node: pointer to the first entry 73 * NOTE: this can be NULL 74 * @rmapp: an (unsigned long *) in which to return the rmap entries on each 75 * iteration 76 * NOTE: this must point to already allocated memory 77 * 78 * The nested_rmap is a llist of (struct rmap_nested) entries pointed to by the 79 * rmap entry in the memslot. The list is always terminated by a "single entry" 80 * stored in the list element of the final entry of the llist. If there is ONLY 81 * a single entry then this is itself in the rmap entry of the memslot, not a 82 * llist head pointer. 83 * 84 * Note that the iterator below assumes that a nested rmap entry is always 85 * non-zero. This is true for our usage because the LPID field is always 86 * non-zero (zero is reserved for the host). 87 * 88 * This should be used to iterate over the list of rmap_nested entries with 89 * processing done on the u64 rmap value given by each iteration. This is safe 90 * against removal of list entries and it is always safe to call free on (pos). 91 * 92 * e.g. 93 * struct rmap_nested *cursor; 94 * struct llist_node *first; 95 * unsigned long rmap; 96 * for_each_nest_rmap_safe(cursor, first, &rmap) { 97 * do_something(rmap); 98 * free(cursor); 99 * } 100 */ 101 #define for_each_nest_rmap_safe(pos, node, rmapp) \ 102 for ((pos) = llist_entry((node), typeof(*(pos)), list); \ 103 (node) && \ 104 (*(rmapp) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ? \ 105 ((u64) (node)) : ((pos)->rmap))) && \ 106 (((node) = ((RMAP_NESTED_IS_SINGLE_ENTRY & ((u64) (node))) ? \ 107 ((struct llist_node *) ((pos) = NULL)) : \ 108 (pos)->list.next)), true); \ 109 (pos) = llist_entry((node), typeof(*(pos)), list)) 110 111 struct kvm_nested_guest *kvmhv_get_nested(struct kvm *kvm, int l1_lpid, 112 bool create); 113 void kvmhv_put_nested(struct kvm_nested_guest *gp); 114 int kvmhv_nested_next_lpid(struct kvm *kvm, int lpid); 115 116 /* Encoding of first parameter for H_TLB_INVALIDATE */ 117 #define H_TLBIE_P1_ENC(ric, prs, r) (___PPC_RIC(ric) | ___PPC_PRS(prs) | \ 118 ___PPC_R(r)) 119 120 /* Power architecture requires HPT is at least 256kiB, at most 64TiB */ 121 #define PPC_MIN_HPT_ORDER 18 122 #define PPC_MAX_HPT_ORDER 46 123 124 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE 125 static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu) 126 { 127 preempt_disable(); 128 return &get_paca()->shadow_vcpu; 129 } 130 131 static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu) 132 { 133 preempt_enable(); 134 } 135 #endif 136 137 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 138 139 static inline bool kvm_is_radix(struct kvm *kvm) 140 { 141 return kvm->arch.radix; 142 } 143 144 static inline bool kvmhv_vcpu_is_radix(struct kvm_vcpu *vcpu) 145 { 146 bool radix; 147 148 if (vcpu->arch.nested) 149 radix = vcpu->arch.nested->radix; 150 else 151 radix = kvm_is_radix(vcpu->kvm); 152 153 return radix; 154 } 155 156 unsigned long kvmppc_msr_hard_disable_set_facilities(struct kvm_vcpu *vcpu, unsigned long msr); 157 158 int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcr, u64 *tb); 159 160 #define KVM_DEFAULT_HPT_ORDER 24 /* 16MB HPT by default */ 161 #endif 162 163 /* 164 * Invalid HDSISR value which is used to indicate when HW has not set the reg. 165 * Used to work around an errata. 166 */ 167 #define HDSISR_CANARY 0x7fff 168 169 /* 170 * We use a lock bit in HPTE dword 0 to synchronize updates and 171 * accesses to each HPTE, and another bit to indicate non-present 172 * HPTEs. 173 */ 174 #define HPTE_V_HVLOCK 0x40UL 175 #define HPTE_V_ABSENT 0x20UL 176 177 /* 178 * We use this bit in the guest_rpte field of the revmap entry 179 * to indicate a modified HPTE. 180 */ 181 #define HPTE_GR_MODIFIED (1ul << 62) 182 183 /* These bits are reserved in the guest view of the HPTE */ 184 #define HPTE_GR_RESERVED HPTE_GR_MODIFIED 185 186 static inline long try_lock_hpte(__be64 *hpte, unsigned long bits) 187 { 188 unsigned long tmp, old; 189 __be64 be_lockbit, be_bits; 190 191 /* 192 * We load/store in native endian, but the HTAB is in big endian. If 193 * we byte swap all data we apply on the PTE we're implicitly correct 194 * again. 195 */ 196 be_lockbit = cpu_to_be64(HPTE_V_HVLOCK); 197 be_bits = cpu_to_be64(bits); 198 199 asm volatile(" ldarx %0,0,%2\n" 200 " and. %1,%0,%3\n" 201 " bne 2f\n" 202 " or %0,%0,%4\n" 203 " stdcx. %0,0,%2\n" 204 " beq+ 2f\n" 205 " mr %1,%3\n" 206 "2: isync" 207 : "=&r" (tmp), "=&r" (old) 208 : "r" (hpte), "r" (be_bits), "r" (be_lockbit) 209 : "cc", "memory"); 210 return old == 0; 211 } 212 213 static inline void unlock_hpte(__be64 *hpte, unsigned long hpte_v) 214 { 215 hpte_v &= ~HPTE_V_HVLOCK; 216 asm volatile(PPC_RELEASE_BARRIER "" : : : "memory"); 217 hpte[0] = cpu_to_be64(hpte_v); 218 } 219 220 /* Without barrier */ 221 static inline void __unlock_hpte(__be64 *hpte, unsigned long hpte_v) 222 { 223 hpte_v &= ~HPTE_V_HVLOCK; 224 hpte[0] = cpu_to_be64(hpte_v); 225 } 226 227 /* 228 * These functions encode knowledge of the POWER7/8/9 hardware 229 * interpretations of the HPTE LP (large page size) field. 230 */ 231 static inline int kvmppc_hpte_page_shifts(unsigned long h, unsigned long l) 232 { 233 unsigned int lphi; 234 235 if (!(h & HPTE_V_LARGE)) 236 return 12; /* 4kB */ 237 lphi = (l >> 16) & 0xf; 238 switch ((l >> 12) & 0xf) { 239 case 0: 240 return !lphi ? 24 : 0; /* 16MB */ 241 break; 242 case 1: 243 return 16; /* 64kB */ 244 break; 245 case 3: 246 return !lphi ? 34 : 0; /* 16GB */ 247 break; 248 case 7: 249 return (16 << 8) + 12; /* 64kB in 4kB */ 250 break; 251 case 8: 252 if (!lphi) 253 return (24 << 8) + 16; /* 16MB in 64kkB */ 254 if (lphi == 3) 255 return (24 << 8) + 12; /* 16MB in 4kB */ 256 break; 257 } 258 return 0; 259 } 260 261 static inline int kvmppc_hpte_base_page_shift(unsigned long h, unsigned long l) 262 { 263 return kvmppc_hpte_page_shifts(h, l) & 0xff; 264 } 265 266 static inline int kvmppc_hpte_actual_page_shift(unsigned long h, unsigned long l) 267 { 268 int tmp = kvmppc_hpte_page_shifts(h, l); 269 270 if (tmp >= 0x100) 271 tmp >>= 8; 272 return tmp; 273 } 274 275 static inline unsigned long kvmppc_actual_pgsz(unsigned long v, unsigned long r) 276 { 277 int shift = kvmppc_hpte_actual_page_shift(v, r); 278 279 if (shift) 280 return 1ul << shift; 281 return 0; 282 } 283 284 static inline int kvmppc_pgsize_lp_encoding(int base_shift, int actual_shift) 285 { 286 switch (base_shift) { 287 case 12: 288 switch (actual_shift) { 289 case 12: 290 return 0; 291 case 16: 292 return 7; 293 case 24: 294 return 0x38; 295 } 296 break; 297 case 16: 298 switch (actual_shift) { 299 case 16: 300 return 1; 301 case 24: 302 return 8; 303 } 304 break; 305 case 24: 306 return 0; 307 } 308 return -1; 309 } 310 311 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r, 312 unsigned long pte_index) 313 { 314 int a_pgshift, b_pgshift; 315 unsigned long rb = 0, va_low, sllp; 316 317 b_pgshift = a_pgshift = kvmppc_hpte_page_shifts(v, r); 318 if (a_pgshift >= 0x100) { 319 b_pgshift &= 0xff; 320 a_pgshift >>= 8; 321 } 322 323 /* 324 * Ignore the top 14 bits of va 325 * v have top two bits covering segment size, hence move 326 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits. 327 * AVA field in v also have the lower 23 bits ignored. 328 * For base page size 4K we need 14 .. 65 bits (so need to 329 * collect extra 11 bits) 330 * For others we need 14..14+i 331 */ 332 /* This covers 14..54 bits of va*/ 333 rb = (v & ~0x7fUL) << 16; /* AVA field */ 334 335 /* 336 * AVA in v had cleared lower 23 bits. We need to derive 337 * that from pteg index 338 */ 339 va_low = pte_index >> 3; 340 if (v & HPTE_V_SECONDARY) 341 va_low = ~va_low; 342 /* 343 * get the vpn bits from va_low using reverse of hashing. 344 * In v we have va with 23 bits dropped and then left shifted 345 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need 346 * right shift it with (SID_SHIFT - (23 - 7)) 347 */ 348 if (!(v & HPTE_V_1TB_SEG)) 349 va_low ^= v >> (SID_SHIFT - 16); 350 else 351 va_low ^= v >> (SID_SHIFT_1T - 16); 352 va_low &= 0x7ff; 353 354 if (b_pgshift <= 12) { 355 if (a_pgshift > 12) { 356 sllp = (a_pgshift == 16) ? 5 : 4; 357 rb |= sllp << 5; /* AP field */ 358 } 359 rb |= (va_low & 0x7ff) << 12; /* remaining 11 bits of AVA */ 360 } else { 361 int aval_shift; 362 /* 363 * remaining bits of AVA/LP fields 364 * Also contain the rr bits of LP 365 */ 366 rb |= (va_low << b_pgshift) & 0x7ff000; 367 /* 368 * Now clear not needed LP bits based on actual psize 369 */ 370 rb &= ~((1ul << a_pgshift) - 1); 371 /* 372 * AVAL field 58..77 - base_page_shift bits of va 373 * we have space for 58..64 bits, Missing bits should 374 * be zero filled. +1 is to take care of L bit shift 375 */ 376 aval_shift = 64 - (77 - b_pgshift) + 1; 377 rb |= ((va_low << aval_shift) & 0xfe); 378 379 rb |= 1; /* L field */ 380 rb |= r & 0xff000 & ((1ul << a_pgshift) - 1); /* LP field */ 381 } 382 /* 383 * This sets both bits of the B field in the PTE. 0b1x values are 384 * reserved, but those will have been filtered by kvmppc_do_h_enter. 385 */ 386 rb |= (v >> HPTE_V_SSIZE_SHIFT) << 8; /* B field */ 387 return rb; 388 } 389 390 static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize) 391 { 392 return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT; 393 } 394 395 static inline int hpte_is_writable(unsigned long ptel) 396 { 397 unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP); 398 399 return pp != PP_RXRX && pp != PP_RXXX; 400 } 401 402 static inline unsigned long hpte_make_readonly(unsigned long ptel) 403 { 404 if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX) 405 ptel = (ptel & ~HPTE_R_PP) | PP_RXXX; 406 else 407 ptel |= PP_RXRX; 408 return ptel; 409 } 410 411 static inline bool hpte_cache_flags_ok(unsigned long hptel, bool is_ci) 412 { 413 unsigned int wimg = hptel & HPTE_R_WIMG; 414 415 /* Handle SAO */ 416 if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) && 417 cpu_has_feature(CPU_FTR_ARCH_206)) 418 wimg = HPTE_R_M; 419 420 if (!is_ci) 421 return wimg == HPTE_R_M; 422 /* 423 * if host is mapped cache inhibited, make sure hptel also have 424 * cache inhibited. 425 */ 426 if (wimg & HPTE_R_W) /* FIXME!! is this ok for all guest. ? */ 427 return false; 428 return !!(wimg & HPTE_R_I); 429 } 430 431 /* 432 * If it's present and writable, atomically set dirty and referenced bits and 433 * return the PTE, otherwise return 0. 434 */ 435 static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing) 436 { 437 pte_t old_pte, new_pte = __pte(0); 438 439 while (1) { 440 /* 441 * Make sure we don't reload from ptep 442 */ 443 old_pte = READ_ONCE(*ptep); 444 /* 445 * wait until H_PAGE_BUSY is clear then set it atomically 446 */ 447 if (unlikely(pte_val(old_pte) & H_PAGE_BUSY)) { 448 cpu_relax(); 449 continue; 450 } 451 /* If pte is not present return None */ 452 if (unlikely(!pte_present(old_pte))) 453 return __pte(0); 454 455 new_pte = pte_mkyoung(old_pte); 456 if (writing && pte_write(old_pte)) 457 new_pte = pte_mkdirty(new_pte); 458 459 if (pte_xchg(ptep, old_pte, new_pte)) 460 break; 461 } 462 return new_pte; 463 } 464 465 static inline bool hpte_read_permission(unsigned long pp, unsigned long key) 466 { 467 if (key) 468 return PP_RWRX <= pp && pp <= PP_RXRX; 469 return true; 470 } 471 472 static inline bool hpte_write_permission(unsigned long pp, unsigned long key) 473 { 474 if (key) 475 return pp == PP_RWRW; 476 return pp <= PP_RWRW; 477 } 478 479 static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr) 480 { 481 unsigned long skey; 482 483 skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) | 484 ((hpte_r & HPTE_R_KEY_LO) >> 9); 485 return (amr >> (62 - 2 * skey)) & 3; 486 } 487 488 static inline void lock_rmap(unsigned long *rmap) 489 { 490 do { 491 while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap)) 492 cpu_relax(); 493 } while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap)); 494 } 495 496 static inline void unlock_rmap(unsigned long *rmap) 497 { 498 __clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap); 499 } 500 501 static inline bool slot_is_aligned(struct kvm_memory_slot *memslot, 502 unsigned long pagesize) 503 { 504 unsigned long mask = (pagesize >> PAGE_SHIFT) - 1; 505 506 if (pagesize <= PAGE_SIZE) 507 return true; 508 return !(memslot->base_gfn & mask) && !(memslot->npages & mask); 509 } 510 511 /* 512 * This works for 4k, 64k and 16M pages on POWER7, 513 * and 4k and 16M pages on PPC970. 514 */ 515 static inline unsigned long slb_pgsize_encoding(unsigned long psize) 516 { 517 unsigned long senc = 0; 518 519 if (psize > 0x1000) { 520 senc = SLB_VSID_L; 521 if (psize == 0x10000) 522 senc |= SLB_VSID_LP_01; 523 } 524 return senc; 525 } 526 527 static inline int is_vrma_hpte(unsigned long hpte_v) 528 { 529 return (hpte_v & ~0xffffffUL) == 530 (HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16))); 531 } 532 533 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 534 /* 535 * Note modification of an HPTE; set the HPTE modified bit 536 * if anyone is interested. 537 */ 538 static inline void note_hpte_modification(struct kvm *kvm, 539 struct revmap_entry *rev) 540 { 541 if (atomic_read(&kvm->arch.hpte_mod_interest)) 542 rev->guest_rpte |= HPTE_GR_MODIFIED; 543 } 544 545 /* 546 * Like kvm_memslots(), but for use in real mode when we can't do 547 * any RCU stuff (since the secondary threads are offline from the 548 * kernel's point of view), and we can't print anything. 549 * Thus we use rcu_dereference_raw() rather than rcu_dereference_check(). 550 */ 551 static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm) 552 { 553 return rcu_dereference_raw_check(kvm->memslots[0]); 554 } 555 556 extern void kvmppc_mmu_debugfs_init(struct kvm *kvm); 557 extern void kvmhv_radix_debugfs_init(struct kvm *kvm); 558 559 extern void kvmhv_rm_send_ipi(int cpu); 560 561 static inline unsigned long kvmppc_hpt_npte(struct kvm_hpt_info *hpt) 562 { 563 /* HPTEs are 2**4 bytes long */ 564 return 1UL << (hpt->order - 4); 565 } 566 567 static inline unsigned long kvmppc_hpt_mask(struct kvm_hpt_info *hpt) 568 { 569 /* 128 (2**7) bytes in each HPTEG */ 570 return (1UL << (hpt->order - 7)) - 1; 571 } 572 573 /* Set bits in a dirty bitmap, which is in LE format */ 574 static inline void set_dirty_bits(unsigned long *map, unsigned long i, 575 unsigned long npages) 576 { 577 578 if (npages >= 8) 579 memset((char *)map + i / 8, 0xff, npages / 8); 580 else 581 for (; npages; ++i, --npages) 582 __set_bit_le(i, map); 583 } 584 585 static inline void set_dirty_bits_atomic(unsigned long *map, unsigned long i, 586 unsigned long npages) 587 { 588 if (npages >= 8) 589 memset((char *)map + i / 8, 0xff, npages / 8); 590 else 591 for (; npages; ++i, --npages) 592 set_bit_le(i, map); 593 } 594 595 static inline u64 sanitize_msr(u64 msr) 596 { 597 msr &= ~MSR_HV; 598 msr |= MSR_ME; 599 return msr; 600 } 601 602 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 603 static inline void copy_from_checkpoint(struct kvm_vcpu *vcpu) 604 { 605 vcpu->arch.regs.ccr = vcpu->arch.cr_tm; 606 vcpu->arch.regs.xer = vcpu->arch.xer_tm; 607 vcpu->arch.regs.link = vcpu->arch.lr_tm; 608 vcpu->arch.regs.ctr = vcpu->arch.ctr_tm; 609 vcpu->arch.amr = vcpu->arch.amr_tm; 610 vcpu->arch.ppr = vcpu->arch.ppr_tm; 611 vcpu->arch.dscr = vcpu->arch.dscr_tm; 612 vcpu->arch.tar = vcpu->arch.tar_tm; 613 memcpy(vcpu->arch.regs.gpr, vcpu->arch.gpr_tm, 614 sizeof(vcpu->arch.regs.gpr)); 615 vcpu->arch.fp = vcpu->arch.fp_tm; 616 vcpu->arch.vr = vcpu->arch.vr_tm; 617 vcpu->arch.vrsave = vcpu->arch.vrsave_tm; 618 } 619 620 static inline void copy_to_checkpoint(struct kvm_vcpu *vcpu) 621 { 622 vcpu->arch.cr_tm = vcpu->arch.regs.ccr; 623 vcpu->arch.xer_tm = vcpu->arch.regs.xer; 624 vcpu->arch.lr_tm = vcpu->arch.regs.link; 625 vcpu->arch.ctr_tm = vcpu->arch.regs.ctr; 626 vcpu->arch.amr_tm = vcpu->arch.amr; 627 vcpu->arch.ppr_tm = vcpu->arch.ppr; 628 vcpu->arch.dscr_tm = vcpu->arch.dscr; 629 vcpu->arch.tar_tm = vcpu->arch.tar; 630 memcpy(vcpu->arch.gpr_tm, vcpu->arch.regs.gpr, 631 sizeof(vcpu->arch.regs.gpr)); 632 vcpu->arch.fp_tm = vcpu->arch.fp; 633 vcpu->arch.vr_tm = vcpu->arch.vr; 634 vcpu->arch.vrsave_tm = vcpu->arch.vrsave; 635 } 636 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ 637 638 extern int kvmppc_create_pte(struct kvm *kvm, pgd_t *pgtable, pte_t pte, 639 unsigned long gpa, unsigned int level, 640 unsigned long mmu_seq, unsigned int lpid, 641 unsigned long *rmapp, struct rmap_nested **n_rmap); 642 extern void kvmhv_insert_nest_rmap(struct kvm *kvm, unsigned long *rmapp, 643 struct rmap_nested **n_rmap); 644 extern void kvmhv_update_nest_rmap_rc_list(struct kvm *kvm, unsigned long *rmapp, 645 unsigned long clr, unsigned long set, 646 unsigned long hpa, unsigned long nbytes); 647 extern void kvmhv_remove_nest_rmap_range(struct kvm *kvm, 648 const struct kvm_memory_slot *memslot, 649 unsigned long gpa, unsigned long hpa, 650 unsigned long nbytes); 651 652 static inline pte_t * 653 find_kvm_secondary_pte_unlocked(struct kvm *kvm, unsigned long ea, 654 unsigned *hshift) 655 { 656 pte_t *pte; 657 658 pte = __find_linux_pte(kvm->arch.pgtable, ea, NULL, hshift); 659 return pte; 660 } 661 662 static inline pte_t *find_kvm_secondary_pte(struct kvm *kvm, unsigned long ea, 663 unsigned *hshift) 664 { 665 pte_t *pte; 666 667 VM_WARN(!spin_is_locked(&kvm->mmu_lock), 668 "%s called with kvm mmu_lock not held \n", __func__); 669 pte = __find_linux_pte(kvm->arch.pgtable, ea, NULL, hshift); 670 671 return pte; 672 } 673 674 static inline pte_t *find_kvm_host_pte(struct kvm *kvm, unsigned long mmu_seq, 675 unsigned long ea, unsigned *hshift) 676 { 677 pte_t *pte; 678 679 VM_WARN(!spin_is_locked(&kvm->mmu_lock), 680 "%s called with kvm mmu_lock not held \n", __func__); 681 682 if (mmu_notifier_retry(kvm, mmu_seq)) 683 return NULL; 684 685 pte = __find_linux_pte(kvm->mm->pgd, ea, NULL, hshift); 686 687 return pte; 688 } 689 690 extern pte_t *find_kvm_nested_guest_pte(struct kvm *kvm, unsigned long lpid, 691 unsigned long ea, unsigned *hshift); 692 693 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ 694 695 #endif /* __ASM_KVM_BOOK3S_64_H__ */ 696