1 /*
2  * This program is free software; you can redistribute it and/or modify
3  * it under the terms of the GNU General Public License, version 2, as
4  * published by the Free Software Foundation.
5  *
6  * This program is distributed in the hope that it will be useful,
7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9  * GNU General Public License for more details.
10  *
11  * You should have received a copy of the GNU General Public License
12  * along with this program; if not, write to the Free Software
13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
14  *
15  * Copyright SUSE Linux Products GmbH 2010
16  *
17  * Authors: Alexander Graf <agraf@suse.de>
18  */
19 
20 #ifndef __ASM_KVM_BOOK3S_64_H__
21 #define __ASM_KVM_BOOK3S_64_H__
22 
23 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
24 static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
25 {
26 	preempt_disable();
27 	return &get_paca()->shadow_vcpu;
28 }
29 
30 static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
31 {
32 	preempt_enable();
33 }
34 #endif
35 
36 #define SPAPR_TCE_SHIFT		12
37 
38 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
39 #define KVM_DEFAULT_HPT_ORDER	24	/* 16MB HPT by default */
40 extern unsigned long kvm_rma_pages;
41 #endif
42 
43 #define VRMA_VSID	0x1ffffffUL	/* 1TB VSID reserved for VRMA */
44 
45 /*
46  * We use a lock bit in HPTE dword 0 to synchronize updates and
47  * accesses to each HPTE, and another bit to indicate non-present
48  * HPTEs.
49  */
50 #define HPTE_V_HVLOCK	0x40UL
51 #define HPTE_V_ABSENT	0x20UL
52 
53 /*
54  * We use this bit in the guest_rpte field of the revmap entry
55  * to indicate a modified HPTE.
56  */
57 #define HPTE_GR_MODIFIED	(1ul << 62)
58 
59 /* These bits are reserved in the guest view of the HPTE */
60 #define HPTE_GR_RESERVED	HPTE_GR_MODIFIED
61 
62 static inline long try_lock_hpte(__be64 *hpte, unsigned long bits)
63 {
64 	unsigned long tmp, old;
65 	__be64 be_lockbit, be_bits;
66 
67 	/*
68 	 * We load/store in native endian, but the HTAB is in big endian. If
69 	 * we byte swap all data we apply on the PTE we're implicitly correct
70 	 * again.
71 	 */
72 	be_lockbit = cpu_to_be64(HPTE_V_HVLOCK);
73 	be_bits = cpu_to_be64(bits);
74 
75 	asm volatile("	ldarx	%0,0,%2\n"
76 		     "	and.	%1,%0,%3\n"
77 		     "	bne	2f\n"
78 		     "	or	%0,%0,%4\n"
79 		     "  stdcx.	%0,0,%2\n"
80 		     "	beq+	2f\n"
81 		     "	mr	%1,%3\n"
82 		     "2:	isync"
83 		     : "=&r" (tmp), "=&r" (old)
84 		     : "r" (hpte), "r" (be_bits), "r" (be_lockbit)
85 		     : "cc", "memory");
86 	return old == 0;
87 }
88 
89 static inline int __hpte_actual_psize(unsigned int lp, int psize)
90 {
91 	int i, shift;
92 	unsigned int mask;
93 
94 	/* start from 1 ignoring MMU_PAGE_4K */
95 	for (i = 1; i < MMU_PAGE_COUNT; i++) {
96 
97 		/* invalid penc */
98 		if (mmu_psize_defs[psize].penc[i] == -1)
99 			continue;
100 		/*
101 		 * encoding bits per actual page size
102 		 *        PTE LP     actual page size
103 		 *    rrrr rrrz		>=8KB
104 		 *    rrrr rrzz		>=16KB
105 		 *    rrrr rzzz		>=32KB
106 		 *    rrrr zzzz		>=64KB
107 		 * .......
108 		 */
109 		shift = mmu_psize_defs[i].shift - LP_SHIFT;
110 		if (shift > LP_BITS)
111 			shift = LP_BITS;
112 		mask = (1 << shift) - 1;
113 		if ((lp & mask) == mmu_psize_defs[psize].penc[i])
114 			return i;
115 	}
116 	return -1;
117 }
118 
119 static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
120 					     unsigned long pte_index)
121 {
122 	int b_psize = MMU_PAGE_4K, a_psize = MMU_PAGE_4K;
123 	unsigned int penc;
124 	unsigned long rb = 0, va_low, sllp;
125 	unsigned int lp = (r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
126 
127 	if (v & HPTE_V_LARGE) {
128 		for (b_psize = 0; b_psize < MMU_PAGE_COUNT; b_psize++) {
129 
130 			/* valid entries have a shift value */
131 			if (!mmu_psize_defs[b_psize].shift)
132 				continue;
133 
134 			a_psize = __hpte_actual_psize(lp, b_psize);
135 			if (a_psize != -1)
136 				break;
137 		}
138 	}
139 	/*
140 	 * Ignore the top 14 bits of va
141 	 * v have top two bits covering segment size, hence move
142 	 * by 16 bits, Also clear the lower HPTE_V_AVPN_SHIFT (7) bits.
143 	 * AVA field in v also have the lower 23 bits ignored.
144 	 * For base page size 4K we need 14 .. 65 bits (so need to
145 	 * collect extra 11 bits)
146 	 * For others we need 14..14+i
147 	 */
148 	/* This covers 14..54 bits of va*/
149 	rb = (v & ~0x7fUL) << 16;		/* AVA field */
150 
151 	rb |= v >> (62 - 8);			/*  B field */
152 	/*
153 	 * AVA in v had cleared lower 23 bits. We need to derive
154 	 * that from pteg index
155 	 */
156 	va_low = pte_index >> 3;
157 	if (v & HPTE_V_SECONDARY)
158 		va_low = ~va_low;
159 	/*
160 	 * get the vpn bits from va_low using reverse of hashing.
161 	 * In v we have va with 23 bits dropped and then left shifted
162 	 * HPTE_V_AVPN_SHIFT (7) bits. Now to find vsid we need
163 	 * right shift it with (SID_SHIFT - (23 - 7))
164 	 */
165 	if (!(v & HPTE_V_1TB_SEG))
166 		va_low ^= v >> (SID_SHIFT - 16);
167 	else
168 		va_low ^= v >> (SID_SHIFT_1T - 16);
169 	va_low &= 0x7ff;
170 
171 	switch (b_psize) {
172 	case MMU_PAGE_4K:
173 		sllp = ((mmu_psize_defs[a_psize].sllp & SLB_VSID_L) >> 6) |
174 			((mmu_psize_defs[a_psize].sllp & SLB_VSID_LP) >> 4);
175 		rb |= sllp << 5;	/*  AP field */
176 		rb |= (va_low & 0x7ff) << 12;	/* remaining 11 bits of AVA */
177 		break;
178 	default:
179 	{
180 		int aval_shift;
181 		/*
182 		 * remaining bits of AVA/LP fields
183 		 * Also contain the rr bits of LP
184 		 */
185 		rb |= (va_low << mmu_psize_defs[b_psize].shift) & 0x7ff000;
186 		/*
187 		 * Now clear not needed LP bits based on actual psize
188 		 */
189 		rb &= ~((1ul << mmu_psize_defs[a_psize].shift) - 1);
190 		/*
191 		 * AVAL field 58..77 - base_page_shift bits of va
192 		 * we have space for 58..64 bits, Missing bits should
193 		 * be zero filled. +1 is to take care of L bit shift
194 		 */
195 		aval_shift = 64 - (77 - mmu_psize_defs[b_psize].shift) + 1;
196 		rb |= ((va_low << aval_shift) & 0xfe);
197 
198 		rb |= 1;		/* L field */
199 		penc = mmu_psize_defs[b_psize].penc[a_psize];
200 		rb |= penc << 12;	/* LP field */
201 		break;
202 	}
203 	}
204 	rb |= (v >> 54) & 0x300;		/* B field */
205 	return rb;
206 }
207 
208 static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
209 					     bool is_base_size)
210 {
211 
212 	int size, a_psize;
213 	/* Look at the 8 bit LP value */
214 	unsigned int lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
215 
216 	/* only handle 4k, 64k and 16M pages for now */
217 	if (!(h & HPTE_V_LARGE))
218 		return 1ul << 12;
219 	else {
220 		for (size = 0; size < MMU_PAGE_COUNT; size++) {
221 			/* valid entries have a shift value */
222 			if (!mmu_psize_defs[size].shift)
223 				continue;
224 
225 			a_psize = __hpte_actual_psize(lp, size);
226 			if (a_psize != -1) {
227 				if (is_base_size)
228 					return 1ul << mmu_psize_defs[size].shift;
229 				return 1ul << mmu_psize_defs[a_psize].shift;
230 			}
231 		}
232 
233 	}
234 	return 0;
235 }
236 
237 static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
238 {
239 	return __hpte_page_size(h, l, 0);
240 }
241 
242 static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
243 {
244 	return __hpte_page_size(h, l, 1);
245 }
246 
247 static inline unsigned long hpte_rpn(unsigned long ptel, unsigned long psize)
248 {
249 	return ((ptel & HPTE_R_RPN) & ~(psize - 1)) >> PAGE_SHIFT;
250 }
251 
252 static inline int hpte_is_writable(unsigned long ptel)
253 {
254 	unsigned long pp = ptel & (HPTE_R_PP0 | HPTE_R_PP);
255 
256 	return pp != PP_RXRX && pp != PP_RXXX;
257 }
258 
259 static inline unsigned long hpte_make_readonly(unsigned long ptel)
260 {
261 	if ((ptel & HPTE_R_PP0) || (ptel & HPTE_R_PP) == PP_RWXX)
262 		ptel = (ptel & ~HPTE_R_PP) | PP_RXXX;
263 	else
264 		ptel |= PP_RXRX;
265 	return ptel;
266 }
267 
268 static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
269 {
270 	unsigned int wimg = ptel & HPTE_R_WIMG;
271 
272 	/* Handle SAO */
273 	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
274 	    cpu_has_feature(CPU_FTR_ARCH_206))
275 		wimg = HPTE_R_M;
276 
277 	if (!io_type)
278 		return wimg == HPTE_R_M;
279 
280 	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
281 }
282 
283 /*
284  * If it's present and writable, atomically set dirty and referenced bits and
285  * return the PTE, otherwise return 0. If we find a transparent hugepage
286  * and if it is marked splitting we return 0;
287  */
288 static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
289 						 unsigned int hugepage)
290 {
291 	pte_t old_pte, new_pte = __pte(0);
292 
293 	while (1) {
294 		old_pte = pte_val(*ptep);
295 		/*
296 		 * wait until _PAGE_BUSY is clear then set it atomically
297 		 */
298 		if (unlikely(old_pte & _PAGE_BUSY)) {
299 			cpu_relax();
300 			continue;
301 		}
302 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
303 		/* If hugepage and is trans splitting return None */
304 		if (unlikely(hugepage &&
305 			     pmd_trans_splitting(pte_pmd(old_pte))))
306 			return __pte(0);
307 #endif
308 		/* If pte is not present return None */
309 		if (unlikely(!(old_pte & _PAGE_PRESENT)))
310 			return __pte(0);
311 
312 		new_pte = pte_mkyoung(old_pte);
313 		if (writing && pte_write(old_pte))
314 			new_pte = pte_mkdirty(new_pte);
315 
316 		if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte,
317 					     new_pte))
318 			break;
319 	}
320 	return new_pte;
321 }
322 
323 
324 /* Return HPTE cache control bits corresponding to Linux pte bits */
325 static inline unsigned long hpte_cache_bits(unsigned long pte_val)
326 {
327 #if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
328 	return pte_val & (HPTE_R_W | HPTE_R_I);
329 #else
330 	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
331 		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
332 #endif
333 }
334 
335 static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
336 {
337 	if (key)
338 		return PP_RWRX <= pp && pp <= PP_RXRX;
339 	return 1;
340 }
341 
342 static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
343 {
344 	if (key)
345 		return pp == PP_RWRW;
346 	return pp <= PP_RWRW;
347 }
348 
349 static inline int hpte_get_skey_perm(unsigned long hpte_r, unsigned long amr)
350 {
351 	unsigned long skey;
352 
353 	skey = ((hpte_r & HPTE_R_KEY_HI) >> 57) |
354 		((hpte_r & HPTE_R_KEY_LO) >> 9);
355 	return (amr >> (62 - 2 * skey)) & 3;
356 }
357 
358 static inline void lock_rmap(unsigned long *rmap)
359 {
360 	do {
361 		while (test_bit(KVMPPC_RMAP_LOCK_BIT, rmap))
362 			cpu_relax();
363 	} while (test_and_set_bit_lock(KVMPPC_RMAP_LOCK_BIT, rmap));
364 }
365 
366 static inline void unlock_rmap(unsigned long *rmap)
367 {
368 	__clear_bit_unlock(KVMPPC_RMAP_LOCK_BIT, rmap);
369 }
370 
371 static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
372 				   unsigned long pagesize)
373 {
374 	unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
375 
376 	if (pagesize <= PAGE_SIZE)
377 		return 1;
378 	return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
379 }
380 
381 /*
382  * This works for 4k, 64k and 16M pages on POWER7,
383  * and 4k and 16M pages on PPC970.
384  */
385 static inline unsigned long slb_pgsize_encoding(unsigned long psize)
386 {
387 	unsigned long senc = 0;
388 
389 	if (psize > 0x1000) {
390 		senc = SLB_VSID_L;
391 		if (psize == 0x10000)
392 			senc |= SLB_VSID_LP_01;
393 	}
394 	return senc;
395 }
396 
397 static inline int is_vrma_hpte(unsigned long hpte_v)
398 {
399 	return (hpte_v & ~0xffffffUL) ==
400 		(HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)));
401 }
402 
403 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
404 /*
405  * Note modification of an HPTE; set the HPTE modified bit
406  * if anyone is interested.
407  */
408 static inline void note_hpte_modification(struct kvm *kvm,
409 					  struct revmap_entry *rev)
410 {
411 	if (atomic_read(&kvm->arch.hpte_mod_interest))
412 		rev->guest_rpte |= HPTE_GR_MODIFIED;
413 }
414 
415 /*
416  * Like kvm_memslots(), but for use in real mode when we can't do
417  * any RCU stuff (since the secondary threads are offline from the
418  * kernel's point of view), and we can't print anything.
419  * Thus we use rcu_dereference_raw() rather than rcu_dereference_check().
420  */
421 static inline struct kvm_memslots *kvm_memslots_raw(struct kvm *kvm)
422 {
423 	return rcu_dereference_raw_notrace(kvm->memslots);
424 }
425 
426 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
427 
428 #endif /* __ASM_KVM_BOOK3S_64_H__ */
429