1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 4 * Rewrite, cleanup: 5 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 6 */ 7 8 #ifndef _ASM_IOMMU_H 9 #define _ASM_IOMMU_H 10 #ifdef __KERNEL__ 11 12 #include <linux/compiler.h> 13 #include <linux/spinlock.h> 14 #include <linux/device.h> 15 #include <linux/dma-map-ops.h> 16 #include <linux/bitops.h> 17 #include <asm/machdep.h> 18 #include <asm/types.h> 19 #include <asm/pci-bridge.h> 20 #include <asm/asm-const.h> 21 22 #define IOMMU_PAGE_SHIFT_4K 12 23 #define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K) 24 #define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1)) 25 #define IOMMU_PAGE_ALIGN_4K(addr) ALIGN(addr, IOMMU_PAGE_SIZE_4K) 26 27 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift) 28 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1)) 29 #define IOMMU_PAGE_ALIGN(addr, tblptr) ALIGN(addr, IOMMU_PAGE_SIZE(tblptr)) 30 31 /* Boot time flags */ 32 extern int iommu_is_off; 33 extern int iommu_force_on; 34 35 struct iommu_table_ops { 36 /* 37 * When called with direction==DMA_NONE, it is equal to clear(). 38 * uaddr is a linear map address. 39 */ 40 int (*set)(struct iommu_table *tbl, 41 long index, long npages, 42 unsigned long uaddr, 43 enum dma_data_direction direction, 44 unsigned long attrs); 45 #ifdef CONFIG_IOMMU_API 46 /* 47 * Exchanges existing TCE with new TCE plus direction bits; 48 * returns old TCE and DMA direction mask. 49 * @tce is a physical address. 50 */ 51 int (*xchg_no_kill)(struct iommu_table *tbl, 52 long index, 53 unsigned long *hpa, 54 enum dma_data_direction *direction, 55 bool realmode); 56 57 void (*tce_kill)(struct iommu_table *tbl, 58 unsigned long index, 59 unsigned long pages, 60 bool realmode); 61 62 __be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc); 63 #endif 64 void (*clear)(struct iommu_table *tbl, 65 long index, long npages); 66 /* get() returns a physical address */ 67 unsigned long (*get)(struct iommu_table *tbl, long index); 68 void (*flush)(struct iommu_table *tbl); 69 void (*free)(struct iommu_table *tbl); 70 }; 71 72 /* These are used by VIO */ 73 extern struct iommu_table_ops iommu_table_lpar_multi_ops; 74 extern struct iommu_table_ops iommu_table_pseries_ops; 75 76 /* 77 * IOMAP_MAX_ORDER defines the largest contiguous block 78 * of dma space we can get. IOMAP_MAX_ORDER = 13 79 * allows up to 2**12 pages (4096 * 4096) = 16 MB 80 */ 81 #define IOMAP_MAX_ORDER 13 82 83 #define IOMMU_POOL_HASHBITS 2 84 #define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS) 85 86 struct iommu_pool { 87 unsigned long start; 88 unsigned long end; 89 unsigned long hint; 90 spinlock_t lock; 91 } ____cacheline_aligned_in_smp; 92 93 struct iommu_table { 94 unsigned long it_busno; /* Bus number this table belongs to */ 95 unsigned long it_size; /* Size of iommu table in entries */ 96 unsigned long it_indirect_levels; 97 unsigned long it_level_size; 98 unsigned long it_allocated_size; 99 unsigned long it_offset; /* Offset into global table */ 100 unsigned long it_base; /* mapped address of tce table */ 101 unsigned long it_index; /* which iommu table this is */ 102 unsigned long it_type; /* type: PCI or Virtual Bus */ 103 unsigned long it_blocksize; /* Entries in each block (cacheline) */ 104 unsigned long poolsize; 105 unsigned long nr_pools; 106 struct iommu_pool large_pool; 107 struct iommu_pool pools[IOMMU_NR_POOLS]; 108 unsigned long *it_map; /* A simple allocation bitmap for now */ 109 unsigned long it_page_shift;/* table iommu page size */ 110 struct list_head it_group_list;/* List of iommu_table_group_link */ 111 __be64 *it_userspace; /* userspace view of the table */ 112 struct iommu_table_ops *it_ops; 113 struct kref it_kref; 114 int it_nid; 115 unsigned long it_reserved_start; /* Start of not-DMA-able (MMIO) area */ 116 unsigned long it_reserved_end; 117 }; 118 119 #define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \ 120 ((tbl)->it_ops->useraddrptr((tbl), (entry), false)) 121 #define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \ 122 ((tbl)->it_ops->useraddrptr((tbl), (entry), true)) 123 124 /* Pure 2^n version of get_order */ 125 static inline __attribute_const__ 126 int get_iommu_order(unsigned long size, struct iommu_table *tbl) 127 { 128 return __ilog2((size - 1) >> tbl->it_page_shift) + 1; 129 } 130 131 132 struct scatterlist; 133 134 #ifdef CONFIG_PPC64 135 136 static inline void set_iommu_table_base(struct device *dev, 137 struct iommu_table *base) 138 { 139 dev->archdata.iommu_table_base = base; 140 } 141 142 static inline void *get_iommu_table_base(struct device *dev) 143 { 144 return dev->archdata.iommu_table_base; 145 } 146 147 extern int dma_iommu_dma_supported(struct device *dev, u64 mask); 148 149 extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl); 150 extern int iommu_tce_table_put(struct iommu_table *tbl); 151 152 /* Initializes an iommu_table based in values set in the passed-in 153 * structure 154 */ 155 extern struct iommu_table *iommu_init_table(struct iommu_table *tbl, 156 int nid, unsigned long res_start, unsigned long res_end); 157 bool iommu_table_in_use(struct iommu_table *tbl); 158 159 #define IOMMU_TABLE_GROUP_MAX_TABLES 2 160 161 struct iommu_table_group; 162 163 struct iommu_table_group_ops { 164 unsigned long (*get_table_size)( 165 __u32 page_shift, 166 __u64 window_size, 167 __u32 levels); 168 long (*create_table)(struct iommu_table_group *table_group, 169 int num, 170 __u32 page_shift, 171 __u64 window_size, 172 __u32 levels, 173 struct iommu_table **ptbl); 174 long (*set_window)(struct iommu_table_group *table_group, 175 int num, 176 struct iommu_table *tblnew); 177 long (*unset_window)(struct iommu_table_group *table_group, 178 int num); 179 /* Switch ownership from platform code to external user (e.g. VFIO) */ 180 void (*take_ownership)(struct iommu_table_group *table_group); 181 /* Switch ownership from external user (e.g. VFIO) back to core */ 182 void (*release_ownership)(struct iommu_table_group *table_group); 183 }; 184 185 struct iommu_table_group_link { 186 struct list_head next; 187 struct rcu_head rcu; 188 struct iommu_table_group *table_group; 189 }; 190 191 struct iommu_table_group { 192 /* IOMMU properties */ 193 __u32 tce32_start; 194 __u32 tce32_size; 195 __u64 pgsizes; /* Bitmap of supported page sizes */ 196 __u32 max_dynamic_windows_supported; 197 __u32 max_levels; 198 199 struct iommu_group *group; 200 struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES]; 201 struct iommu_table_group_ops *ops; 202 }; 203 204 #ifdef CONFIG_IOMMU_API 205 206 extern void iommu_register_group(struct iommu_table_group *table_group, 207 int pci_domain_number, unsigned long pe_num); 208 extern int iommu_add_device(struct iommu_table_group *table_group, 209 struct device *dev); 210 extern void iommu_del_device(struct device *dev); 211 extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl, 212 unsigned long entry, unsigned long *hpa, 213 enum dma_data_direction *direction); 214 extern long iommu_tce_xchg_no_kill(struct mm_struct *mm, 215 struct iommu_table *tbl, 216 unsigned long entry, unsigned long *hpa, 217 enum dma_data_direction *direction); 218 extern void iommu_tce_kill(struct iommu_table *tbl, 219 unsigned long entry, unsigned long pages); 220 #else 221 static inline void iommu_register_group(struct iommu_table_group *table_group, 222 int pci_domain_number, 223 unsigned long pe_num) 224 { 225 } 226 227 static inline int iommu_add_device(struct iommu_table_group *table_group, 228 struct device *dev) 229 { 230 return 0; 231 } 232 233 static inline void iommu_del_device(struct device *dev) 234 { 235 } 236 #endif /* !CONFIG_IOMMU_API */ 237 238 u64 dma_iommu_get_required_mask(struct device *dev); 239 #else 240 241 static inline void *get_iommu_table_base(struct device *dev) 242 { 243 return NULL; 244 } 245 246 static inline int dma_iommu_dma_supported(struct device *dev, u64 mask) 247 { 248 return 0; 249 } 250 251 #endif /* CONFIG_PPC64 */ 252 253 extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl, 254 struct scatterlist *sglist, int nelems, 255 unsigned long mask, 256 enum dma_data_direction direction, 257 unsigned long attrs); 258 extern void ppc_iommu_unmap_sg(struct iommu_table *tbl, 259 struct scatterlist *sglist, 260 int nelems, 261 enum dma_data_direction direction, 262 unsigned long attrs); 263 264 extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl, 265 size_t size, dma_addr_t *dma_handle, 266 unsigned long mask, gfp_t flag, int node); 267 extern void iommu_free_coherent(struct iommu_table *tbl, size_t size, 268 void *vaddr, dma_addr_t dma_handle); 269 extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl, 270 struct page *page, unsigned long offset, 271 size_t size, unsigned long mask, 272 enum dma_data_direction direction, 273 unsigned long attrs); 274 extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle, 275 size_t size, enum dma_data_direction direction, 276 unsigned long attrs); 277 278 extern void iommu_init_early_pSeries(void); 279 extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops); 280 extern void iommu_init_early_pasemi(void); 281 282 #if defined(CONFIG_PPC64) && defined(CONFIG_PM) 283 static inline void iommu_save(void) 284 { 285 if (ppc_md.iommu_save) 286 ppc_md.iommu_save(); 287 } 288 289 static inline void iommu_restore(void) 290 { 291 if (ppc_md.iommu_restore) 292 ppc_md.iommu_restore(); 293 } 294 #endif 295 296 /* The API to support IOMMU operations for VFIO */ 297 extern int iommu_tce_check_ioba(unsigned long page_shift, 298 unsigned long offset, unsigned long size, 299 unsigned long ioba, unsigned long npages); 300 extern int iommu_tce_check_gpa(unsigned long page_shift, 301 unsigned long gpa); 302 303 #define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \ 304 (iommu_tce_check_ioba((tbl)->it_page_shift, \ 305 (tbl)->it_offset, (tbl)->it_size, \ 306 (ioba), (npages)) || (tce_value)) 307 #define iommu_tce_put_param_check(tbl, ioba, gpa) \ 308 (iommu_tce_check_ioba((tbl)->it_page_shift, \ 309 (tbl)->it_offset, (tbl)->it_size, \ 310 (ioba), 1) || \ 311 iommu_tce_check_gpa((tbl)->it_page_shift, (gpa))) 312 313 extern void iommu_flush_tce(struct iommu_table *tbl); 314 extern int iommu_take_ownership(struct iommu_table *tbl); 315 extern void iommu_release_ownership(struct iommu_table *tbl); 316 317 extern enum dma_data_direction iommu_tce_direction(unsigned long tce); 318 extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir); 319 320 #ifdef CONFIG_PPC_CELL_NATIVE 321 extern bool iommu_fixed_is_weak; 322 #else 323 #define iommu_fixed_is_weak false 324 #endif 325 326 extern const struct dma_map_ops dma_iommu_ops; 327 328 #endif /* __KERNEL__ */ 329 #endif /* _ASM_IOMMU_H */ 330