1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 7 /* 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20 extern struct pci_dev *isa_bridge_pcidev; 21 /* 22 * has legacy ISA devices ? 23 */ 24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL) 25 #endif 26 27 #include <linux/device.h> 28 #include <linux/io.h> 29 30 #include <linux/compiler.h> 31 #include <asm/page.h> 32 #include <asm/byteorder.h> 33 #include <asm/synch.h> 34 #include <asm/delay.h> 35 #include <asm/mmu.h> 36 37 #include <asm-generic/iomap.h> 38 39 #ifdef CONFIG_PPC64 40 #include <asm/paca.h> 41 #endif 42 43 #define SIO_CONFIG_RA 0x398 44 #define SIO_CONFIG_RD 0x399 45 46 #define SLOW_DOWN_IO 47 48 /* 32 bits uses slightly different variables for the various IO 49 * bases. Most of this file only uses _IO_BASE though which we 50 * define properly based on the platform 51 */ 52 #ifndef CONFIG_PCI 53 #define _IO_BASE 0 54 #define _ISA_MEM_BASE 0 55 #define PCI_DRAM_OFFSET 0 56 #elif defined(CONFIG_PPC32) 57 #define _IO_BASE isa_io_base 58 #define _ISA_MEM_BASE isa_mem_base 59 #define PCI_DRAM_OFFSET pci_dram_offset 60 #else 61 #define _IO_BASE pci_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET 0 64 #endif 65 66 extern unsigned long isa_io_base; 67 extern unsigned long pci_io_base; 68 extern unsigned long pci_dram_offset; 69 70 extern resource_size_t isa_mem_base; 71 72 #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) 73 #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits 74 #endif 75 76 /* 77 * 78 * Low level MMIO accessors 79 * 80 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 81 * specific and thus shouldn't be used in generic code. The accessors 82 * provided here are: 83 * 84 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 85 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 86 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 87 * 88 * Those operate directly on a kernel virtual address. Note that the prototype 89 * for the out_* accessors has the arguments in opposite order from the usual 90 * linux PCI accessors. Unlike those, they take the address first and the value 91 * next. 92 * 93 * Note: I might drop the _ns suffix on the stream operations soon as it is 94 * simply normal for stream operations to not swap in the first place. 95 * 96 */ 97 98 #ifdef CONFIG_PPC64 99 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 100 #else 101 #define IO_SET_SYNC_FLAG() 102 #endif 103 104 /* gcc 4.0 and older doesn't have 'Z' constraint */ 105 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) 106 #define DEF_MMIO_IN_LE(name, size, insn) \ 107 static inline u##size name(const volatile u##size __iomem *addr) \ 108 { \ 109 u##size ret; \ 110 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ 111 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ 112 return ret; \ 113 } 114 115 #define DEF_MMIO_OUT_LE(name, size, insn) \ 116 static inline void name(volatile u##size __iomem *addr, u##size val) \ 117 { \ 118 __asm__ __volatile__("sync;"#insn" %1,0,%2" \ 119 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ 120 IO_SET_SYNC_FLAG(); \ 121 } 122 #else /* newer gcc */ 123 #define DEF_MMIO_IN_LE(name, size, insn) \ 124 static inline u##size name(const volatile u##size __iomem *addr) \ 125 { \ 126 u##size ret; \ 127 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 128 : "=r" (ret) : "Z" (*addr) : "memory"); \ 129 return ret; \ 130 } 131 132 #define DEF_MMIO_OUT_LE(name, size, insn) \ 133 static inline void name(volatile u##size __iomem *addr, u##size val) \ 134 { \ 135 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 136 : "=Z" (*addr) : "r" (val) : "memory"); \ 137 IO_SET_SYNC_FLAG(); \ 138 } 139 #endif 140 141 #define DEF_MMIO_IN_BE(name, size, insn) \ 142 static inline u##size name(const volatile u##size __iomem *addr) \ 143 { \ 144 u##size ret; \ 145 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 146 : "=r" (ret) : "m" (*addr) : "memory"); \ 147 return ret; \ 148 } 149 150 #define DEF_MMIO_OUT_BE(name, size, insn) \ 151 static inline void name(volatile u##size __iomem *addr, u##size val) \ 152 { \ 153 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 154 : "=m" (*addr) : "r" (val) : "memory"); \ 155 IO_SET_SYNC_FLAG(); \ 156 } 157 158 159 DEF_MMIO_IN_BE(in_8, 8, lbz); 160 DEF_MMIO_IN_BE(in_be16, 16, lhz); 161 DEF_MMIO_IN_BE(in_be32, 32, lwz); 162 DEF_MMIO_IN_LE(in_le16, 16, lhbrx); 163 DEF_MMIO_IN_LE(in_le32, 32, lwbrx); 164 165 DEF_MMIO_OUT_BE(out_8, 8, stb); 166 DEF_MMIO_OUT_BE(out_be16, 16, sth); 167 DEF_MMIO_OUT_BE(out_be32, 32, stw); 168 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); 169 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); 170 171 #ifdef __powerpc64__ 172 DEF_MMIO_OUT_BE(out_be64, 64, std); 173 DEF_MMIO_IN_BE(in_be64, 64, ld); 174 175 /* There is no asm instructions for 64 bits reverse loads and stores */ 176 static inline u64 in_le64(const volatile u64 __iomem *addr) 177 { 178 return swab64(in_be64(addr)); 179 } 180 181 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 182 { 183 out_be64(addr, swab64(val)); 184 } 185 #endif /* __powerpc64__ */ 186 187 /* 188 * Low level IO stream instructions are defined out of line for now 189 */ 190 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 191 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 192 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 193 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 194 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 195 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 196 197 /* The _ns naming is historical and will be removed. For now, just #define 198 * the non _ns equivalent names 199 */ 200 #define _insw _insw_ns 201 #define _insl _insl_ns 202 #define _outsw _outsw_ns 203 #define _outsl _outsl_ns 204 205 206 /* 207 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 208 */ 209 210 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 211 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 212 unsigned long n); 213 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 214 unsigned long n); 215 216 /* 217 * 218 * PCI and standard ISA accessors 219 * 220 * Those are globally defined linux accessors for devices on PCI or ISA 221 * busses. They follow the Linux defined semantics. The current implementation 222 * for PowerPC is as close as possible to the x86 version of these, and thus 223 * provides fairly heavy weight barriers for the non-raw versions 224 * 225 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO 226 * allowing the platform to provide its own implementation of some or all 227 * of the accessors. 228 */ 229 230 /* 231 * Include the EEH definitions when EEH is enabled only so they don't get 232 * in the way when building for 32 bits 233 */ 234 #ifdef CONFIG_EEH 235 #include <asm/eeh.h> 236 #endif 237 238 /* Shortcut to the MMIO argument pointer */ 239 #define PCI_IO_ADDR volatile void __iomem * 240 241 /* Indirect IO address tokens: 242 * 243 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks 244 * on all IOs. (Note that this is all 64 bits only for now) 245 * 246 * To help platforms who may need to differenciate MMIO addresses in 247 * their hooks, a bitfield is reserved for use by the platform near the 248 * top of MMIO addresses (not PIO, those have to cope the hard way). 249 * 250 * This bit field is 12 bits and is at the top of the IO virtual 251 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 252 * 253 * The kernel virtual space is thus: 254 * 255 * 0xD000000000000000 : vmalloc 256 * 0xD000080000000000 : PCI PHB IO space 257 * 0xD000080080000000 : ioremap 258 * 0xD0000fffffffffff : end of ioremap region 259 * 260 * Since the top 4 bits are reserved as the region ID, we use thus 261 * the next 12 bits and keep 4 bits available for the future if the 262 * virtual address space is ever to be extended. 263 * 264 * The direct IO mapping operations will then mask off those bits 265 * before doing the actual access, though that only happen when 266 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that 267 * mechanism 268 */ 269 270 #ifdef CONFIG_PPC_INDIRECT_IO 271 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 272 #define PCI_IO_IND_TOKEN_SHIFT 48 273 #define PCI_FIX_ADDR(addr) \ 274 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 275 #define PCI_GET_ADDR_TOKEN(addr) \ 276 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 277 PCI_IO_IND_TOKEN_SHIFT) 278 #define PCI_SET_ADDR_TOKEN(addr, token) \ 279 do { \ 280 unsigned long __a = (unsigned long)(addr); \ 281 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 282 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 283 (addr) = (void __iomem *)__a; \ 284 } while(0) 285 #else 286 #define PCI_FIX_ADDR(addr) (addr) 287 #endif 288 289 290 /* 291 * Non ordered and non-swapping "raw" accessors 292 */ 293 294 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 295 { 296 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 297 } 298 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 299 { 300 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 301 } 302 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 303 { 304 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 305 } 306 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 307 { 308 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 309 } 310 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 311 { 312 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 313 } 314 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 315 { 316 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 317 } 318 319 #ifdef __powerpc64__ 320 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 321 { 322 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 323 } 324 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 325 { 326 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 327 } 328 #endif /* __powerpc64__ */ 329 330 /* 331 * 332 * PCI PIO and MMIO accessors. 333 * 334 * 335 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 336 * machine checks (which they occasionally do when probing non existing 337 * IO ports on some platforms, like PowerMac and 8xx). 338 * I always found it to be of dubious reliability and I am tempted to get 339 * rid of it one of these days. So if you think it's important to keep it, 340 * please voice up asap. We never had it for 64 bits and I do not intend 341 * to port it over 342 */ 343 344 #ifdef CONFIG_PPC32 345 346 #define __do_in_asm(name, op) \ 347 static inline unsigned int name(unsigned int port) \ 348 { \ 349 unsigned int x; \ 350 __asm__ __volatile__( \ 351 "sync\n" \ 352 "0:" op " %0,0,%1\n" \ 353 "1: twi 0,%0,0\n" \ 354 "2: isync\n" \ 355 "3: nop\n" \ 356 "4:\n" \ 357 ".section .fixup,\"ax\"\n" \ 358 "5: li %0,-1\n" \ 359 " b 4b\n" \ 360 ".previous\n" \ 361 ".section __ex_table,\"a\"\n" \ 362 " .align 2\n" \ 363 " .long 0b,5b\n" \ 364 " .long 1b,5b\n" \ 365 " .long 2b,5b\n" \ 366 " .long 3b,5b\n" \ 367 ".previous" \ 368 : "=&r" (x) \ 369 : "r" (port + _IO_BASE) \ 370 : "memory"); \ 371 return x; \ 372 } 373 374 #define __do_out_asm(name, op) \ 375 static inline void name(unsigned int val, unsigned int port) \ 376 { \ 377 __asm__ __volatile__( \ 378 "sync\n" \ 379 "0:" op " %0,0,%1\n" \ 380 "1: sync\n" \ 381 "2:\n" \ 382 ".section __ex_table,\"a\"\n" \ 383 " .align 2\n" \ 384 " .long 0b,2b\n" \ 385 " .long 1b,2b\n" \ 386 ".previous" \ 387 : : "r" (val), "r" (port + _IO_BASE) \ 388 : "memory"); \ 389 } 390 391 __do_in_asm(_rec_inb, "lbzx") 392 __do_in_asm(_rec_inw, "lhbrx") 393 __do_in_asm(_rec_inl, "lwbrx") 394 __do_out_asm(_rec_outb, "stbx") 395 __do_out_asm(_rec_outw, "sthbrx") 396 __do_out_asm(_rec_outl, "stwbrx") 397 398 #endif /* CONFIG_PPC32 */ 399 400 /* The "__do_*" operations below provide the actual "base" implementation 401 * for each of the defined accessors. Some of them use the out_* functions 402 * directly, some of them still use EEH, though we might change that in the 403 * future. Those macros below provide the necessary argument swapping and 404 * handling of the IO base for PIO. 405 * 406 * They are themselves used by the macros that define the actual accessors 407 * and can be used by the hooks if any. 408 * 409 * Note that PIO operations are always defined in terms of their corresonding 410 * MMIO operations. That allows platforms like iSeries who want to modify the 411 * behaviour of both to only hook on the MMIO version and get both. It's also 412 * possible to hook directly at the toplevel PIO operation if they have to 413 * be handled differently 414 */ 415 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 416 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 417 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 418 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 419 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 420 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 421 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 422 423 #ifdef CONFIG_EEH 424 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 425 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 426 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 427 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 428 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 429 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 430 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 431 #else /* CONFIG_EEH */ 432 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 433 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 434 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 435 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 436 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 437 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 438 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 439 #endif /* !defined(CONFIG_EEH) */ 440 441 #ifdef CONFIG_PPC32 442 #define __do_outb(val, port) _rec_outb(val, port) 443 #define __do_outw(val, port) _rec_outw(val, port) 444 #define __do_outl(val, port) _rec_outl(val, port) 445 #define __do_inb(port) _rec_inb(port) 446 #define __do_inw(port) _rec_inw(port) 447 #define __do_inl(port) _rec_inl(port) 448 #else /* CONFIG_PPC32 */ 449 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 450 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 451 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 452 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 453 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 454 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 455 #endif /* !CONFIG_PPC32 */ 456 457 #ifdef CONFIG_EEH 458 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 459 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 460 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 461 #else /* CONFIG_EEH */ 462 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 463 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 464 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 465 #endif /* !CONFIG_EEH */ 466 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 467 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 468 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 469 470 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 471 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 472 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 473 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 474 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 475 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 476 477 #define __do_memset_io(addr, c, n) \ 478 _memset_io(PCI_FIX_ADDR(addr), c, n) 479 #define __do_memcpy_toio(dst, src, n) \ 480 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 481 482 #ifdef CONFIG_EEH 483 #define __do_memcpy_fromio(dst, src, n) \ 484 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 485 #else /* CONFIG_EEH */ 486 #define __do_memcpy_fromio(dst, src, n) \ 487 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 488 #endif /* !CONFIG_EEH */ 489 490 #ifdef CONFIG_PPC_INDIRECT_PIO 491 #define DEF_PCI_HOOK_pio(x) x 492 #else 493 #define DEF_PCI_HOOK_pio(x) NULL 494 #endif 495 496 #ifdef CONFIG_PPC_INDIRECT_MMIO 497 #define DEF_PCI_HOOK_mem(x) x 498 #else 499 #define DEF_PCI_HOOK_mem(x) NULL 500 #endif 501 502 /* Structure containing all the hooks */ 503 extern struct ppc_pci_io { 504 505 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 506 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 507 508 #include <asm/io-defs.h> 509 510 #undef DEF_PCI_AC_RET 511 #undef DEF_PCI_AC_NORET 512 513 } ppc_pci_io; 514 515 /* The inline wrappers */ 516 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 517 static inline ret name at \ 518 { \ 519 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 520 return ppc_pci_io.name al; \ 521 return __do_##name al; \ 522 } 523 524 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 525 static inline void name at \ 526 { \ 527 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 528 ppc_pci_io.name al; \ 529 else \ 530 __do_##name al; \ 531 } 532 533 #include <asm/io-defs.h> 534 535 #undef DEF_PCI_AC_RET 536 #undef DEF_PCI_AC_NORET 537 538 /* Some drivers check for the presence of readq & writeq with 539 * a #ifdef, so we make them happy here. 540 */ 541 #ifdef __powerpc64__ 542 #define readq readq 543 #define writeq writeq 544 #endif 545 546 /* 547 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 548 * access 549 */ 550 #define xlate_dev_mem_ptr(p) __va(p) 551 552 /* 553 * Convert a virtual cached pointer to an uncached pointer 554 */ 555 #define xlate_dev_kmem_ptr(p) p 556 557 /* 558 * We don't do relaxed operations yet, at least not with this semantic 559 */ 560 #define readb_relaxed(addr) readb(addr) 561 #define readw_relaxed(addr) readw(addr) 562 #define readl_relaxed(addr) readl(addr) 563 #define readq_relaxed(addr) readq(addr) 564 565 #ifdef CONFIG_PPC32 566 #define mmiowb() 567 #else 568 /* 569 * Enforce synchronisation of stores vs. spin_unlock 570 * (this does it explicitly, though our implementation of spin_unlock 571 * does it implicitely too) 572 */ 573 static inline void mmiowb(void) 574 { 575 unsigned long tmp; 576 577 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 578 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 579 : "memory"); 580 } 581 #endif /* !CONFIG_PPC32 */ 582 583 static inline void iosync(void) 584 { 585 __asm__ __volatile__ ("sync" : : : "memory"); 586 } 587 588 /* Enforce in-order execution of data I/O. 589 * No distinction between read/write on PPC; use eieio for all three. 590 * Those are fairly week though. They don't provide a barrier between 591 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 592 * they only provide barriers between 2 __raw MMIO operations and 593 * possibly break write combining. 594 */ 595 #define iobarrier_rw() eieio() 596 #define iobarrier_r() eieio() 597 #define iobarrier_w() eieio() 598 599 600 /* 601 * output pause versions need a delay at least for the 602 * w83c105 ide controller in a p610. 603 */ 604 #define inb_p(port) inb(port) 605 #define outb_p(val, port) (udelay(1), outb((val), (port))) 606 #define inw_p(port) inw(port) 607 #define outw_p(val, port) (udelay(1), outw((val), (port))) 608 #define inl_p(port) inl(port) 609 #define outl_p(val, port) (udelay(1), outl((val), (port))) 610 611 612 #define IO_SPACE_LIMIT ~(0UL) 613 614 615 /** 616 * ioremap - map bus memory into CPU space 617 * @address: bus address of the memory 618 * @size: size of the resource to map 619 * 620 * ioremap performs a platform specific sequence of operations to 621 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 622 * writew/writel functions and the other mmio helpers. The returned 623 * address is not guaranteed to be usable directly as a virtual 624 * address. 625 * 626 * We provide a few variations of it: 627 * 628 * * ioremap is the standard one and provides non-cacheable guarded mappings 629 * and can be hooked by the platform via ppc_md 630 * 631 * * ioremap_prot allows to specify the page flags as an argument and can 632 * also be hooked by the platform via ppc_md. 633 * 634 * * ioremap_nocache is identical to ioremap 635 * 636 * * ioremap_wc enables write combining 637 * 638 * * iounmap undoes such a mapping and can be hooked 639 * 640 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 641 * create hand-made mappings for use only by the PCI code and cannot 642 * currently be hooked. Must be page aligned. 643 * 644 * * __ioremap is the low level implementation used by ioremap and 645 * ioremap_prot and cannot be hooked (but can be used by a hook on one 646 * of the previous ones) 647 * 648 * * __ioremap_caller is the same as above but takes an explicit caller 649 * reference rather than using __builtin_return_address(0) 650 * 651 * * __iounmap, is the low level implementation used by iounmap and cannot 652 * be hooked (but can be used by a hook on iounmap) 653 * 654 */ 655 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 656 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 657 unsigned long flags); 658 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 659 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 660 661 extern void iounmap(volatile void __iomem *addr); 662 663 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 664 unsigned long flags); 665 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 666 unsigned long flags, void *caller); 667 668 extern void __iounmap(volatile void __iomem *addr); 669 670 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 671 unsigned long size, unsigned long flags); 672 extern void __iounmap_at(void *ea, unsigned long size); 673 674 /* 675 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation 676 * which needs some additional definitions here. They basically allow PIO 677 * space overall to be 1GB. This will work as long as we never try to use 678 * iomap to map MMIO below 1GB which should be fine on ppc64 679 */ 680 #define HAVE_ARCH_PIO_SIZE 1 681 #define PIO_OFFSET 0x00000000UL 682 #define PIO_MASK (FULL_IO_SIZE - 1) 683 #define PIO_RESERVED (FULL_IO_SIZE) 684 685 #define mmio_read16be(addr) readw_be(addr) 686 #define mmio_read32be(addr) readl_be(addr) 687 #define mmio_write16be(val, addr) writew_be(val, addr) 688 #define mmio_write32be(val, addr) writel_be(val, addr) 689 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 690 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 691 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 692 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 693 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 694 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 695 696 /** 697 * virt_to_phys - map virtual addresses to physical 698 * @address: address to remap 699 * 700 * The returned physical address is the physical (CPU) mapping for 701 * the memory address given. It is only valid to use this function on 702 * addresses directly mapped or allocated via kmalloc. 703 * 704 * This function does not give bus mappings for DMA transfers. In 705 * almost all conceivable cases a device driver should not be using 706 * this function 707 */ 708 static inline unsigned long virt_to_phys(volatile void * address) 709 { 710 return __pa((unsigned long)address); 711 } 712 713 /** 714 * phys_to_virt - map physical address to virtual 715 * @address: address to remap 716 * 717 * The returned virtual address is a current CPU mapping for 718 * the memory address given. It is only valid to use this function on 719 * addresses that have a kernel mapping 720 * 721 * This function does not handle bus mappings for DMA transfers. In 722 * almost all conceivable cases a device driver should not be using 723 * this function 724 */ 725 static inline void * phys_to_virt(unsigned long address) 726 { 727 return (void *)__va(address); 728 } 729 730 /* 731 * Change "struct page" to physical address. 732 */ 733 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 734 735 /* 736 * 32 bits still uses virt_to_bus() for it's implementation of DMA 737 * mappings se we have to keep it defined here. We also have some old 738 * drivers (shame shame shame) that use bus_to_virt() and haven't been 739 * fixed yet so I need to define it here. 740 */ 741 #ifdef CONFIG_PPC32 742 743 static inline unsigned long virt_to_bus(volatile void * address) 744 { 745 if (address == NULL) 746 return 0; 747 return __pa(address) + PCI_DRAM_OFFSET; 748 } 749 750 static inline void * bus_to_virt(unsigned long address) 751 { 752 if (address == 0) 753 return NULL; 754 return __va(address - PCI_DRAM_OFFSET); 755 } 756 757 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 758 759 #endif /* CONFIG_PPC32 */ 760 761 /* access ports */ 762 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 763 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 764 765 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 766 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 767 768 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 769 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 770 771 /* Clear and set bits in one shot. These macros can be used to clear and 772 * set multiple bits in a register using a single read-modify-write. These 773 * macros can also be used to set a multiple-bit bit pattern using a mask, 774 * by specifying the mask in the 'clear' parameter and the new bit pattern 775 * in the 'set' parameter. 776 */ 777 778 #define clrsetbits(type, addr, clear, set) \ 779 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 780 781 #ifdef __powerpc64__ 782 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 783 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 784 #endif 785 786 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 787 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 788 789 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 790 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 791 792 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 793 794 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset, 795 size_t size, unsigned long flags); 796 797 #endif /* __KERNEL__ */ 798 799 #endif /* _ASM_POWERPC_IO_H */ 800