1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 #ifndef _ASM_POWERPC_IO_H 3 #define _ASM_POWERPC_IO_H 4 #ifdef __KERNEL__ 5 6 #define ARCH_HAS_IOREMAP_WC 7 #ifdef CONFIG_PPC32 8 #define ARCH_HAS_IOREMAP_WT 9 #endif 10 11 /* 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 19 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 20 extern struct pci_dev *isa_bridge_pcidev; 21 /* 22 * has legacy ISA devices ? 23 */ 24 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special) 25 #endif 26 27 #include <linux/device.h> 28 #include <linux/compiler.h> 29 #include <linux/mm.h> 30 #include <asm/page.h> 31 #include <asm/byteorder.h> 32 #include <asm/synch.h> 33 #include <asm/delay.h> 34 #include <asm/mmiowb.h> 35 #include <asm/mmu.h> 36 #include <asm/ppc_asm.h> 37 38 #define SIO_CONFIG_RA 0x398 39 #define SIO_CONFIG_RD 0x399 40 41 #define SLOW_DOWN_IO 42 43 /* 32 bits uses slightly different variables for the various IO 44 * bases. Most of this file only uses _IO_BASE though which we 45 * define properly based on the platform 46 */ 47 #ifndef CONFIG_PCI 48 #define _IO_BASE 0 49 #define _ISA_MEM_BASE 0 50 #define PCI_DRAM_OFFSET 0 51 #elif defined(CONFIG_PPC32) 52 #define _IO_BASE isa_io_base 53 #define _ISA_MEM_BASE isa_mem_base 54 #define PCI_DRAM_OFFSET pci_dram_offset 55 #else 56 #define _IO_BASE pci_io_base 57 #define _ISA_MEM_BASE isa_mem_base 58 #define PCI_DRAM_OFFSET 0 59 #endif 60 61 extern unsigned long isa_io_base; 62 extern unsigned long pci_io_base; 63 extern unsigned long pci_dram_offset; 64 65 extern resource_size_t isa_mem_base; 66 67 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE 68 * is not set or addresses cannot be translated to MMIO. This is typically 69 * set when the platform supports "special" PIO accesses via a non memory 70 * mapped mechanism, and allows things like the early udbg UART code to 71 * function. 72 */ 73 extern bool isa_io_special; 74 75 #ifdef CONFIG_PPC32 76 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO) 77 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits 78 #endif 79 #endif 80 81 /* 82 * 83 * Low level MMIO accessors 84 * 85 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 86 * specific and thus shouldn't be used in generic code. The accessors 87 * provided here are: 88 * 89 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 90 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 91 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 92 * 93 * Those operate directly on a kernel virtual address. Note that the prototype 94 * for the out_* accessors has the arguments in opposite order from the usual 95 * linux PCI accessors. Unlike those, they take the address first and the value 96 * next. 97 * 98 * Note: I might drop the _ns suffix on the stream operations soon as it is 99 * simply normal for stream operations to not swap in the first place. 100 * 101 */ 102 103 #define DEF_MMIO_IN_X(name, size, insn) \ 104 static inline u##size name(const volatile u##size __iomem *addr) \ 105 { \ 106 u##size ret; \ 107 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 108 : "=r" (ret) : "Z" (*addr) : "memory"); \ 109 return ret; \ 110 } 111 112 #define DEF_MMIO_OUT_X(name, size, insn) \ 113 static inline void name(volatile u##size __iomem *addr, u##size val) \ 114 { \ 115 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 116 : "=Z" (*addr) : "r" (val) : "memory"); \ 117 mmiowb_set_pending(); \ 118 } 119 120 #define DEF_MMIO_IN_D(name, size, insn) \ 121 static inline u##size name(const volatile u##size __iomem *addr) \ 122 { \ 123 u##size ret; \ 124 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 125 : "=r" (ret) : "m<>" (*addr) : "memory"); \ 126 return ret; \ 127 } 128 129 #define DEF_MMIO_OUT_D(name, size, insn) \ 130 static inline void name(volatile u##size __iomem *addr, u##size val) \ 131 { \ 132 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 133 : "=m<>" (*addr) : "r" (val) : "memory"); \ 134 mmiowb_set_pending(); \ 135 } 136 137 DEF_MMIO_IN_D(in_8, 8, lbz); 138 DEF_MMIO_OUT_D(out_8, 8, stb); 139 140 #ifdef __BIG_ENDIAN__ 141 DEF_MMIO_IN_D(in_be16, 16, lhz); 142 DEF_MMIO_IN_D(in_be32, 32, lwz); 143 DEF_MMIO_IN_X(in_le16, 16, lhbrx); 144 DEF_MMIO_IN_X(in_le32, 32, lwbrx); 145 146 DEF_MMIO_OUT_D(out_be16, 16, sth); 147 DEF_MMIO_OUT_D(out_be32, 32, stw); 148 DEF_MMIO_OUT_X(out_le16, 16, sthbrx); 149 DEF_MMIO_OUT_X(out_le32, 32, stwbrx); 150 #else 151 DEF_MMIO_IN_X(in_be16, 16, lhbrx); 152 DEF_MMIO_IN_X(in_be32, 32, lwbrx); 153 DEF_MMIO_IN_D(in_le16, 16, lhz); 154 DEF_MMIO_IN_D(in_le32, 32, lwz); 155 156 DEF_MMIO_OUT_X(out_be16, 16, sthbrx); 157 DEF_MMIO_OUT_X(out_be32, 32, stwbrx); 158 DEF_MMIO_OUT_D(out_le16, 16, sth); 159 DEF_MMIO_OUT_D(out_le32, 32, stw); 160 161 #endif /* __BIG_ENDIAN */ 162 163 #ifdef __powerpc64__ 164 165 #ifdef __BIG_ENDIAN__ 166 DEF_MMIO_OUT_D(out_be64, 64, std); 167 DEF_MMIO_IN_D(in_be64, 64, ld); 168 169 /* There is no asm instructions for 64 bits reverse loads and stores */ 170 static inline u64 in_le64(const volatile u64 __iomem *addr) 171 { 172 return swab64(in_be64(addr)); 173 } 174 175 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 176 { 177 out_be64(addr, swab64(val)); 178 } 179 #else 180 DEF_MMIO_OUT_D(out_le64, 64, std); 181 DEF_MMIO_IN_D(in_le64, 64, ld); 182 183 /* There is no asm instructions for 64 bits reverse loads and stores */ 184 static inline u64 in_be64(const volatile u64 __iomem *addr) 185 { 186 return swab64(in_le64(addr)); 187 } 188 189 static inline void out_be64(volatile u64 __iomem *addr, u64 val) 190 { 191 out_le64(addr, swab64(val)); 192 } 193 194 #endif 195 #endif /* __powerpc64__ */ 196 197 /* 198 * Low level IO stream instructions are defined out of line for now 199 */ 200 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 201 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 202 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 203 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 204 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 205 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 206 207 /* The _ns naming is historical and will be removed. For now, just #define 208 * the non _ns equivalent names 209 */ 210 #define _insw _insw_ns 211 #define _insl _insl_ns 212 #define _outsw _outsw_ns 213 #define _outsl _outsl_ns 214 215 216 /* 217 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 218 */ 219 220 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 221 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 222 unsigned long n); 223 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 224 unsigned long n); 225 226 /* 227 * 228 * PCI and standard ISA accessors 229 * 230 * Those are globally defined linux accessors for devices on PCI or ISA 231 * busses. They follow the Linux defined semantics. The current implementation 232 * for PowerPC is as close as possible to the x86 version of these, and thus 233 * provides fairly heavy weight barriers for the non-raw versions 234 * 235 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO 236 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its 237 * own implementation of some or all of the accessors. 238 */ 239 240 /* 241 * Include the EEH definitions when EEH is enabled only so they don't get 242 * in the way when building for 32 bits 243 */ 244 #ifdef CONFIG_EEH 245 #include <asm/eeh.h> 246 #endif 247 248 /* Shortcut to the MMIO argument pointer */ 249 #define PCI_IO_ADDR volatile void __iomem * 250 251 /* Indirect IO address tokens: 252 * 253 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks 254 * on all MMIOs. (Note that this is all 64 bits only for now) 255 * 256 * To help platforms who may need to differentiate MMIO addresses in 257 * their hooks, a bitfield is reserved for use by the platform near the 258 * top of MMIO addresses (not PIO, those have to cope the hard way). 259 * 260 * The highest address in the kernel virtual space are: 261 * 262 * d0003fffffffffff # with Hash MMU 263 * c00fffffffffffff # with Radix MMU 264 * 265 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits 266 * that can be used for the field. 267 * 268 * The direct IO mapping operations will then mask off those bits 269 * before doing the actual access, though that only happen when 270 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that 271 * mechanism 272 * 273 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes 274 * all PIO functions call through a hook. 275 */ 276 277 #ifdef CONFIG_PPC_INDIRECT_MMIO 278 #define PCI_IO_IND_TOKEN_SHIFT 52 279 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT) 280 #define PCI_FIX_ADDR(addr) \ 281 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 282 #define PCI_GET_ADDR_TOKEN(addr) \ 283 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 284 PCI_IO_IND_TOKEN_SHIFT) 285 #define PCI_SET_ADDR_TOKEN(addr, token) \ 286 do { \ 287 unsigned long __a = (unsigned long)(addr); \ 288 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 289 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 290 (addr) = (void __iomem *)__a; \ 291 } while(0) 292 #else 293 #define PCI_FIX_ADDR(addr) (addr) 294 #endif 295 296 297 /* 298 * Non ordered and non-swapping "raw" accessors 299 */ 300 301 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 302 { 303 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 304 } 305 #define __raw_readb __raw_readb 306 307 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 308 { 309 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 310 } 311 #define __raw_readw __raw_readw 312 313 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 314 { 315 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 316 } 317 #define __raw_readl __raw_readl 318 319 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 320 { 321 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 322 } 323 #define __raw_writeb __raw_writeb 324 325 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 326 { 327 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 328 } 329 #define __raw_writew __raw_writew 330 331 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 332 { 333 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 334 } 335 #define __raw_writel __raw_writel 336 337 #ifdef __powerpc64__ 338 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 339 { 340 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 341 } 342 #define __raw_readq __raw_readq 343 344 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 345 { 346 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 347 } 348 #define __raw_writeq __raw_writeq 349 350 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr) 351 { 352 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr); 353 } 354 #define __raw_writeq_be __raw_writeq_be 355 356 /* 357 * Real mode versions of the above. Those instructions are only supposed 358 * to be used in hypervisor real mode as per the architecture spec. 359 */ 360 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr) 361 { 362 __asm__ __volatile__("stbcix %0,0,%1" 363 : : "r" (val), "r" (paddr) : "memory"); 364 } 365 366 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr) 367 { 368 __asm__ __volatile__("sthcix %0,0,%1" 369 : : "r" (val), "r" (paddr) : "memory"); 370 } 371 372 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr) 373 { 374 __asm__ __volatile__("stwcix %0,0,%1" 375 : : "r" (val), "r" (paddr) : "memory"); 376 } 377 378 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr) 379 { 380 __asm__ __volatile__("stdcix %0,0,%1" 381 : : "r" (val), "r" (paddr) : "memory"); 382 } 383 384 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr) 385 { 386 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr); 387 } 388 389 static inline u8 __raw_rm_readb(volatile void __iomem *paddr) 390 { 391 u8 ret; 392 __asm__ __volatile__("lbzcix %0,0, %1" 393 : "=r" (ret) : "r" (paddr) : "memory"); 394 return ret; 395 } 396 397 static inline u16 __raw_rm_readw(volatile void __iomem *paddr) 398 { 399 u16 ret; 400 __asm__ __volatile__("lhzcix %0,0, %1" 401 : "=r" (ret) : "r" (paddr) : "memory"); 402 return ret; 403 } 404 405 static inline u32 __raw_rm_readl(volatile void __iomem *paddr) 406 { 407 u32 ret; 408 __asm__ __volatile__("lwzcix %0,0, %1" 409 : "=r" (ret) : "r" (paddr) : "memory"); 410 return ret; 411 } 412 413 static inline u64 __raw_rm_readq(volatile void __iomem *paddr) 414 { 415 u64 ret; 416 __asm__ __volatile__("ldcix %0,0, %1" 417 : "=r" (ret) : "r" (paddr) : "memory"); 418 return ret; 419 } 420 #endif /* __powerpc64__ */ 421 422 /* 423 * 424 * PCI PIO and MMIO accessors. 425 * 426 * 427 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 428 * machine checks (which they occasionally do when probing non existing 429 * IO ports on some platforms, like PowerMac and 8xx). 430 * I always found it to be of dubious reliability and I am tempted to get 431 * rid of it one of these days. So if you think it's important to keep it, 432 * please voice up asap. We never had it for 64 bits and I do not intend 433 * to port it over 434 */ 435 436 #ifdef CONFIG_PPC32 437 438 #define __do_in_asm(name, op) \ 439 static inline unsigned int name(unsigned int port) \ 440 { \ 441 unsigned int x; \ 442 __asm__ __volatile__( \ 443 "sync\n" \ 444 "0:" op " %0,0,%1\n" \ 445 "1: twi 0,%0,0\n" \ 446 "2: isync\n" \ 447 "3: nop\n" \ 448 "4:\n" \ 449 ".section .fixup,\"ax\"\n" \ 450 "5: li %0,-1\n" \ 451 " b 4b\n" \ 452 ".previous\n" \ 453 EX_TABLE(0b, 5b) \ 454 EX_TABLE(1b, 5b) \ 455 EX_TABLE(2b, 5b) \ 456 EX_TABLE(3b, 5b) \ 457 : "=&r" (x) \ 458 : "r" (port + _IO_BASE) \ 459 : "memory"); \ 460 return x; \ 461 } 462 463 #define __do_out_asm(name, op) \ 464 static inline void name(unsigned int val, unsigned int port) \ 465 { \ 466 __asm__ __volatile__( \ 467 "sync\n" \ 468 "0:" op " %0,0,%1\n" \ 469 "1: sync\n" \ 470 "2:\n" \ 471 EX_TABLE(0b, 2b) \ 472 EX_TABLE(1b, 2b) \ 473 : : "r" (val), "r" (port + _IO_BASE) \ 474 : "memory"); \ 475 } 476 477 __do_in_asm(_rec_inb, "lbzx") 478 __do_in_asm(_rec_inw, "lhbrx") 479 __do_in_asm(_rec_inl, "lwbrx") 480 __do_out_asm(_rec_outb, "stbx") 481 __do_out_asm(_rec_outw, "sthbrx") 482 __do_out_asm(_rec_outl, "stwbrx") 483 484 #endif /* CONFIG_PPC32 */ 485 486 /* The "__do_*" operations below provide the actual "base" implementation 487 * for each of the defined accessors. Some of them use the out_* functions 488 * directly, some of them still use EEH, though we might change that in the 489 * future. Those macros below provide the necessary argument swapping and 490 * handling of the IO base for PIO. 491 * 492 * They are themselves used by the macros that define the actual accessors 493 * and can be used by the hooks if any. 494 * 495 * Note that PIO operations are always defined in terms of their corresonding 496 * MMIO operations. That allows platforms like iSeries who want to modify the 497 * behaviour of both to only hook on the MMIO version and get both. It's also 498 * possible to hook directly at the toplevel PIO operation if they have to 499 * be handled differently 500 */ 501 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 502 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 503 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 504 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 505 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 506 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 507 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 508 509 #ifdef CONFIG_EEH 510 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 511 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 512 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 513 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 514 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 515 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 516 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 517 #else /* CONFIG_EEH */ 518 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 519 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 520 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 521 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 522 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 523 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 524 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 525 #endif /* !defined(CONFIG_EEH) */ 526 527 #ifdef CONFIG_PPC32 528 #define __do_outb(val, port) _rec_outb(val, port) 529 #define __do_outw(val, port) _rec_outw(val, port) 530 #define __do_outl(val, port) _rec_outl(val, port) 531 #define __do_inb(port) _rec_inb(port) 532 #define __do_inw(port) _rec_inw(port) 533 #define __do_inl(port) _rec_inl(port) 534 #else /* CONFIG_PPC32 */ 535 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 536 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 537 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 538 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 539 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 540 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 541 #endif /* !CONFIG_PPC32 */ 542 543 #ifdef CONFIG_EEH 544 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 545 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 546 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 547 #else /* CONFIG_EEH */ 548 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 549 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 550 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 551 #endif /* !CONFIG_EEH */ 552 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 553 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 554 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 555 556 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 557 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 558 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 559 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 560 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 561 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 562 563 #define __do_memset_io(addr, c, n) \ 564 _memset_io(PCI_FIX_ADDR(addr), c, n) 565 #define __do_memcpy_toio(dst, src, n) \ 566 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 567 568 #ifdef CONFIG_EEH 569 #define __do_memcpy_fromio(dst, src, n) \ 570 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 571 #else /* CONFIG_EEH */ 572 #define __do_memcpy_fromio(dst, src, n) \ 573 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 574 #endif /* !CONFIG_EEH */ 575 576 #ifdef CONFIG_PPC_INDIRECT_PIO 577 #define DEF_PCI_HOOK_pio(x) x 578 #else 579 #define DEF_PCI_HOOK_pio(x) NULL 580 #endif 581 582 #ifdef CONFIG_PPC_INDIRECT_MMIO 583 #define DEF_PCI_HOOK_mem(x) x 584 #else 585 #define DEF_PCI_HOOK_mem(x) NULL 586 #endif 587 588 /* Structure containing all the hooks */ 589 extern struct ppc_pci_io { 590 591 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 592 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 593 594 #include <asm/io-defs.h> 595 596 #undef DEF_PCI_AC_RET 597 #undef DEF_PCI_AC_NORET 598 599 } ppc_pci_io; 600 601 /* The inline wrappers */ 602 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 603 static inline ret name at \ 604 { \ 605 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 606 return ppc_pci_io.name al; \ 607 return __do_##name al; \ 608 } 609 610 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 611 static inline void name at \ 612 { \ 613 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 614 ppc_pci_io.name al; \ 615 else \ 616 __do_##name al; \ 617 } 618 619 #include <asm/io-defs.h> 620 621 #undef DEF_PCI_AC_RET 622 #undef DEF_PCI_AC_NORET 623 624 /* Some drivers check for the presence of readq & writeq with 625 * a #ifdef, so we make them happy here. 626 */ 627 #define readb readb 628 #define readw readw 629 #define readl readl 630 #define writeb writeb 631 #define writew writew 632 #define writel writel 633 #define readsb readsb 634 #define readsw readsw 635 #define readsl readsl 636 #define writesb writesb 637 #define writesw writesw 638 #define writesl writesl 639 #define inb inb 640 #define inw inw 641 #define inl inl 642 #define outb outb 643 #define outw outw 644 #define outl outl 645 #define insb insb 646 #define insw insw 647 #define insl insl 648 #define outsb outsb 649 #define outsw outsw 650 #define outsl outsl 651 #ifdef __powerpc64__ 652 #define readq readq 653 #define writeq writeq 654 #endif 655 #define memset_io memset_io 656 #define memcpy_fromio memcpy_fromio 657 #define memcpy_toio memcpy_toio 658 659 /* 660 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 661 * access 662 */ 663 #define xlate_dev_mem_ptr(p) __va(p) 664 665 /* 666 * We don't do relaxed operations yet, at least not with this semantic 667 */ 668 #define readb_relaxed(addr) readb(addr) 669 #define readw_relaxed(addr) readw(addr) 670 #define readl_relaxed(addr) readl(addr) 671 #define readq_relaxed(addr) readq(addr) 672 #define writeb_relaxed(v, addr) writeb(v, addr) 673 #define writew_relaxed(v, addr) writew(v, addr) 674 #define writel_relaxed(v, addr) writel(v, addr) 675 #define writeq_relaxed(v, addr) writeq(v, addr) 676 677 #ifdef CONFIG_GENERIC_IOMAP 678 #include <asm-generic/iomap.h> 679 #else 680 /* 681 * Here comes the implementation of the IOMAP interfaces. 682 */ 683 static inline unsigned int ioread16be(const void __iomem *addr) 684 { 685 return readw_be(addr); 686 } 687 #define ioread16be ioread16be 688 689 static inline unsigned int ioread32be(const void __iomem *addr) 690 { 691 return readl_be(addr); 692 } 693 #define ioread32be ioread32be 694 695 #ifdef __powerpc64__ 696 static inline u64 ioread64_lo_hi(const void __iomem *addr) 697 { 698 return readq(addr); 699 } 700 #define ioread64_lo_hi ioread64_lo_hi 701 702 static inline u64 ioread64_hi_lo(const void __iomem *addr) 703 { 704 return readq(addr); 705 } 706 #define ioread64_hi_lo ioread64_hi_lo 707 708 static inline u64 ioread64be(const void __iomem *addr) 709 { 710 return readq_be(addr); 711 } 712 #define ioread64be ioread64be 713 714 static inline u64 ioread64be_lo_hi(const void __iomem *addr) 715 { 716 return readq_be(addr); 717 } 718 #define ioread64be_lo_hi ioread64be_lo_hi 719 720 static inline u64 ioread64be_hi_lo(const void __iomem *addr) 721 { 722 return readq_be(addr); 723 } 724 #define ioread64be_hi_lo ioread64be_hi_lo 725 #endif /* __powerpc64__ */ 726 727 static inline void iowrite16be(u16 val, void __iomem *addr) 728 { 729 writew_be(val, addr); 730 } 731 #define iowrite16be iowrite16be 732 733 static inline void iowrite32be(u32 val, void __iomem *addr) 734 { 735 writel_be(val, addr); 736 } 737 #define iowrite32be iowrite32be 738 739 #ifdef __powerpc64__ 740 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr) 741 { 742 writeq(val, addr); 743 } 744 #define iowrite64_lo_hi iowrite64_lo_hi 745 746 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr) 747 { 748 writeq(val, addr); 749 } 750 #define iowrite64_hi_lo iowrite64_hi_lo 751 752 static inline void iowrite64be(u64 val, void __iomem *addr) 753 { 754 writeq_be(val, addr); 755 } 756 #define iowrite64be iowrite64be 757 758 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr) 759 { 760 writeq_be(val, addr); 761 } 762 #define iowrite64be_lo_hi iowrite64be_lo_hi 763 764 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr) 765 { 766 writeq_be(val, addr); 767 } 768 #define iowrite64be_hi_lo iowrite64be_hi_lo 769 #endif /* __powerpc64__ */ 770 771 struct pci_dev; 772 void pci_iounmap(struct pci_dev *dev, void __iomem *addr); 773 #define pci_iounmap pci_iounmap 774 void __iomem *ioport_map(unsigned long port, unsigned int len); 775 #define ioport_map ioport_map 776 #endif 777 778 static inline void iosync(void) 779 { 780 __asm__ __volatile__ ("sync" : : : "memory"); 781 } 782 783 /* Enforce in-order execution of data I/O. 784 * No distinction between read/write on PPC; use eieio for all three. 785 * Those are fairly week though. They don't provide a barrier between 786 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 787 * they only provide barriers between 2 __raw MMIO operations and 788 * possibly break write combining. 789 */ 790 #define iobarrier_rw() eieio() 791 #define iobarrier_r() eieio() 792 #define iobarrier_w() eieio() 793 794 795 /* 796 * output pause versions need a delay at least for the 797 * w83c105 ide controller in a p610. 798 */ 799 #define inb_p(port) inb(port) 800 #define outb_p(val, port) (udelay(1), outb((val), (port))) 801 #define inw_p(port) inw(port) 802 #define outw_p(val, port) (udelay(1), outw((val), (port))) 803 #define inl_p(port) inl(port) 804 #define outl_p(val, port) (udelay(1), outl((val), (port))) 805 806 807 #define IO_SPACE_LIMIT ~(0UL) 808 809 /** 810 * ioremap - map bus memory into CPU space 811 * @address: bus address of the memory 812 * @size: size of the resource to map 813 * 814 * ioremap performs a platform specific sequence of operations to 815 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 816 * writew/writel functions and the other mmio helpers. The returned 817 * address is not guaranteed to be usable directly as a virtual 818 * address. 819 * 820 * We provide a few variations of it: 821 * 822 * * ioremap is the standard one and provides non-cacheable guarded mappings 823 * and can be hooked by the platform via ppc_md 824 * 825 * * ioremap_prot allows to specify the page flags as an argument and can 826 * also be hooked by the platform via ppc_md. 827 * 828 * * ioremap_wc enables write combining 829 * 830 * * ioremap_wt enables write through 831 * 832 * * ioremap_coherent maps coherent cached memory 833 * 834 * * iounmap undoes such a mapping and can be hooked 835 * 836 * * __ioremap_caller is the same as above but takes an explicit caller 837 * reference rather than using __builtin_return_address(0) 838 * 839 */ 840 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 841 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 842 unsigned long flags); 843 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 844 #define ioremap_wc ioremap_wc 845 846 #ifdef CONFIG_PPC32 847 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size); 848 #define ioremap_wt ioremap_wt 849 #endif 850 851 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size); 852 #define ioremap_uc(addr, size) ioremap((addr), (size)) 853 #define ioremap_cache(addr, size) \ 854 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL)) 855 856 extern void iounmap(volatile void __iomem *addr); 857 858 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size); 859 860 int early_ioremap_range(unsigned long ea, phys_addr_t pa, 861 unsigned long size, pgprot_t prot); 862 void __iomem *do_ioremap(phys_addr_t pa, phys_addr_t offset, unsigned long size, 863 pgprot_t prot, void *caller); 864 865 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 866 pgprot_t prot, void *caller); 867 868 /* 869 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation 870 * which needs some additional definitions here. They basically allow PIO 871 * space overall to be 1GB. This will work as long as we never try to use 872 * iomap to map MMIO below 1GB which should be fine on ppc64 873 */ 874 #define HAVE_ARCH_PIO_SIZE 1 875 #define PIO_OFFSET 0x00000000UL 876 #define PIO_MASK (FULL_IO_SIZE - 1) 877 #define PIO_RESERVED (FULL_IO_SIZE) 878 879 #define mmio_read16be(addr) readw_be(addr) 880 #define mmio_read32be(addr) readl_be(addr) 881 #define mmio_read64be(addr) readq_be(addr) 882 #define mmio_write16be(val, addr) writew_be(val, addr) 883 #define mmio_write32be(val, addr) writel_be(val, addr) 884 #define mmio_write64be(val, addr) writeq_be(val, addr) 885 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 886 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 887 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 888 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 889 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 890 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 891 892 /** 893 * virt_to_phys - map virtual addresses to physical 894 * @address: address to remap 895 * 896 * The returned physical address is the physical (CPU) mapping for 897 * the memory address given. It is only valid to use this function on 898 * addresses directly mapped or allocated via kmalloc. 899 * 900 * This function does not give bus mappings for DMA transfers. In 901 * almost all conceivable cases a device driver should not be using 902 * this function 903 */ 904 static inline unsigned long virt_to_phys(volatile void * address) 905 { 906 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address)); 907 908 return __pa((unsigned long)address); 909 } 910 #define virt_to_phys virt_to_phys 911 912 /** 913 * phys_to_virt - map physical address to virtual 914 * @address: address to remap 915 * 916 * The returned virtual address is a current CPU mapping for 917 * the memory address given. It is only valid to use this function on 918 * addresses that have a kernel mapping 919 * 920 * This function does not handle bus mappings for DMA transfers. In 921 * almost all conceivable cases a device driver should not be using 922 * this function 923 */ 924 static inline void * phys_to_virt(unsigned long address) 925 { 926 return (void *)__va(address); 927 } 928 #define phys_to_virt phys_to_virt 929 930 /* 931 * Change "struct page" to physical address. 932 */ 933 static inline phys_addr_t page_to_phys(struct page *page) 934 { 935 unsigned long pfn = page_to_pfn(page); 936 937 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn)); 938 939 return PFN_PHYS(pfn); 940 } 941 942 /* 943 * 32 bits still uses virt_to_bus() for it's implementation of DMA 944 * mappings se we have to keep it defined here. We also have some old 945 * drivers (shame shame shame) that use bus_to_virt() and haven't been 946 * fixed yet so I need to define it here. 947 */ 948 #ifdef CONFIG_PPC32 949 950 static inline unsigned long virt_to_bus(volatile void * address) 951 { 952 if (address == NULL) 953 return 0; 954 return __pa(address) + PCI_DRAM_OFFSET; 955 } 956 #define virt_to_bus virt_to_bus 957 958 static inline void * bus_to_virt(unsigned long address) 959 { 960 if (address == 0) 961 return NULL; 962 return __va(address - PCI_DRAM_OFFSET); 963 } 964 #define bus_to_virt bus_to_virt 965 966 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 967 968 #endif /* CONFIG_PPC32 */ 969 970 /* access ports */ 971 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 972 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 973 974 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 975 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 976 977 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 978 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 979 980 /* Clear and set bits in one shot. These macros can be used to clear and 981 * set multiple bits in a register using a single read-modify-write. These 982 * macros can also be used to set a multiple-bit bit pattern using a mask, 983 * by specifying the mask in the 'clear' parameter and the new bit pattern 984 * in the 'set' parameter. 985 */ 986 987 #define clrsetbits(type, addr, clear, set) \ 988 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 989 990 #ifdef __powerpc64__ 991 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 992 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 993 #endif 994 995 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 996 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 997 998 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 999 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 1000 1001 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 1002 1003 #include <asm-generic/io.h> 1004 1005 #endif /* __KERNEL__ */ 1006 1007 #endif /* _ASM_POWERPC_IO_H */ 1008