1 #ifndef _ASM_POWERPC_IO_H 2 #define _ASM_POWERPC_IO_H 3 #ifdef __KERNEL__ 4 5 #define ARCH_HAS_IOREMAP_WC 6 7 /* 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14 /* Check of existence of legacy devices */ 15 extern int check_legacy_ioport(unsigned long base_port); 16 #define I8042_DATA_REG 0x60 17 #define FDC_BASE 0x3f0 18 /* only relevant for PReP */ 19 #define _PIDXR 0x279 20 #define _PNPWRP 0xa79 21 #define PNPBIOS_BASE 0xf000 22 23 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI) 24 extern struct pci_dev *isa_bridge_pcidev; 25 /* 26 * has legacy ISA devices ? 27 */ 28 #define arch_has_dev_port() (isa_bridge_pcidev != NULL) 29 #endif 30 31 #include <linux/device.h> 32 #include <linux/io.h> 33 34 #include <linux/compiler.h> 35 #include <asm/page.h> 36 #include <asm/byteorder.h> 37 #include <asm/synch.h> 38 #include <asm/delay.h> 39 #include <asm/mmu.h> 40 41 #include <asm-generic/iomap.h> 42 43 #ifdef CONFIG_PPC64 44 #include <asm/paca.h> 45 #endif 46 47 #define SIO_CONFIG_RA 0x398 48 #define SIO_CONFIG_RD 0x399 49 50 #define SLOW_DOWN_IO 51 52 /* 32 bits uses slightly different variables for the various IO 53 * bases. Most of this file only uses _IO_BASE though which we 54 * define properly based on the platform 55 */ 56 #ifndef CONFIG_PCI 57 #define _IO_BASE 0 58 #define _ISA_MEM_BASE 0 59 #define PCI_DRAM_OFFSET 0 60 #elif defined(CONFIG_PPC32) 61 #define _IO_BASE isa_io_base 62 #define _ISA_MEM_BASE isa_mem_base 63 #define PCI_DRAM_OFFSET pci_dram_offset 64 #else 65 #define _IO_BASE pci_io_base 66 #define _ISA_MEM_BASE isa_mem_base 67 #define PCI_DRAM_OFFSET 0 68 #endif 69 70 extern unsigned long isa_io_base; 71 extern unsigned long pci_io_base; 72 extern unsigned long pci_dram_offset; 73 74 extern resource_size_t isa_mem_base; 75 76 #if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO) 77 #error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits 78 #endif 79 80 /* 81 * 82 * Low level MMIO accessors 83 * 84 * This provides the non-bus specific accessors to MMIO. Those are PowerPC 85 * specific and thus shouldn't be used in generic code. The accessors 86 * provided here are: 87 * 88 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64 89 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64 90 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns 91 * 92 * Those operate directly on a kernel virtual address. Note that the prototype 93 * for the out_* accessors has the arguments in opposite order from the usual 94 * linux PCI accessors. Unlike those, they take the address first and the value 95 * next. 96 * 97 * Note: I might drop the _ns suffix on the stream operations soon as it is 98 * simply normal for stream operations to not swap in the first place. 99 * 100 */ 101 102 #ifdef CONFIG_PPC64 103 #define IO_SET_SYNC_FLAG() do { local_paca->io_sync = 1; } while(0) 104 #else 105 #define IO_SET_SYNC_FLAG() 106 #endif 107 108 /* gcc 4.0 and older doesn't have 'Z' constraint */ 109 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0) 110 #define DEF_MMIO_IN_LE(name, size, insn) \ 111 static inline u##size name(const volatile u##size __iomem *addr) \ 112 { \ 113 u##size ret; \ 114 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \ 115 : "=r" (ret) : "r" (addr), "m" (*addr) : "memory"); \ 116 return ret; \ 117 } 118 119 #define DEF_MMIO_OUT_LE(name, size, insn) \ 120 static inline void name(volatile u##size __iomem *addr, u##size val) \ 121 { \ 122 __asm__ __volatile__("sync;"#insn" %1,0,%2" \ 123 : "=m" (*addr) : "r" (val), "r" (addr) : "memory"); \ 124 IO_SET_SYNC_FLAG(); \ 125 } 126 #else /* newer gcc */ 127 #define DEF_MMIO_IN_LE(name, size, insn) \ 128 static inline u##size name(const volatile u##size __iomem *addr) \ 129 { \ 130 u##size ret; \ 131 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \ 132 : "=r" (ret) : "Z" (*addr) : "memory"); \ 133 return ret; \ 134 } 135 136 #define DEF_MMIO_OUT_LE(name, size, insn) \ 137 static inline void name(volatile u##size __iomem *addr, u##size val) \ 138 { \ 139 __asm__ __volatile__("sync;"#insn" %1,%y0" \ 140 : "=Z" (*addr) : "r" (val) : "memory"); \ 141 IO_SET_SYNC_FLAG(); \ 142 } 143 #endif 144 145 #define DEF_MMIO_IN_BE(name, size, insn) \ 146 static inline u##size name(const volatile u##size __iomem *addr) \ 147 { \ 148 u##size ret; \ 149 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\ 150 : "=r" (ret) : "m" (*addr) : "memory"); \ 151 return ret; \ 152 } 153 154 #define DEF_MMIO_OUT_BE(name, size, insn) \ 155 static inline void name(volatile u##size __iomem *addr, u##size val) \ 156 { \ 157 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \ 158 : "=m" (*addr) : "r" (val) : "memory"); \ 159 IO_SET_SYNC_FLAG(); \ 160 } 161 162 163 DEF_MMIO_IN_BE(in_8, 8, lbz); 164 DEF_MMIO_IN_BE(in_be16, 16, lhz); 165 DEF_MMIO_IN_BE(in_be32, 32, lwz); 166 DEF_MMIO_IN_LE(in_le16, 16, lhbrx); 167 DEF_MMIO_IN_LE(in_le32, 32, lwbrx); 168 169 DEF_MMIO_OUT_BE(out_8, 8, stb); 170 DEF_MMIO_OUT_BE(out_be16, 16, sth); 171 DEF_MMIO_OUT_BE(out_be32, 32, stw); 172 DEF_MMIO_OUT_LE(out_le16, 16, sthbrx); 173 DEF_MMIO_OUT_LE(out_le32, 32, stwbrx); 174 175 #ifdef __powerpc64__ 176 DEF_MMIO_OUT_BE(out_be64, 64, std); 177 DEF_MMIO_IN_BE(in_be64, 64, ld); 178 179 /* There is no asm instructions for 64 bits reverse loads and stores */ 180 static inline u64 in_le64(const volatile u64 __iomem *addr) 181 { 182 return swab64(in_be64(addr)); 183 } 184 185 static inline void out_le64(volatile u64 __iomem *addr, u64 val) 186 { 187 out_be64(addr, swab64(val)); 188 } 189 #endif /* __powerpc64__ */ 190 191 /* 192 * Low level IO stream instructions are defined out of line for now 193 */ 194 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count); 195 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count); 196 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count); 197 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count); 198 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count); 199 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count); 200 201 /* The _ns naming is historical and will be removed. For now, just #define 202 * the non _ns equivalent names 203 */ 204 #define _insw _insw_ns 205 #define _insl _insl_ns 206 #define _outsw _outsw_ns 207 #define _outsl _outsl_ns 208 209 210 /* 211 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line 212 */ 213 214 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n); 215 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src, 216 unsigned long n); 217 extern void _memcpy_toio(volatile void __iomem *dest, const void *src, 218 unsigned long n); 219 220 /* 221 * 222 * PCI and standard ISA accessors 223 * 224 * Those are globally defined linux accessors for devices on PCI or ISA 225 * busses. They follow the Linux defined semantics. The current implementation 226 * for PowerPC is as close as possible to the x86 version of these, and thus 227 * provides fairly heavy weight barriers for the non-raw versions 228 * 229 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO 230 * allowing the platform to provide its own implementation of some or all 231 * of the accessors. 232 */ 233 234 /* 235 * Include the EEH definitions when EEH is enabled only so they don't get 236 * in the way when building for 32 bits 237 */ 238 #ifdef CONFIG_EEH 239 #include <asm/eeh.h> 240 #endif 241 242 /* Shortcut to the MMIO argument pointer */ 243 #define PCI_IO_ADDR volatile void __iomem * 244 245 /* Indirect IO address tokens: 246 * 247 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks 248 * on all IOs. (Note that this is all 64 bits only for now) 249 * 250 * To help platforms who may need to differenciate MMIO addresses in 251 * their hooks, a bitfield is reserved for use by the platform near the 252 * top of MMIO addresses (not PIO, those have to cope the hard way). 253 * 254 * This bit field is 12 bits and is at the top of the IO virtual 255 * addresses PCI_IO_INDIRECT_TOKEN_MASK. 256 * 257 * The kernel virtual space is thus: 258 * 259 * 0xD000000000000000 : vmalloc 260 * 0xD000080000000000 : PCI PHB IO space 261 * 0xD000080080000000 : ioremap 262 * 0xD0000fffffffffff : end of ioremap region 263 * 264 * Since the top 4 bits are reserved as the region ID, we use thus 265 * the next 12 bits and keep 4 bits available for the future if the 266 * virtual address space is ever to be extended. 267 * 268 * The direct IO mapping operations will then mask off those bits 269 * before doing the actual access, though that only happen when 270 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that 271 * mechanism 272 */ 273 274 #ifdef CONFIG_PPC_INDIRECT_IO 275 #define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul 276 #define PCI_IO_IND_TOKEN_SHIFT 48 277 #define PCI_FIX_ADDR(addr) \ 278 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK)) 279 #define PCI_GET_ADDR_TOKEN(addr) \ 280 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \ 281 PCI_IO_IND_TOKEN_SHIFT) 282 #define PCI_SET_ADDR_TOKEN(addr, token) \ 283 do { \ 284 unsigned long __a = (unsigned long)(addr); \ 285 __a &= ~PCI_IO_IND_TOKEN_MASK; \ 286 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \ 287 (addr) = (void __iomem *)__a; \ 288 } while(0) 289 #else 290 #define PCI_FIX_ADDR(addr) (addr) 291 #endif 292 293 294 /* 295 * Non ordered and non-swapping "raw" accessors 296 */ 297 298 static inline unsigned char __raw_readb(const volatile void __iomem *addr) 299 { 300 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr); 301 } 302 static inline unsigned short __raw_readw(const volatile void __iomem *addr) 303 { 304 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr); 305 } 306 static inline unsigned int __raw_readl(const volatile void __iomem *addr) 307 { 308 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr); 309 } 310 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 311 { 312 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v; 313 } 314 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 315 { 316 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v; 317 } 318 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 319 { 320 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v; 321 } 322 323 #ifdef __powerpc64__ 324 static inline unsigned long __raw_readq(const volatile void __iomem *addr) 325 { 326 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr); 327 } 328 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 329 { 330 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v; 331 } 332 #endif /* __powerpc64__ */ 333 334 /* 335 * 336 * PCI PIO and MMIO accessors. 337 * 338 * 339 * On 32 bits, PIO operations have a recovery mechanism in case they trigger 340 * machine checks (which they occasionally do when probing non existing 341 * IO ports on some platforms, like PowerMac and 8xx). 342 * I always found it to be of dubious reliability and I am tempted to get 343 * rid of it one of these days. So if you think it's important to keep it, 344 * please voice up asap. We never had it for 64 bits and I do not intend 345 * to port it over 346 */ 347 348 #ifdef CONFIG_PPC32 349 350 #define __do_in_asm(name, op) \ 351 static inline unsigned int name(unsigned int port) \ 352 { \ 353 unsigned int x; \ 354 __asm__ __volatile__( \ 355 "sync\n" \ 356 "0:" op " %0,0,%1\n" \ 357 "1: twi 0,%0,0\n" \ 358 "2: isync\n" \ 359 "3: nop\n" \ 360 "4:\n" \ 361 ".section .fixup,\"ax\"\n" \ 362 "5: li %0,-1\n" \ 363 " b 4b\n" \ 364 ".previous\n" \ 365 ".section __ex_table,\"a\"\n" \ 366 " .align 2\n" \ 367 " .long 0b,5b\n" \ 368 " .long 1b,5b\n" \ 369 " .long 2b,5b\n" \ 370 " .long 3b,5b\n" \ 371 ".previous" \ 372 : "=&r" (x) \ 373 : "r" (port + _IO_BASE) \ 374 : "memory"); \ 375 return x; \ 376 } 377 378 #define __do_out_asm(name, op) \ 379 static inline void name(unsigned int val, unsigned int port) \ 380 { \ 381 __asm__ __volatile__( \ 382 "sync\n" \ 383 "0:" op " %0,0,%1\n" \ 384 "1: sync\n" \ 385 "2:\n" \ 386 ".section __ex_table,\"a\"\n" \ 387 " .align 2\n" \ 388 " .long 0b,2b\n" \ 389 " .long 1b,2b\n" \ 390 ".previous" \ 391 : : "r" (val), "r" (port + _IO_BASE) \ 392 : "memory"); \ 393 } 394 395 __do_in_asm(_rec_inb, "lbzx") 396 __do_in_asm(_rec_inw, "lhbrx") 397 __do_in_asm(_rec_inl, "lwbrx") 398 __do_out_asm(_rec_outb, "stbx") 399 __do_out_asm(_rec_outw, "sthbrx") 400 __do_out_asm(_rec_outl, "stwbrx") 401 402 #endif /* CONFIG_PPC32 */ 403 404 /* The "__do_*" operations below provide the actual "base" implementation 405 * for each of the defined accessors. Some of them use the out_* functions 406 * directly, some of them still use EEH, though we might change that in the 407 * future. Those macros below provide the necessary argument swapping and 408 * handling of the IO base for PIO. 409 * 410 * They are themselves used by the macros that define the actual accessors 411 * and can be used by the hooks if any. 412 * 413 * Note that PIO operations are always defined in terms of their corresonding 414 * MMIO operations. That allows platforms like iSeries who want to modify the 415 * behaviour of both to only hook on the MMIO version and get both. It's also 416 * possible to hook directly at the toplevel PIO operation if they have to 417 * be handled differently 418 */ 419 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val) 420 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val) 421 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val) 422 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val) 423 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val) 424 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val) 425 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val) 426 427 #ifdef CONFIG_EEH 428 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr)) 429 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr)) 430 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr)) 431 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr)) 432 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr)) 433 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr)) 434 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr)) 435 #else /* CONFIG_EEH */ 436 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr)) 437 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr)) 438 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr)) 439 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr)) 440 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr)) 441 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr)) 442 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr)) 443 #endif /* !defined(CONFIG_EEH) */ 444 445 #ifdef CONFIG_PPC32 446 #define __do_outb(val, port) _rec_outb(val, port) 447 #define __do_outw(val, port) _rec_outw(val, port) 448 #define __do_outl(val, port) _rec_outl(val, port) 449 #define __do_inb(port) _rec_inb(port) 450 #define __do_inw(port) _rec_inw(port) 451 #define __do_inl(port) _rec_inl(port) 452 #else /* CONFIG_PPC32 */ 453 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port); 454 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port); 455 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port); 456 #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); 457 #define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port); 458 #define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port); 459 #endif /* !CONFIG_PPC32 */ 460 461 #ifdef CONFIG_EEH 462 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n)) 463 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n)) 464 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n)) 465 #else /* CONFIG_EEH */ 466 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n)) 467 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n)) 468 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n)) 469 #endif /* !CONFIG_EEH */ 470 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n)) 471 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n)) 472 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n)) 473 474 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 475 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 476 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n)) 477 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 478 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 479 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n)) 480 481 #define __do_memset_io(addr, c, n) \ 482 _memset_io(PCI_FIX_ADDR(addr), c, n) 483 #define __do_memcpy_toio(dst, src, n) \ 484 _memcpy_toio(PCI_FIX_ADDR(dst), src, n) 485 486 #ifdef CONFIG_EEH 487 #define __do_memcpy_fromio(dst, src, n) \ 488 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n) 489 #else /* CONFIG_EEH */ 490 #define __do_memcpy_fromio(dst, src, n) \ 491 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n) 492 #endif /* !CONFIG_EEH */ 493 494 #ifdef CONFIG_PPC_INDIRECT_PIO 495 #define DEF_PCI_HOOK_pio(x) x 496 #else 497 #define DEF_PCI_HOOK_pio(x) NULL 498 #endif 499 500 #ifdef CONFIG_PPC_INDIRECT_MMIO 501 #define DEF_PCI_HOOK_mem(x) x 502 #else 503 #define DEF_PCI_HOOK_mem(x) NULL 504 #endif 505 506 /* Structure containing all the hooks */ 507 extern struct ppc_pci_io { 508 509 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at; 510 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at; 511 512 #include <asm/io-defs.h> 513 514 #undef DEF_PCI_AC_RET 515 #undef DEF_PCI_AC_NORET 516 517 } ppc_pci_io; 518 519 /* The inline wrappers */ 520 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \ 521 static inline ret name at \ 522 { \ 523 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 524 return ppc_pci_io.name al; \ 525 return __do_##name al; \ 526 } 527 528 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \ 529 static inline void name at \ 530 { \ 531 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \ 532 ppc_pci_io.name al; \ 533 else \ 534 __do_##name al; \ 535 } 536 537 #include <asm/io-defs.h> 538 539 #undef DEF_PCI_AC_RET 540 #undef DEF_PCI_AC_NORET 541 542 /* Some drivers check for the presence of readq & writeq with 543 * a #ifdef, so we make them happy here. 544 */ 545 #ifdef __powerpc64__ 546 #define readq readq 547 #define writeq writeq 548 #endif 549 550 /* 551 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 552 * access 553 */ 554 #define xlate_dev_mem_ptr(p) __va(p) 555 556 /* 557 * Convert a virtual cached pointer to an uncached pointer 558 */ 559 #define xlate_dev_kmem_ptr(p) p 560 561 /* 562 * We don't do relaxed operations yet, at least not with this semantic 563 */ 564 #define readb_relaxed(addr) readb(addr) 565 #define readw_relaxed(addr) readw(addr) 566 #define readl_relaxed(addr) readl(addr) 567 #define readq_relaxed(addr) readq(addr) 568 569 #ifdef CONFIG_PPC32 570 #define mmiowb() 571 #else 572 /* 573 * Enforce synchronisation of stores vs. spin_unlock 574 * (this does it explicitly, though our implementation of spin_unlock 575 * does it implicitely too) 576 */ 577 static inline void mmiowb(void) 578 { 579 unsigned long tmp; 580 581 __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)" 582 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 583 : "memory"); 584 } 585 #endif /* !CONFIG_PPC32 */ 586 587 static inline void iosync(void) 588 { 589 __asm__ __volatile__ ("sync" : : : "memory"); 590 } 591 592 /* Enforce in-order execution of data I/O. 593 * No distinction between read/write on PPC; use eieio for all three. 594 * Those are fairly week though. They don't provide a barrier between 595 * MMIO and cacheable storage nor do they provide a barrier vs. locks, 596 * they only provide barriers between 2 __raw MMIO operations and 597 * possibly break write combining. 598 */ 599 #define iobarrier_rw() eieio() 600 #define iobarrier_r() eieio() 601 #define iobarrier_w() eieio() 602 603 604 /* 605 * output pause versions need a delay at least for the 606 * w83c105 ide controller in a p610. 607 */ 608 #define inb_p(port) inb(port) 609 #define outb_p(val, port) (udelay(1), outb((val), (port))) 610 #define inw_p(port) inw(port) 611 #define outw_p(val, port) (udelay(1), outw((val), (port))) 612 #define inl_p(port) inl(port) 613 #define outl_p(val, port) (udelay(1), outl((val), (port))) 614 615 616 #define IO_SPACE_LIMIT ~(0UL) 617 618 619 /** 620 * ioremap - map bus memory into CPU space 621 * @address: bus address of the memory 622 * @size: size of the resource to map 623 * 624 * ioremap performs a platform specific sequence of operations to 625 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 626 * writew/writel functions and the other mmio helpers. The returned 627 * address is not guaranteed to be usable directly as a virtual 628 * address. 629 * 630 * We provide a few variations of it: 631 * 632 * * ioremap is the standard one and provides non-cacheable guarded mappings 633 * and can be hooked by the platform via ppc_md 634 * 635 * * ioremap_prot allows to specify the page flags as an argument and can 636 * also be hooked by the platform via ppc_md. 637 * 638 * * ioremap_nocache is identical to ioremap 639 * 640 * * ioremap_wc enables write combining 641 * 642 * * iounmap undoes such a mapping and can be hooked 643 * 644 * * __ioremap_at (and the pending __iounmap_at) are low level functions to 645 * create hand-made mappings for use only by the PCI code and cannot 646 * currently be hooked. Must be page aligned. 647 * 648 * * __ioremap is the low level implementation used by ioremap and 649 * ioremap_prot and cannot be hooked (but can be used by a hook on one 650 * of the previous ones) 651 * 652 * * __ioremap_caller is the same as above but takes an explicit caller 653 * reference rather than using __builtin_return_address(0) 654 * 655 * * __iounmap, is the low level implementation used by iounmap and cannot 656 * be hooked (but can be used by a hook on iounmap) 657 * 658 */ 659 extern void __iomem *ioremap(phys_addr_t address, unsigned long size); 660 extern void __iomem *ioremap_prot(phys_addr_t address, unsigned long size, 661 unsigned long flags); 662 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size); 663 #define ioremap_nocache(addr, size) ioremap((addr), (size)) 664 665 extern void iounmap(volatile void __iomem *addr); 666 667 extern void __iomem *__ioremap(phys_addr_t, unsigned long size, 668 unsigned long flags); 669 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size, 670 unsigned long flags, void *caller); 671 672 extern void __iounmap(volatile void __iomem *addr); 673 674 extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea, 675 unsigned long size, unsigned long flags); 676 extern void __iounmap_at(void *ea, unsigned long size); 677 678 /* 679 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation 680 * which needs some additional definitions here. They basically allow PIO 681 * space overall to be 1GB. This will work as long as we never try to use 682 * iomap to map MMIO below 1GB which should be fine on ppc64 683 */ 684 #define HAVE_ARCH_PIO_SIZE 1 685 #define PIO_OFFSET 0x00000000UL 686 #define PIO_MASK (FULL_IO_SIZE - 1) 687 #define PIO_RESERVED (FULL_IO_SIZE) 688 689 #define mmio_read16be(addr) readw_be(addr) 690 #define mmio_read32be(addr) readl_be(addr) 691 #define mmio_write16be(val, addr) writew_be(val, addr) 692 #define mmio_write32be(val, addr) writel_be(val, addr) 693 #define mmio_insb(addr, dst, count) readsb(addr, dst, count) 694 #define mmio_insw(addr, dst, count) readsw(addr, dst, count) 695 #define mmio_insl(addr, dst, count) readsl(addr, dst, count) 696 #define mmio_outsb(addr, src, count) writesb(addr, src, count) 697 #define mmio_outsw(addr, src, count) writesw(addr, src, count) 698 #define mmio_outsl(addr, src, count) writesl(addr, src, count) 699 700 /** 701 * virt_to_phys - map virtual addresses to physical 702 * @address: address to remap 703 * 704 * The returned physical address is the physical (CPU) mapping for 705 * the memory address given. It is only valid to use this function on 706 * addresses directly mapped or allocated via kmalloc. 707 * 708 * This function does not give bus mappings for DMA transfers. In 709 * almost all conceivable cases a device driver should not be using 710 * this function 711 */ 712 static inline unsigned long virt_to_phys(volatile void * address) 713 { 714 return __pa((unsigned long)address); 715 } 716 717 /** 718 * phys_to_virt - map physical address to virtual 719 * @address: address to remap 720 * 721 * The returned virtual address is a current CPU mapping for 722 * the memory address given. It is only valid to use this function on 723 * addresses that have a kernel mapping 724 * 725 * This function does not handle bus mappings for DMA transfers. In 726 * almost all conceivable cases a device driver should not be using 727 * this function 728 */ 729 static inline void * phys_to_virt(unsigned long address) 730 { 731 return (void *)__va(address); 732 } 733 734 /* 735 * Change "struct page" to physical address. 736 */ 737 #define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT) 738 739 /* 740 * 32 bits still uses virt_to_bus() for it's implementation of DMA 741 * mappings se we have to keep it defined here. We also have some old 742 * drivers (shame shame shame) that use bus_to_virt() and haven't been 743 * fixed yet so I need to define it here. 744 */ 745 #ifdef CONFIG_PPC32 746 747 static inline unsigned long virt_to_bus(volatile void * address) 748 { 749 if (address == NULL) 750 return 0; 751 return __pa(address) + PCI_DRAM_OFFSET; 752 } 753 754 static inline void * bus_to_virt(unsigned long address) 755 { 756 if (address == 0) 757 return NULL; 758 return __va(address - PCI_DRAM_OFFSET); 759 } 760 761 #define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 762 763 #endif /* CONFIG_PPC32 */ 764 765 /* access ports */ 766 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) 767 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) 768 769 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) 770 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) 771 772 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) 773 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) 774 775 /* Clear and set bits in one shot. These macros can be used to clear and 776 * set multiple bits in a register using a single read-modify-write. These 777 * macros can also be used to set a multiple-bit bit pattern using a mask, 778 * by specifying the mask in the 'clear' parameter and the new bit pattern 779 * in the 'set' parameter. 780 */ 781 782 #define clrsetbits(type, addr, clear, set) \ 783 out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) 784 785 #ifdef __powerpc64__ 786 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set) 787 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set) 788 #endif 789 790 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) 791 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) 792 793 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) 794 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set) 795 796 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) 797 798 void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset, 799 size_t size, unsigned long flags); 800 801 #endif /* __KERNEL__ */ 802 803 #endif /* _ASM_POWERPC_IO_H */ 804